Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8295225 |
1 |
|
|
T22 |
52 |
|
T23 |
1430 |
|
T24 |
403 |
| auto[1] |
6336501 |
1 |
|
|
T22 |
24 |
|
T23 |
1293 |
|
T29 |
209 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12073931 |
1 |
|
|
T22 |
71 |
|
T23 |
1868 |
|
T24 |
403 |
| auto[1] |
2557795 |
1 |
|
|
T22 |
5 |
|
T23 |
855 |
|
T29 |
70 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8310504 |
1 |
|
|
T22 |
66 |
|
T23 |
947 |
|
T24 |
403 |
| auto[1] |
6321222 |
1 |
|
|
T22 |
10 |
|
T23 |
1776 |
|
T29 |
170 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1868826 |
1 |
|
|
T23 |
481 |
|
T29 |
36 |
|
T30 |
10 |
| auto[1] |
auto[0] |
auto[1] |
1271207 |
1 |
|
|
T22 |
5 |
|
T23 |
446 |
|
T29 |
46 |
| auto[1] |
auto[1] |
auto[0] |
1894601 |
1 |
|
|
T22 |
5 |
|
T23 |
440 |
|
T29 |
64 |
| auto[1] |
auto[1] |
auto[1] |
1286588 |
1 |
|
|
T23 |
409 |
|
T29 |
24 |
|
T1 |
36 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |