Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8294979 |
1 |
|
|
T22 |
59 |
|
T23 |
1309 |
|
T24 |
403 |
| auto[1] |
6336747 |
1 |
|
|
T22 |
17 |
|
T23 |
1414 |
|
T29 |
242 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12080681 |
1 |
|
|
T22 |
67 |
|
T23 |
1893 |
|
T24 |
403 |
| auto[1] |
2551045 |
1 |
|
|
T22 |
9 |
|
T23 |
830 |
|
T29 |
105 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8317837 |
1 |
|
|
T22 |
61 |
|
T23 |
1087 |
|
T24 |
403 |
| auto[1] |
6313889 |
1 |
|
|
T22 |
15 |
|
T23 |
1636 |
|
T29 |
176 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1877019 |
1 |
|
|
T22 |
6 |
|
T23 |
387 |
|
T29 |
34 |
| auto[1] |
auto[0] |
auto[1] |
1272266 |
1 |
|
|
T22 |
7 |
|
T23 |
364 |
|
T29 |
44 |
| auto[1] |
auto[1] |
auto[0] |
1885825 |
1 |
|
|
T23 |
419 |
|
T29 |
37 |
|
T30 |
4 |
| auto[1] |
auto[1] |
auto[1] |
1278779 |
1 |
|
|
T22 |
2 |
|
T23 |
466 |
|
T29 |
61 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |