Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8283816 |
1 |
|
|
T22 |
55 |
|
T23 |
1134 |
|
T24 |
403 |
| auto[1] |
6347910 |
1 |
|
|
T22 |
21 |
|
T23 |
1589 |
|
T29 |
234 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13822223 |
1 |
|
|
T22 |
76 |
|
T23 |
2476 |
|
T24 |
403 |
| auto[1] |
809503 |
1 |
|
|
T23 |
247 |
|
T29 |
9 |
|
T30 |
1 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8283579 |
1 |
|
|
T22 |
62 |
|
T23 |
1474 |
|
T24 |
403 |
| auto[1] |
6348147 |
1 |
|
|
T22 |
14 |
|
T23 |
1249 |
|
T29 |
211 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2753817 |
1 |
|
|
T22 |
6 |
|
T23 |
422 |
|
T29 |
108 |
| auto[1] |
auto[0] |
auto[1] |
401680 |
1 |
|
|
T23 |
106 |
|
T29 |
4 |
|
T30 |
1 |
| auto[1] |
auto[1] |
auto[0] |
2784827 |
1 |
|
|
T22 |
8 |
|
T23 |
580 |
|
T29 |
94 |
| auto[1] |
auto[1] |
auto[1] |
407823 |
1 |
|
|
T23 |
141 |
|
T29 |
5 |
|
T32 |
1 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |