Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8336126 |
1 |
|
|
T22 |
50 |
|
T23 |
1542 |
|
T24 |
403 |
| auto[1] |
6295600 |
1 |
|
|
T22 |
26 |
|
T23 |
1181 |
|
T29 |
205 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13829961 |
1 |
|
|
T22 |
76 |
|
T23 |
2456 |
|
T24 |
403 |
| auto[1] |
801765 |
1 |
|
|
T23 |
267 |
|
T29 |
9 |
|
T30 |
2 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8323548 |
1 |
|
|
T22 |
66 |
|
T23 |
1232 |
|
T24 |
403 |
| auto[1] |
6308178 |
1 |
|
|
T22 |
10 |
|
T23 |
1491 |
|
T29 |
199 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2763901 |
1 |
|
|
T22 |
5 |
|
T23 |
715 |
|
T29 |
82 |
| auto[1] |
auto[0] |
auto[1] |
401258 |
1 |
|
|
T23 |
150 |
|
T29 |
4 |
|
T30 |
1 |
| auto[1] |
auto[1] |
auto[0] |
2742512 |
1 |
|
|
T22 |
5 |
|
T23 |
509 |
|
T29 |
108 |
| auto[1] |
auto[1] |
auto[1] |
400507 |
1 |
|
|
T23 |
117 |
|
T29 |
5 |
|
T30 |
1 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |