Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8304742 |
1 |
|
|
T22 |
67 |
|
T23 |
1005 |
|
T24 |
403 |
| auto[1] |
6326984 |
1 |
|
|
T22 |
9 |
|
T23 |
1718 |
|
T29 |
197 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13824059 |
1 |
|
|
T22 |
76 |
|
T23 |
2421 |
|
T24 |
403 |
| auto[1] |
807667 |
1 |
|
|
T23 |
302 |
|
T29 |
10 |
|
T30 |
2 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8309189 |
1 |
|
|
T22 |
65 |
|
T23 |
1120 |
|
T24 |
403 |
| auto[1] |
6322537 |
1 |
|
|
T22 |
11 |
|
T23 |
1603 |
|
T29 |
230 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2764330 |
1 |
|
|
T22 |
8 |
|
T23 |
448 |
|
T29 |
107 |
| auto[1] |
auto[0] |
auto[1] |
403075 |
1 |
|
|
T23 |
107 |
|
T29 |
5 |
|
T30 |
2 |
| auto[1] |
auto[1] |
auto[0] |
2750540 |
1 |
|
|
T22 |
3 |
|
T23 |
853 |
|
T29 |
113 |
| auto[1] |
auto[1] |
auto[1] |
404592 |
1 |
|
|
T23 |
195 |
|
T29 |
5 |
|
T1 |
13 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |