Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8314778 |
1 |
|
|
T22 |
65 |
|
T23 |
1601 |
|
T24 |
403 |
| auto[1] |
6316948 |
1 |
|
|
T22 |
11 |
|
T23 |
1122 |
|
T29 |
244 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13828687 |
1 |
|
|
T22 |
76 |
|
T23 |
2469 |
|
T24 |
403 |
| auto[1] |
803039 |
1 |
|
|
T23 |
254 |
|
T29 |
8 |
|
T30 |
2 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8322563 |
1 |
|
|
T22 |
64 |
|
T23 |
1375 |
|
T24 |
403 |
| auto[1] |
6309163 |
1 |
|
|
T22 |
12 |
|
T23 |
1348 |
|
T29 |
225 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2749808 |
1 |
|
|
T22 |
10 |
|
T23 |
608 |
|
T29 |
71 |
| auto[1] |
auto[0] |
auto[1] |
399113 |
1 |
|
|
T23 |
149 |
|
T29 |
2 |
|
T30 |
2 |
| auto[1] |
auto[1] |
auto[0] |
2756316 |
1 |
|
|
T22 |
2 |
|
T23 |
486 |
|
T29 |
146 |
| auto[1] |
auto[1] |
auto[1] |
403926 |
1 |
|
|
T23 |
105 |
|
T29 |
6 |
|
T32 |
1 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |