Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.63 99.06 99.24 100.00 99.80 99.68 99.99


Total test records in report: 943
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T767 /workspace/coverage/cover_reg_top/3.gpio_tl_errors.1063291810 Jun 30 04:21:55 PM PDT 24 Jun 30 04:21:59 PM PDT 24 128929415 ps
T89 /workspace/coverage/cover_reg_top/0.gpio_same_csr_outstanding.4086531116 Jun 30 04:17:09 PM PDT 24 Jun 30 04:17:10 PM PDT 24 20153532 ps
T768 /workspace/coverage/cover_reg_top/3.gpio_csr_mem_rw_with_rand_reset.1437331770 Jun 30 04:21:03 PM PDT 24 Jun 30 04:21:06 PM PDT 24 162363827 ps
T769 /workspace/coverage/cover_reg_top/2.gpio_tl_intg_err.4180599640 Jun 30 04:21:52 PM PDT 24 Jun 30 04:21:54 PM PDT 24 85562831 ps
T770 /workspace/coverage/cover_reg_top/4.gpio_csr_aliasing.2509362093 Jun 30 04:21:55 PM PDT 24 Jun 30 04:21:57 PM PDT 24 21832191 ps
T771 /workspace/coverage/cover_reg_top/5.gpio_intr_test.3985365382 Jun 30 04:22:18 PM PDT 24 Jun 30 04:22:20 PM PDT 24 64917513 ps
T46 /workspace/coverage/cover_reg_top/0.gpio_tl_intg_err.1758869814 Jun 30 04:23:00 PM PDT 24 Jun 30 04:23:03 PM PDT 24 210049128 ps
T772 /workspace/coverage/cover_reg_top/16.gpio_intr_test.553978031 Jun 30 04:22:39 PM PDT 24 Jun 30 04:22:42 PM PDT 24 14455088 ps
T47 /workspace/coverage/cover_reg_top/3.gpio_tl_intg_err.1158075444 Jun 30 04:21:54 PM PDT 24 Jun 30 04:21:58 PM PDT 24 409527107 ps
T90 /workspace/coverage/cover_reg_top/18.gpio_same_csr_outstanding.1956481915 Jun 30 04:22:42 PM PDT 24 Jun 30 04:22:46 PM PDT 24 15417599 ps
T773 /workspace/coverage/cover_reg_top/12.gpio_csr_mem_rw_with_rand_reset.3504451932 Jun 30 04:22:01 PM PDT 24 Jun 30 04:22:03 PM PDT 24 51024122 ps
T75 /workspace/coverage/cover_reg_top/9.gpio_same_csr_outstanding.3170868338 Jun 30 04:20:02 PM PDT 24 Jun 30 04:20:03 PM PDT 24 21149008 ps
T774 /workspace/coverage/cover_reg_top/6.gpio_intr_test.2154163919 Jun 30 04:22:12 PM PDT 24 Jun 30 04:22:14 PM PDT 24 56078795 ps
T775 /workspace/coverage/cover_reg_top/14.gpio_tl_errors.1545467938 Jun 30 04:22:42 PM PDT 24 Jun 30 04:22:48 PM PDT 24 208289457 ps
T776 /workspace/coverage/cover_reg_top/45.gpio_intr_test.1579116175 Jun 30 04:22:50 PM PDT 24 Jun 30 04:22:52 PM PDT 24 15583300 ps
T777 /workspace/coverage/cover_reg_top/38.gpio_intr_test.2380563317 Jun 30 04:22:44 PM PDT 24 Jun 30 04:22:48 PM PDT 24 235721496 ps
T76 /workspace/coverage/cover_reg_top/18.gpio_csr_rw.2964056761 Jun 30 04:22:42 PM PDT 24 Jun 30 04:22:46 PM PDT 24 122343181 ps
T778 /workspace/coverage/cover_reg_top/26.gpio_intr_test.1891776081 Jun 30 04:22:38 PM PDT 24 Jun 30 04:22:40 PM PDT 24 53625014 ps
T77 /workspace/coverage/cover_reg_top/7.gpio_csr_rw.3615098602 Jun 30 04:22:12 PM PDT 24 Jun 30 04:22:14 PM PDT 24 28594390 ps
T779 /workspace/coverage/cover_reg_top/19.gpio_csr_mem_rw_with_rand_reset.1578339319 Jun 30 04:22:41 PM PDT 24 Jun 30 04:22:45 PM PDT 24 55760227 ps
T780 /workspace/coverage/cover_reg_top/29.gpio_intr_test.3997588121 Jun 30 04:22:42 PM PDT 24 Jun 30 04:22:46 PM PDT 24 53092022 ps
T781 /workspace/coverage/cover_reg_top/0.gpio_intr_test.1017504201 Jun 30 04:22:43 PM PDT 24 Jun 30 04:22:47 PM PDT 24 117233442 ps
T782 /workspace/coverage/cover_reg_top/1.gpio_intr_test.473028787 Jun 30 04:22:38 PM PDT 24 Jun 30 04:22:40 PM PDT 24 18305383 ps
T783 /workspace/coverage/cover_reg_top/4.gpio_tl_errors.4086435402 Jun 30 04:22:15 PM PDT 24 Jun 30 04:22:19 PM PDT 24 187392775 ps
T109 /workspace/coverage/cover_reg_top/9.gpio_tl_intg_err.1084513928 Jun 30 04:21:52 PM PDT 24 Jun 30 04:21:54 PM PDT 24 120902535 ps
T784 /workspace/coverage/cover_reg_top/24.gpio_intr_test.1549769217 Jun 30 04:22:41 PM PDT 24 Jun 30 04:22:44 PM PDT 24 14418837 ps
T78 /workspace/coverage/cover_reg_top/2.gpio_same_csr_outstanding.1067042381 Jun 30 04:20:32 PM PDT 24 Jun 30 04:20:33 PM PDT 24 34568985 ps
T785 /workspace/coverage/cover_reg_top/5.gpio_tl_intg_err.1862160374 Jun 30 04:22:30 PM PDT 24 Jun 30 04:22:32 PM PDT 24 623841812 ps
T786 /workspace/coverage/cover_reg_top/8.gpio_intr_test.3671937120 Jun 30 04:21:53 PM PDT 24 Jun 30 04:21:55 PM PDT 24 21579119 ps
T787 /workspace/coverage/cover_reg_top/13.gpio_csr_rw.3466754114 Jun 30 04:22:37 PM PDT 24 Jun 30 04:22:39 PM PDT 24 42849313 ps
T788 /workspace/coverage/cover_reg_top/4.gpio_csr_rw.3229812546 Jun 30 04:20:59 PM PDT 24 Jun 30 04:21:00 PM PDT 24 15363141 ps
T79 /workspace/coverage/cover_reg_top/2.gpio_csr_aliasing.2656991012 Jun 30 04:22:36 PM PDT 24 Jun 30 04:22:38 PM PDT 24 99607237 ps
T789 /workspace/coverage/cover_reg_top/18.gpio_tl_errors.529780573 Jun 30 04:22:42 PM PDT 24 Jun 30 04:22:46 PM PDT 24 29983047 ps
T790 /workspace/coverage/cover_reg_top/15.gpio_csr_rw.2509305867 Jun 30 04:22:40 PM PDT 24 Jun 30 04:22:43 PM PDT 24 23267495 ps
T791 /workspace/coverage/cover_reg_top/7.gpio_intr_test.3553184914 Jun 30 04:18:18 PM PDT 24 Jun 30 04:18:19 PM PDT 24 11490484 ps
T792 /workspace/coverage/cover_reg_top/11.gpio_tl_intg_err.579957290 Jun 30 04:21:55 PM PDT 24 Jun 30 04:21:58 PM PDT 24 246362208 ps
T793 /workspace/coverage/cover_reg_top/19.gpio_tl_intg_err.341602361 Jun 30 04:22:36 PM PDT 24 Jun 30 04:22:38 PM PDT 24 262581451 ps
T794 /workspace/coverage/cover_reg_top/5.gpio_tl_errors.2909908307 Jun 30 04:22:18 PM PDT 24 Jun 30 04:22:22 PM PDT 24 242877766 ps
T795 /workspace/coverage/cover_reg_top/2.gpio_tl_errors.1031779922 Jun 30 04:22:49 PM PDT 24 Jun 30 04:22:52 PM PDT 24 226732970 ps
T796 /workspace/coverage/cover_reg_top/21.gpio_intr_test.3530786817 Jun 30 04:22:43 PM PDT 24 Jun 30 04:22:47 PM PDT 24 14041295 ps
T91 /workspace/coverage/cover_reg_top/7.gpio_same_csr_outstanding.1960290524 Jun 30 04:22:10 PM PDT 24 Jun 30 04:22:13 PM PDT 24 45249404 ps
T80 /workspace/coverage/cover_reg_top/0.gpio_csr_rw.1090187459 Jun 30 04:21:06 PM PDT 24 Jun 30 04:21:07 PM PDT 24 11224644 ps
T797 /workspace/coverage/cover_reg_top/39.gpio_intr_test.2547674939 Jun 30 04:22:47 PM PDT 24 Jun 30 04:22:50 PM PDT 24 23266462 ps
T798 /workspace/coverage/cover_reg_top/15.gpio_csr_mem_rw_with_rand_reset.665317139 Jun 30 04:22:54 PM PDT 24 Jun 30 04:22:58 PM PDT 24 34921352 ps
T799 /workspace/coverage/cover_reg_top/10.gpio_intr_test.2156168501 Jun 30 04:21:54 PM PDT 24 Jun 30 04:21:57 PM PDT 24 93133719 ps
T800 /workspace/coverage/cover_reg_top/27.gpio_intr_test.3836881700 Jun 30 04:22:49 PM PDT 24 Jun 30 04:22:51 PM PDT 24 21074527 ps
T81 /workspace/coverage/cover_reg_top/4.gpio_csr_hw_reset.1161708513 Jun 30 04:22:16 PM PDT 24 Jun 30 04:22:18 PM PDT 24 14070212 ps
T801 /workspace/coverage/cover_reg_top/15.gpio_intr_test.1475466192 Jun 30 04:22:38 PM PDT 24 Jun 30 04:22:40 PM PDT 24 11742620 ps
T802 /workspace/coverage/cover_reg_top/19.gpio_intr_test.781446869 Jun 30 04:22:54 PM PDT 24 Jun 30 04:22:58 PM PDT 24 25235742 ps
T803 /workspace/coverage/cover_reg_top/11.gpio_same_csr_outstanding.3195685438 Jun 30 04:22:15 PM PDT 24 Jun 30 04:22:16 PM PDT 24 20461851 ps
T804 /workspace/coverage/cover_reg_top/5.gpio_csr_rw.3542572621 Jun 30 04:18:57 PM PDT 24 Jun 30 04:18:58 PM PDT 24 44426751 ps
T805 /workspace/coverage/cover_reg_top/3.gpio_csr_aliasing.2697225415 Jun 30 04:22:35 PM PDT 24 Jun 30 04:22:37 PM PDT 24 36054874 ps
T806 /workspace/coverage/cover_reg_top/14.gpio_same_csr_outstanding.3767380972 Jun 30 04:22:40 PM PDT 24 Jun 30 04:22:43 PM PDT 24 32473278 ps
T807 /workspace/coverage/cover_reg_top/19.gpio_same_csr_outstanding.134537090 Jun 30 04:22:38 PM PDT 24 Jun 30 04:22:41 PM PDT 24 26961014 ps
T83 /workspace/coverage/cover_reg_top/0.gpio_csr_hw_reset.2667737022 Jun 30 04:22:51 PM PDT 24 Jun 30 04:22:53 PM PDT 24 20343963 ps
T808 /workspace/coverage/cover_reg_top/2.gpio_intr_test.2239767405 Jun 30 04:20:30 PM PDT 24 Jun 30 04:20:31 PM PDT 24 10580531 ps
T809 /workspace/coverage/cover_reg_top/41.gpio_intr_test.187216543 Jun 30 04:22:41 PM PDT 24 Jun 30 04:22:45 PM PDT 24 47213167 ps
T810 /workspace/coverage/cover_reg_top/10.gpio_tl_intg_err.4163723266 Jun 30 04:21:55 PM PDT 24 Jun 30 04:21:58 PM PDT 24 389542369 ps
T811 /workspace/coverage/cover_reg_top/1.gpio_csr_mem_rw_with_rand_reset.3796792760 Jun 30 04:22:38 PM PDT 24 Jun 30 04:22:40 PM PDT 24 30226758 ps
T812 /workspace/coverage/cover_reg_top/2.gpio_csr_bit_bash.2921498786 Jun 30 04:20:04 PM PDT 24 Jun 30 04:20:07 PM PDT 24 1549321096 ps
T813 /workspace/coverage/cover_reg_top/17.gpio_csr_rw.554975479 Jun 30 04:22:37 PM PDT 24 Jun 30 04:22:38 PM PDT 24 12739612 ps
T814 /workspace/coverage/cover_reg_top/19.gpio_csr_rw.25192735 Jun 30 04:22:54 PM PDT 24 Jun 30 04:22:57 PM PDT 24 12781543 ps
T82 /workspace/coverage/cover_reg_top/12.gpio_csr_rw.569448955 Jun 30 04:21:57 PM PDT 24 Jun 30 04:21:59 PM PDT 24 16443427 ps
T815 /workspace/coverage/cover_reg_top/40.gpio_intr_test.3324609723 Jun 30 04:22:50 PM PDT 24 Jun 30 04:22:52 PM PDT 24 22873605 ps
T816 /workspace/coverage/cover_reg_top/2.gpio_csr_hw_reset.1216037625 Jun 30 04:23:09 PM PDT 24 Jun 30 04:23:10 PM PDT 24 23933594 ps
T817 /workspace/coverage/cover_reg_top/4.gpio_intr_test.1943318643 Jun 30 04:22:01 PM PDT 24 Jun 30 04:22:02 PM PDT 24 29101881 ps
T818 /workspace/coverage/cover_reg_top/8.gpio_same_csr_outstanding.416081942 Jun 30 04:22:18 PM PDT 24 Jun 30 04:22:20 PM PDT 24 98721732 ps
T819 /workspace/coverage/cover_reg_top/3.gpio_intr_test.1717316915 Jun 30 04:22:09 PM PDT 24 Jun 30 04:22:12 PM PDT 24 108341566 ps
T820 /workspace/coverage/cover_reg_top/8.gpio_tl_errors.2635075112 Jun 30 04:22:06 PM PDT 24 Jun 30 04:22:09 PM PDT 24 24203445 ps
T821 /workspace/coverage/cover_reg_top/1.gpio_csr_bit_bash.2042953902 Jun 30 04:20:29 PM PDT 24 Jun 30 04:20:31 PM PDT 24 37022299 ps
T822 /workspace/coverage/cover_reg_top/16.gpio_csr_mem_rw_with_rand_reset.3990194169 Jun 30 04:22:38 PM PDT 24 Jun 30 04:22:40 PM PDT 24 15198735 ps
T823 /workspace/coverage/cover_reg_top/47.gpio_intr_test.3697200830 Jun 30 04:22:44 PM PDT 24 Jun 30 04:22:48 PM PDT 24 13462732 ps
T824 /workspace/coverage/cover_reg_top/5.gpio_csr_mem_rw_with_rand_reset.1497765905 Jun 30 04:20:42 PM PDT 24 Jun 30 04:20:43 PM PDT 24 44864254 ps
T825 /workspace/coverage/cover_reg_top/15.gpio_tl_intg_err.3723329272 Jun 30 04:22:36 PM PDT 24 Jun 30 04:22:38 PM PDT 24 457983709 ps
T826 /workspace/coverage/cover_reg_top/17.gpio_same_csr_outstanding.1265092356 Jun 30 04:22:38 PM PDT 24 Jun 30 04:22:41 PM PDT 24 27637819 ps
T827 /workspace/coverage/cover_reg_top/17.gpio_tl_errors.1060122844 Jun 30 04:22:54 PM PDT 24 Jun 30 04:22:59 PM PDT 24 72524509 ps
T828 /workspace/coverage/cover_reg_top/6.gpio_same_csr_outstanding.396957779 Jun 30 04:22:05 PM PDT 24 Jun 30 04:22:07 PM PDT 24 51441463 ps
T829 /workspace/coverage/cover_reg_top/10.gpio_tl_errors.362319366 Jun 30 04:20:22 PM PDT 24 Jun 30 04:20:24 PM PDT 24 461849276 ps
T830 /workspace/coverage/cover_reg_top/15.gpio_same_csr_outstanding.348050977 Jun 30 04:22:40 PM PDT 24 Jun 30 04:22:44 PM PDT 24 34658297 ps
T831 /workspace/coverage/cover_reg_top/3.gpio_csr_rw.1031062945 Jun 30 04:18:29 PM PDT 24 Jun 30 04:18:30 PM PDT 24 58828671 ps
T832 /workspace/coverage/cover_reg_top/6.gpio_tl_errors.3248369674 Jun 30 04:22:12 PM PDT 24 Jun 30 04:22:15 PM PDT 24 48073573 ps
T833 /workspace/coverage/cover_reg_top/37.gpio_intr_test.3751092462 Jun 30 04:22:46 PM PDT 24 Jun 30 04:22:49 PM PDT 24 11123664 ps
T834 /workspace/coverage/cover_reg_top/30.gpio_intr_test.4208281646 Jun 30 04:22:50 PM PDT 24 Jun 30 04:22:52 PM PDT 24 12395090 ps
T835 /workspace/coverage/cover_reg_top/6.gpio_tl_intg_err.2575709462 Jun 30 04:18:47 PM PDT 24 Jun 30 04:18:48 PM PDT 24 302164285 ps
T836 /workspace/coverage/cover_reg_top/8.gpio_tl_intg_err.1448375329 Jun 30 04:18:59 PM PDT 24 Jun 30 04:19:00 PM PDT 24 42190356 ps
T837 /workspace/coverage/cover_reg_top/5.gpio_same_csr_outstanding.2237872022 Jun 30 04:18:57 PM PDT 24 Jun 30 04:18:58 PM PDT 24 96960972 ps
T838 /workspace/coverage/cover_reg_top/0.gpio_csr_mem_rw_with_rand_reset.1078560261 Jun 30 04:20:07 PM PDT 24 Jun 30 04:20:08 PM PDT 24 18371569 ps
T84 /workspace/coverage/cover_reg_top/9.gpio_csr_rw.2108701300 Jun 30 04:20:04 PM PDT 24 Jun 30 04:20:05 PM PDT 24 52146889 ps
T839 /workspace/coverage/cover_reg_top/12.gpio_same_csr_outstanding.3571660106 Jun 30 04:20:59 PM PDT 24 Jun 30 04:21:00 PM PDT 24 270422307 ps
T840 /workspace/coverage/cover_reg_top/16.gpio_same_csr_outstanding.1129589143 Jun 30 04:22:54 PM PDT 24 Jun 30 04:22:58 PM PDT 24 36356757 ps
T841 /workspace/coverage/cover_reg_top/9.gpio_csr_mem_rw_with_rand_reset.1586934280 Jun 30 04:23:08 PM PDT 24 Jun 30 04:23:09 PM PDT 24 20830978 ps
T842 /workspace/coverage/cover_reg_top/4.gpio_tl_intg_err.224169766 Jun 30 04:21:54 PM PDT 24 Jun 30 04:21:57 PM PDT 24 55239891 ps
T843 /workspace/coverage/cover_reg_top/2.gpio_csr_rw.2959875344 Jun 30 04:22:50 PM PDT 24 Jun 30 04:22:53 PM PDT 24 13589903 ps
T844 /workspace/coverage/en_cdc_prims/14.gpio_smoke_en_cdc_prim.1034745129 Jun 30 04:22:00 PM PDT 24 Jun 30 04:22:02 PM PDT 24 30855082 ps
T845 /workspace/coverage/en_cdc_prims/17.gpio_smoke_en_cdc_prim.1356828487 Jun 30 04:20:17 PM PDT 24 Jun 30 04:20:18 PM PDT 24 52865010 ps
T846 /workspace/coverage/en_cdc_prims/26.gpio_smoke_en_cdc_prim.4117752282 Jun 30 04:22:06 PM PDT 24 Jun 30 04:22:09 PM PDT 24 87453469 ps
T847 /workspace/coverage/en_cdc_prims/38.gpio_smoke_no_pullup_pulldown_en_cdc_prim.361497933 Jun 30 04:19:58 PM PDT 24 Jun 30 04:19:59 PM PDT 24 65467045 ps
T848 /workspace/coverage/en_cdc_prims/42.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2256784556 Jun 30 04:22:42 PM PDT 24 Jun 30 04:22:46 PM PDT 24 304694093 ps
T849 /workspace/coverage/en_cdc_prims/44.gpio_smoke_en_cdc_prim.757481778 Jun 30 04:19:44 PM PDT 24 Jun 30 04:19:45 PM PDT 24 136757638 ps
T850 /workspace/coverage/en_cdc_prims/8.gpio_smoke_no_pullup_pulldown_en_cdc_prim.671155033 Jun 30 04:20:47 PM PDT 24 Jun 30 04:20:48 PM PDT 24 131272594 ps
T851 /workspace/coverage/en_cdc_prims/9.gpio_smoke_en_cdc_prim.2088233003 Jun 30 04:22:09 PM PDT 24 Jun 30 04:22:12 PM PDT 24 106674096 ps
T852 /workspace/coverage/en_cdc_prims/46.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1161655678 Jun 30 04:22:46 PM PDT 24 Jun 30 04:22:49 PM PDT 24 266238175 ps
T853 /workspace/coverage/en_cdc_prims/49.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3106697753 Jun 30 04:22:45 PM PDT 24 Jun 30 04:22:49 PM PDT 24 47734353 ps
T854 /workspace/coverage/en_cdc_prims/16.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2531144917 Jun 30 04:20:37 PM PDT 24 Jun 30 04:20:39 PM PDT 24 80633442 ps
T855 /workspace/coverage/en_cdc_prims/34.gpio_smoke_en_cdc_prim.190872353 Jun 30 04:20:07 PM PDT 24 Jun 30 04:20:08 PM PDT 24 210713644 ps
T856 /workspace/coverage/en_cdc_prims/15.gpio_smoke_en_cdc_prim.2879458930 Jun 30 04:22:09 PM PDT 24 Jun 30 04:22:12 PM PDT 24 93409982 ps
T857 /workspace/coverage/en_cdc_prims/25.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2326192310 Jun 30 04:19:21 PM PDT 24 Jun 30 04:19:22 PM PDT 24 51877253 ps
T858 /workspace/coverage/en_cdc_prims/21.gpio_smoke_en_cdc_prim.1673236069 Jun 30 04:22:52 PM PDT 24 Jun 30 04:22:55 PM PDT 24 201606293 ps
T859 /workspace/coverage/en_cdc_prims/20.gpio_smoke_no_pullup_pulldown_en_cdc_prim.195523641 Jun 30 04:18:49 PM PDT 24 Jun 30 04:18:51 PM PDT 24 343614462 ps
T860 /workspace/coverage/en_cdc_prims/10.gpio_smoke_en_cdc_prim.3648628906 Jun 30 04:20:18 PM PDT 24 Jun 30 04:20:20 PM PDT 24 36868004 ps
T861 /workspace/coverage/en_cdc_prims/48.gpio_smoke_en_cdc_prim.2829948219 Jun 30 04:22:56 PM PDT 24 Jun 30 04:22:59 PM PDT 24 47711706 ps
T862 /workspace/coverage/en_cdc_prims/34.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1076558090 Jun 30 04:22:07 PM PDT 24 Jun 30 04:22:09 PM PDT 24 106039415 ps
T863 /workspace/coverage/en_cdc_prims/46.gpio_smoke_en_cdc_prim.3060270906 Jun 30 04:22:48 PM PDT 24 Jun 30 04:22:51 PM PDT 24 170889241 ps
T864 /workspace/coverage/en_cdc_prims/2.gpio_smoke_en_cdc_prim.1259775910 Jun 30 04:17:05 PM PDT 24 Jun 30 04:17:07 PM PDT 24 154092041 ps
T865 /workspace/coverage/en_cdc_prims/0.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1069643652 Jun 30 04:17:33 PM PDT 24 Jun 30 04:17:35 PM PDT 24 132889852 ps
T866 /workspace/coverage/en_cdc_prims/13.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1022845849 Jun 30 04:22:06 PM PDT 24 Jun 30 04:22:09 PM PDT 24 199507339 ps
T867 /workspace/coverage/en_cdc_prims/15.gpio_smoke_no_pullup_pulldown_en_cdc_prim.833227144 Jun 30 04:22:12 PM PDT 24 Jun 30 04:22:14 PM PDT 24 172668075 ps
T868 /workspace/coverage/en_cdc_prims/27.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2563282677 Jun 30 04:22:06 PM PDT 24 Jun 30 04:22:10 PM PDT 24 135849461 ps
T869 /workspace/coverage/en_cdc_prims/41.gpio_smoke_en_cdc_prim.242095037 Jun 30 04:22:12 PM PDT 24 Jun 30 04:22:14 PM PDT 24 255161762 ps
T870 /workspace/coverage/en_cdc_prims/36.gpio_smoke_en_cdc_prim.2600197349 Jun 30 04:22:06 PM PDT 24 Jun 30 04:22:08 PM PDT 24 180294445 ps
T871 /workspace/coverage/en_cdc_prims/4.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1997726384 Jun 30 04:18:16 PM PDT 24 Jun 30 04:18:18 PM PDT 24 80090921 ps
T872 /workspace/coverage/en_cdc_prims/13.gpio_smoke_en_cdc_prim.4263145252 Jun 30 04:22:53 PM PDT 24 Jun 30 04:22:56 PM PDT 24 38535793 ps
T873 /workspace/coverage/en_cdc_prims/32.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2468638602 Jun 30 04:22:15 PM PDT 24 Jun 30 04:22:18 PM PDT 24 73585501 ps
T874 /workspace/coverage/en_cdc_prims/37.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1018328091 Jun 30 04:22:39 PM PDT 24 Jun 30 04:22:42 PM PDT 24 302332951 ps
T875 /workspace/coverage/en_cdc_prims/4.gpio_smoke_en_cdc_prim.2909541633 Jun 30 04:18:24 PM PDT 24 Jun 30 04:18:25 PM PDT 24 95508987 ps
T876 /workspace/coverage/en_cdc_prims/5.gpio_smoke_en_cdc_prim.2760857381 Jun 30 04:17:40 PM PDT 24 Jun 30 04:17:41 PM PDT 24 108782019 ps
T877 /workspace/coverage/en_cdc_prims/40.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3669231047 Jun 30 04:22:27 PM PDT 24 Jun 30 04:22:29 PM PDT 24 104297205 ps
T878 /workspace/coverage/en_cdc_prims/21.gpio_smoke_no_pullup_pulldown_en_cdc_prim.856051721 Jun 30 04:21:52 PM PDT 24 Jun 30 04:21:54 PM PDT 24 73300216 ps
T879 /workspace/coverage/en_cdc_prims/44.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3033542364 Jun 30 04:22:18 PM PDT 24 Jun 30 04:22:20 PM PDT 24 199535450 ps
T880 /workspace/coverage/en_cdc_prims/47.gpio_smoke_en_cdc_prim.4292385809 Jun 30 04:22:45 PM PDT 24 Jun 30 04:22:49 PM PDT 24 60210730 ps
T881 /workspace/coverage/en_cdc_prims/40.gpio_smoke_en_cdc_prim.161502148 Jun 30 04:21:56 PM PDT 24 Jun 30 04:21:59 PM PDT 24 106038499 ps
T882 /workspace/coverage/en_cdc_prims/11.gpio_smoke_en_cdc_prim.759283829 Jun 30 04:21:50 PM PDT 24 Jun 30 04:21:52 PM PDT 24 104361142 ps
T883 /workspace/coverage/en_cdc_prims/33.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1449189643 Jun 30 04:19:33 PM PDT 24 Jun 30 04:19:34 PM PDT 24 21746610 ps
T884 /workspace/coverage/en_cdc_prims/25.gpio_smoke_en_cdc_prim.3923282534 Jun 30 04:18:29 PM PDT 24 Jun 30 04:18:31 PM PDT 24 258941790 ps
T885 /workspace/coverage/en_cdc_prims/11.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3755991969 Jun 30 04:22:47 PM PDT 24 Jun 30 04:22:51 PM PDT 24 91542313 ps
T886 /workspace/coverage/en_cdc_prims/18.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3006183904 Jun 30 04:18:57 PM PDT 24 Jun 30 04:18:58 PM PDT 24 134475533 ps
T887 /workspace/coverage/en_cdc_prims/32.gpio_smoke_en_cdc_prim.3587205588 Jun 30 04:22:01 PM PDT 24 Jun 30 04:22:03 PM PDT 24 82001777 ps
T888 /workspace/coverage/en_cdc_prims/48.gpio_smoke_no_pullup_pulldown_en_cdc_prim.70436908 Jun 30 04:22:48 PM PDT 24 Jun 30 04:22:51 PM PDT 24 75172179 ps
T889 /workspace/coverage/en_cdc_prims/45.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3645766132 Jun 30 04:22:42 PM PDT 24 Jun 30 04:22:47 PM PDT 24 120933788 ps
T890 /workspace/coverage/en_cdc_prims/43.gpio_smoke_en_cdc_prim.2875942793 Jun 30 04:18:56 PM PDT 24 Jun 30 04:18:58 PM PDT 24 42396256 ps
T891 /workspace/coverage/en_cdc_prims/0.gpio_smoke_en_cdc_prim.855058604 Jun 30 04:17:52 PM PDT 24 Jun 30 04:17:54 PM PDT 24 102565125 ps
T892 /workspace/coverage/en_cdc_prims/42.gpio_smoke_en_cdc_prim.1425137303 Jun 30 04:20:16 PM PDT 24 Jun 30 04:20:18 PM PDT 24 91293778 ps
T893 /workspace/coverage/en_cdc_prims/10.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2852233920 Jun 30 04:22:16 PM PDT 24 Jun 30 04:22:18 PM PDT 24 77415124 ps
T894 /workspace/coverage/en_cdc_prims/30.gpio_smoke_en_cdc_prim.3838715977 Jun 30 04:22:00 PM PDT 24 Jun 30 04:22:02 PM PDT 24 20174658 ps
T895 /workspace/coverage/en_cdc_prims/41.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2956799599 Jun 30 04:22:27 PM PDT 24 Jun 30 04:22:28 PM PDT 24 47235863 ps
T896 /workspace/coverage/en_cdc_prims/23.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3952963022 Jun 30 04:21:52 PM PDT 24 Jun 30 04:21:54 PM PDT 24 63330535 ps
T897 /workspace/coverage/en_cdc_prims/19.gpio_smoke_en_cdc_prim.197937118 Jun 30 04:22:13 PM PDT 24 Jun 30 04:22:15 PM PDT 24 108477848 ps
T898 /workspace/coverage/en_cdc_prims/18.gpio_smoke_en_cdc_prim.2493231678 Jun 30 04:20:15 PM PDT 24 Jun 30 04:20:17 PM PDT 24 219255538 ps
T899 /workspace/coverage/en_cdc_prims/38.gpio_smoke_en_cdc_prim.3132332249 Jun 30 04:18:55 PM PDT 24 Jun 30 04:18:56 PM PDT 24 101565234 ps
T900 /workspace/coverage/en_cdc_prims/5.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3082573709 Jun 30 04:22:10 PM PDT 24 Jun 30 04:22:13 PM PDT 24 220133541 ps
T901 /workspace/coverage/en_cdc_prims/6.gpio_smoke_en_cdc_prim.1700594167 Jun 30 04:19:45 PM PDT 24 Jun 30 04:19:47 PM PDT 24 242572533 ps
T902 /workspace/coverage/en_cdc_prims/7.gpio_smoke_no_pullup_pulldown_en_cdc_prim.424168444 Jun 30 04:17:56 PM PDT 24 Jun 30 04:17:57 PM PDT 24 82368874 ps
T903 /workspace/coverage/en_cdc_prims/12.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2885320086 Jun 30 04:19:25 PM PDT 24 Jun 30 04:19:27 PM PDT 24 1065137409 ps
T904 /workspace/coverage/en_cdc_prims/19.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1178044105 Jun 30 04:22:56 PM PDT 24 Jun 30 04:22:59 PM PDT 24 71293564 ps
T905 /workspace/coverage/en_cdc_prims/22.gpio_smoke_en_cdc_prim.3600393809 Jun 30 04:23:10 PM PDT 24 Jun 30 04:23:11 PM PDT 24 77842756 ps
T906 /workspace/coverage/en_cdc_prims/29.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3735530722 Jun 30 04:22:15 PM PDT 24 Jun 30 04:22:17 PM PDT 24 87095482 ps
T907 /workspace/coverage/en_cdc_prims/27.gpio_smoke_en_cdc_prim.2001527571 Jun 30 04:21:07 PM PDT 24 Jun 30 04:21:08 PM PDT 24 47997906 ps
T908 /workspace/coverage/en_cdc_prims/49.gpio_smoke_en_cdc_prim.1268656005 Jun 30 04:22:56 PM PDT 24 Jun 30 04:23:00 PM PDT 24 100524595 ps
T909 /workspace/coverage/en_cdc_prims/30.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1657113688 Jun 30 04:19:45 PM PDT 24 Jun 30 04:19:46 PM PDT 24 106813877 ps
T910 /workspace/coverage/en_cdc_prims/43.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2256197736 Jun 30 04:22:13 PM PDT 24 Jun 30 04:22:15 PM PDT 24 89881288 ps
T911 /workspace/coverage/en_cdc_prims/35.gpio_smoke_en_cdc_prim.3486286388 Jun 30 04:22:05 PM PDT 24 Jun 30 04:22:07 PM PDT 24 29453234 ps
T912 /workspace/coverage/en_cdc_prims/12.gpio_smoke_en_cdc_prim.3922297999 Jun 30 04:22:47 PM PDT 24 Jun 30 04:22:50 PM PDT 24 298362927 ps
T913 /workspace/coverage/en_cdc_prims/33.gpio_smoke_en_cdc_prim.314263854 Jun 30 04:19:34 PM PDT 24 Jun 30 04:19:35 PM PDT 24 34048277 ps
T914 /workspace/coverage/en_cdc_prims/37.gpio_smoke_en_cdc_prim.2637164660 Jun 30 04:19:51 PM PDT 24 Jun 30 04:19:52 PM PDT 24 21839226 ps
T915 /workspace/coverage/en_cdc_prims/31.gpio_smoke_en_cdc_prim.439045383 Jun 30 04:18:56 PM PDT 24 Jun 30 04:18:58 PM PDT 24 35619105 ps
T916 /workspace/coverage/en_cdc_prims/1.gpio_smoke_en_cdc_prim.251511797 Jun 30 04:20:47 PM PDT 24 Jun 30 04:20:48 PM PDT 24 79825636 ps
T917 /workspace/coverage/en_cdc_prims/14.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3121563735 Jun 30 04:19:20 PM PDT 24 Jun 30 04:19:22 PM PDT 24 48692650 ps
T918 /workspace/coverage/en_cdc_prims/23.gpio_smoke_en_cdc_prim.3436535455 Jun 30 04:21:52 PM PDT 24 Jun 30 04:21:54 PM PDT 24 204235277 ps
T919 /workspace/coverage/en_cdc_prims/3.gpio_smoke_en_cdc_prim.2518662474 Jun 30 04:18:47 PM PDT 24 Jun 30 04:18:49 PM PDT 24 42220572 ps
T920 /workspace/coverage/en_cdc_prims/8.gpio_smoke_en_cdc_prim.1393602943 Jun 30 04:20:50 PM PDT 24 Jun 30 04:20:52 PM PDT 24 237985923 ps
T921 /workspace/coverage/en_cdc_prims/28.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1799942246 Jun 30 04:22:15 PM PDT 24 Jun 30 04:22:17 PM PDT 24 54154931 ps
T922 /workspace/coverage/en_cdc_prims/24.gpio_smoke_en_cdc_prim.2850463682 Jun 30 04:19:11 PM PDT 24 Jun 30 04:19:12 PM PDT 24 41561526 ps
T923 /workspace/coverage/en_cdc_prims/31.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2544661167 Jun 30 04:20:49 PM PDT 24 Jun 30 04:20:50 PM PDT 24 168471369 ps
T924 /workspace/coverage/en_cdc_prims/3.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3029269052 Jun 30 04:18:16 PM PDT 24 Jun 30 04:18:18 PM PDT 24 77075950 ps
T925 /workspace/coverage/en_cdc_prims/20.gpio_smoke_en_cdc_prim.868817643 Jun 30 04:22:57 PM PDT 24 Jun 30 04:23:00 PM PDT 24 73510009 ps
T926 /workspace/coverage/en_cdc_prims/22.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2408265934 Jun 30 04:22:47 PM PDT 24 Jun 30 04:22:50 PM PDT 24 29068947 ps
T927 /workspace/coverage/en_cdc_prims/17.gpio_smoke_no_pullup_pulldown_en_cdc_prim.53469155 Jun 30 04:22:12 PM PDT 24 Jun 30 04:22:14 PM PDT 24 28287838 ps
T928 /workspace/coverage/en_cdc_prims/6.gpio_smoke_no_pullup_pulldown_en_cdc_prim.280057913 Jun 30 04:22:40 PM PDT 24 Jun 30 04:22:43 PM PDT 24 111299173 ps
T929 /workspace/coverage/en_cdc_prims/9.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1813706211 Jun 30 04:22:50 PM PDT 24 Jun 30 04:22:53 PM PDT 24 40950770 ps
T930 /workspace/coverage/en_cdc_prims/2.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3809857565 Jun 30 04:20:06 PM PDT 24 Jun 30 04:20:08 PM PDT 24 30512427 ps
T931 /workspace/coverage/en_cdc_prims/39.gpio_smoke_en_cdc_prim.4168190745 Jun 30 04:22:53 PM PDT 24 Jun 30 04:22:57 PM PDT 24 116531382 ps
T932 /workspace/coverage/en_cdc_prims/35.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3227789154 Jun 30 04:22:50 PM PDT 24 Jun 30 04:22:53 PM PDT 24 55689981 ps
T933 /workspace/coverage/en_cdc_prims/36.gpio_smoke_no_pullup_pulldown_en_cdc_prim.232203841 Jun 30 04:22:35 PM PDT 24 Jun 30 04:22:37 PM PDT 24 79194368 ps
T934 /workspace/coverage/en_cdc_prims/45.gpio_smoke_en_cdc_prim.704240790 Jun 30 04:22:44 PM PDT 24 Jun 30 04:22:49 PM PDT 24 80732141 ps
T935 /workspace/coverage/en_cdc_prims/24.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2152889118 Jun 30 04:22:49 PM PDT 24 Jun 30 04:22:53 PM PDT 24 60484936 ps
T936 /workspace/coverage/en_cdc_prims/29.gpio_smoke_en_cdc_prim.1208842595 Jun 30 04:18:41 PM PDT 24 Jun 30 04:18:43 PM PDT 24 226097000 ps
T937 /workspace/coverage/en_cdc_prims/47.gpio_smoke_no_pullup_pulldown_en_cdc_prim.92580453 Jun 30 04:22:51 PM PDT 24 Jun 30 04:22:53 PM PDT 24 165243195 ps
T938 /workspace/coverage/en_cdc_prims/26.gpio_smoke_no_pullup_pulldown_en_cdc_prim.137720659 Jun 30 04:22:06 PM PDT 24 Jun 30 04:22:10 PM PDT 24 89900208 ps
T939 /workspace/coverage/en_cdc_prims/39.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4247198605 Jun 30 04:21:56 PM PDT 24 Jun 30 04:21:59 PM PDT 24 208479356 ps
T940 /workspace/coverage/en_cdc_prims/28.gpio_smoke_en_cdc_prim.2912681095 Jun 30 04:20:04 PM PDT 24 Jun 30 04:20:06 PM PDT 24 457996807 ps
T941 /workspace/coverage/en_cdc_prims/1.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3879106810 Jun 30 04:17:48 PM PDT 24 Jun 30 04:17:49 PM PDT 24 74167721 ps
T942 /workspace/coverage/en_cdc_prims/16.gpio_smoke_en_cdc_prim.937779550 Jun 30 04:21:57 PM PDT 24 Jun 30 04:21:59 PM PDT 24 42561702 ps
T943 /workspace/coverage/en_cdc_prims/7.gpio_smoke_en_cdc_prim.1371344910 Jun 30 04:19:22 PM PDT 24 Jun 30 04:19:23 PM PDT 24 45441669 ps

Test location /workspace/coverage/default/35.gpio_full_random.2109727097
Short name T30
Test name
Test status
Simulation time 397278419 ps
CPU time 0.95 seconds
Started Jun 30 04:24:03 PM PDT 24
Finished Jun 30 04:24:07 PM PDT 24
Peak memory 197072 kb
Host smart-8b15bb5a-626d-4dfd-8f1a-378d1110fa31
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2109727097 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_full_random.2109727097
Directory /workspace/35.gpio_full_random/latest

Test location /workspace/coverage/default/37.gpio_intr_with_filter_rand_intr_event.2721052405
Short name T52
Test name
Test status
Simulation time 185304393 ps
CPU time 1.91 seconds
Started Jun 30 04:23:56 PM PDT 24
Finished Jun 30 04:23:59 PM PDT 24
Peak memory 198480 kb
Host smart-b5efe147-e8a3-4a1a-a1f9-1e68834945d2
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2721052405 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 37.gpio_intr_with_filter_rand_intr_event.2721052405
Directory /workspace/37.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/33.gpio_stress_all_with_rand_reset.3572416679
Short name T5
Test name
Test status
Simulation time 149101168790 ps
CPU time 550.7 seconds
Started Jun 30 04:24:10 PM PDT 24
Finished Jun 30 04:33:24 PM PDT 24
Peak memory 198708 kb
Host smart-0d041895-ce78-4fd1-abc9-5ceb07401a4a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3572416679 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_stress_all_with_rand_reset.3572416679
Directory /workspace/33.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.gpio_random_long_reg_writes_reg_reads.4257741129
Short name T2
Test name
Test status
Simulation time 1696812764 ps
CPU time 4.73 seconds
Started Jun 30 04:23:12 PM PDT 24
Finished Jun 30 04:23:18 PM PDT 24
Peak memory 198244 kb
Host smart-39fd2c99-1664-4e17-9c40-f3896f8f2940
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4257741129 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_ra
ndom_long_reg_writes_reg_reads.4257741129
Directory /workspace/12.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/0.gpio_sec_cm.3609345238
Short name T38
Test name
Test status
Simulation time 39710468 ps
CPU time 0.85 seconds
Started Jun 30 04:18:37 PM PDT 24
Finished Jun 30 04:18:39 PM PDT 24
Peak memory 214472 kb
Host smart-e5ee96ef-f328-460d-a8ea-132cb91e493d
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3609345238 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_sec_cm.3609345238
Directory /workspace/0.gpio_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_csr_aliasing.2500169291
Short name T69
Test name
Test status
Simulation time 177576062 ps
CPU time 0.82 seconds
Started Jun 30 04:22:38 PM PDT 24
Finished Jun 30 04:22:41 PM PDT 24
Peak memory 196252 kb
Host smart-b7f431a1-b0e2-4ed4-b859-357c5a92e546
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2500169291 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM
_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
1.gpio_csr_aliasing.2500169291
Directory /workspace/1.gpio_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_tl_intg_err.3178195881
Short name T42
Test name
Test status
Simulation time 1765916549 ps
CPU time 1.5 seconds
Started Jun 30 04:22:54 PM PDT 24
Finished Jun 30 04:22:58 PM PDT 24
Peak memory 199012 kb
Host smart-115930fe-6103-4406-8f14-c2507954e1c9
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3178195881 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 18.gpio_tl_intg_err.3178195881
Directory /workspace/18.gpio_tl_intg_err/latest

Test location /workspace/coverage/default/20.gpio_alert_test.2700658807
Short name T18
Test name
Test status
Simulation time 13265246 ps
CPU time 0.56 seconds
Started Jun 30 04:23:44 PM PDT 24
Finished Jun 30 04:23:45 PM PDT 24
Peak memory 194624 kb
Host smart-d5946236-3a0b-461b-b56a-d3b9a11ff0c4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2700658807 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_alert_test.2700658807
Directory /workspace/20.gpio_alert_test/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_csr_rw.1090187459
Short name T80
Test name
Test status
Simulation time 11224644 ps
CPU time 0.62 seconds
Started Jun 30 04:21:06 PM PDT 24
Finished Jun 30 04:21:07 PM PDT 24
Peak memory 195280 kb
Host smart-f2df3c4c-cd72-4bc5-b156-0614ec503b86
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1090187459 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio
_csr_rw.1090187459
Directory /workspace/0.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_same_csr_outstanding.4086531116
Short name T89
Test name
Test status
Simulation time 20153532 ps
CPU time 0.78 seconds
Started Jun 30 04:17:09 PM PDT 24
Finished Jun 30 04:17:10 PM PDT 24
Peak memory 197036 kb
Host smart-8209a92d-072d-4116-abb8-178a0ffc4394
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4086531116 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 0.gpio_same_csr_outstanding.4086531116
Directory /workspace/0.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_tl_intg_err.2710278708
Short name T45
Test name
Test status
Simulation time 80340569 ps
CPU time 1.12 seconds
Started Jun 30 04:22:36 PM PDT 24
Finished Jun 30 04:22:38 PM PDT 24
Peak memory 198532 kb
Host smart-1881bd68-c505-46ac-be8b-0c1774bc92bd
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2710278708 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 12.gpio_tl_intg_err.2710278708
Directory /workspace/12.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_csr_aliasing.2734539981
Short name T103
Test name
Test status
Simulation time 233064704 ps
CPU time 0.87 seconds
Started Jun 30 04:22:41 PM PDT 24
Finished Jun 30 04:22:45 PM PDT 24
Peak memory 196336 kb
Host smart-c66971b5-a380-4230-b617-f2d4006a675f
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2734539981 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM
_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
0.gpio_csr_aliasing.2734539981
Directory /workspace/0.gpio_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_csr_bit_bash.3214246448
Short name T108
Test name
Test status
Simulation time 87105505 ps
CPU time 2.85 seconds
Started Jun 30 04:22:38 PM PDT 24
Finished Jun 30 04:22:42 PM PDT 24
Peak memory 198212 kb
Host smart-ec67a41a-7fd7-4543-a6d9-8306cfb99c00
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3214246448 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_csr_bit_bash.3214246448
Directory /workspace/0.gpio_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_csr_hw_reset.2667737022
Short name T83
Test name
Test status
Simulation time 20343963 ps
CPU time 0.61 seconds
Started Jun 30 04:22:51 PM PDT 24
Finished Jun 30 04:22:53 PM PDT 24
Peak memory 194652 kb
Host smart-782438a1-286f-4aad-84ee-a855008ca0a1
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2667737022 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_csr_hw_reset.2667737022
Directory /workspace/0.gpio_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_csr_mem_rw_with_rand_reset.1078560261
Short name T838
Test name
Test status
Simulation time 18371569 ps
CPU time 0.92 seconds
Started Jun 30 04:20:07 PM PDT 24
Finished Jun 30 04:20:08 PM PDT 24
Peak memory 198376 kb
Host smart-5afaa266-2e0f-4512-a977-c6b2592cb3b0
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1078560261 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_csr_mem_rw_with_rand_reset.1078560261
Directory /workspace/0.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_intr_test.1017504201
Short name T781
Test name
Test status
Simulation time 117233442 ps
CPU time 0.63 seconds
Started Jun 30 04:22:43 PM PDT 24
Finished Jun 30 04:22:47 PM PDT 24
Peak memory 193524 kb
Host smart-de10e21f-68e5-456d-866e-25460b0940c0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1017504201 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_intr_test.1017504201
Directory /workspace/0.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_tl_errors.2773815853
Short name T726
Test name
Test status
Simulation time 57282986 ps
CPU time 1.64 seconds
Started Jun 30 04:21:03 PM PDT 24
Finished Jun 30 04:21:05 PM PDT 24
Peak memory 198508 kb
Host smart-ff679db7-b658-4769-b5ee-9a80003bdf04
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2773815853 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_tl_errors.2773815853
Directory /workspace/0.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_tl_intg_err.1758869814
Short name T46
Test name
Test status
Simulation time 210049128 ps
CPU time 1.42 seconds
Started Jun 30 04:23:00 PM PDT 24
Finished Jun 30 04:23:03 PM PDT 24
Peak memory 198516 kb
Host smart-48f8c416-8f46-482f-964b-a614f2f4384f
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1758869814 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 0.gpio_tl_intg_err.1758869814
Directory /workspace/0.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_csr_bit_bash.2042953902
Short name T821
Test name
Test status
Simulation time 37022299 ps
CPU time 1.31 seconds
Started Jun 30 04:20:29 PM PDT 24
Finished Jun 30 04:20:31 PM PDT 24
Peak memory 197156 kb
Host smart-12b358f8-680a-4446-a498-c1dc22cd5757
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2042953902 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_csr_bit_bash.2042953902
Directory /workspace/1.gpio_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_csr_hw_reset.3387688200
Short name T106
Test name
Test status
Simulation time 15605634 ps
CPU time 0.6 seconds
Started Jun 30 04:18:22 PM PDT 24
Finished Jun 30 04:18:23 PM PDT 24
Peak memory 195108 kb
Host smart-1c49554c-5d04-4460-8e59-0e9deeaf1a7f
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3387688200 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_csr_hw_reset.3387688200
Directory /workspace/1.gpio_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_csr_mem_rw_with_rand_reset.3796792760
Short name T811
Test name
Test status
Simulation time 30226758 ps
CPU time 1.34 seconds
Started Jun 30 04:22:38 PM PDT 24
Finished Jun 30 04:22:40 PM PDT 24
Peak memory 198300 kb
Host smart-a5cb13c7-23b5-481d-8a9a-928636831a68
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3796792760 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_csr_mem_rw_with_rand_reset.3796792760
Directory /workspace/1.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_csr_rw.3018652045
Short name T753
Test name
Test status
Simulation time 69270550 ps
CPU time 0.61 seconds
Started Jun 30 04:22:37 PM PDT 24
Finished Jun 30 04:22:39 PM PDT 24
Peak memory 194692 kb
Host smart-ecc6521f-c20b-40b5-b6f2-ac8d2f18eeb9
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3018652045 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio
_csr_rw.3018652045
Directory /workspace/1.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_intr_test.473028787
Short name T782
Test name
Test status
Simulation time 18305383 ps
CPU time 0.64 seconds
Started Jun 30 04:22:38 PM PDT 24
Finished Jun 30 04:22:40 PM PDT 24
Peak memory 194016 kb
Host smart-c3cf46f5-d650-4a79-b053-435830efdcc4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=473028787 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_intr_test.473028787
Directory /workspace/1.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_same_csr_outstanding.319969151
Short name T88
Test name
Test status
Simulation time 32468350 ps
CPU time 0.7 seconds
Started Jun 30 04:22:37 PM PDT 24
Finished Jun 30 04:22:39 PM PDT 24
Peak memory 194512 kb
Host smart-9eec8454-8033-424d-ba9e-cf9d7b78ebfd
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=319969151 -assert nopostproc +UVM_TESTNAME=gpio_bas
e_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 1.gpio_same_csr_outstanding.319969151
Directory /workspace/1.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_tl_errors.1472334395
Short name T737
Test name
Test status
Simulation time 103495684 ps
CPU time 2.04 seconds
Started Jun 30 04:22:38 PM PDT 24
Finished Jun 30 04:22:43 PM PDT 24
Peak memory 198296 kb
Host smart-26a9ec8b-8840-4cc6-99eb-6ba4aa9555d0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1472334395 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_tl_errors.1472334395
Directory /workspace/1.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_tl_intg_err.2825658165
Short name T43
Test name
Test status
Simulation time 344034213 ps
CPU time 1.28 seconds
Started Jun 30 04:22:38 PM PDT 24
Finished Jun 30 04:22:41 PM PDT 24
Peak memory 198224 kb
Host smart-c2b131e7-a043-4d78-8e0f-15ac74613b4c
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2825658165 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 1.gpio_tl_intg_err.2825658165
Directory /workspace/1.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_csr_mem_rw_with_rand_reset.3160011632
Short name T765
Test name
Test status
Simulation time 30690889 ps
CPU time 0.83 seconds
Started Jun 30 04:21:55 PM PDT 24
Finished Jun 30 04:21:57 PM PDT 24
Peak memory 198032 kb
Host smart-76ab2b4f-5ed3-4f7f-9ccc-91161808b1fc
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3160011632 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.gpio_csr_mem_rw_with_rand_reset.3160011632
Directory /workspace/10.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_csr_rw.3628289935
Short name T757
Test name
Test status
Simulation time 11867157 ps
CPU time 0.61 seconds
Started Jun 30 04:20:06 PM PDT 24
Finished Jun 30 04:20:07 PM PDT 24
Peak memory 195388 kb
Host smart-b2217b6b-5c40-4661-879e-b2b0ad7b4cf1
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3628289935 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.gpi
o_csr_rw.3628289935
Directory /workspace/10.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_intr_test.2156168501
Short name T799
Test name
Test status
Simulation time 93133719 ps
CPU time 0.64 seconds
Started Jun 30 04:21:54 PM PDT 24
Finished Jun 30 04:21:57 PM PDT 24
Peak memory 194164 kb
Host smart-67f1c898-89ac-478c-8289-a796bded1246
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2156168501 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.gpio_intr_test.2156168501
Directory /workspace/10.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_same_csr_outstanding.2191945782
Short name T86
Test name
Test status
Simulation time 22431045 ps
CPU time 0.68 seconds
Started Jun 30 04:20:26 PM PDT 24
Finished Jun 30 04:20:27 PM PDT 24
Peak memory 195040 kb
Host smart-4b52102a-a7fa-45b4-8ee6-5388f1398e80
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2191945782 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 10.gpio_same_csr_outstanding.2191945782
Directory /workspace/10.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_tl_errors.362319366
Short name T829
Test name
Test status
Simulation time 461849276 ps
CPU time 1.39 seconds
Started Jun 30 04:20:22 PM PDT 24
Finished Jun 30 04:20:24 PM PDT 24
Peak memory 198560 kb
Host smart-31e11dd7-35d7-4b1c-bc99-51170c12bf00
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=362319366 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.gpio_tl_errors.362319366
Directory /workspace/10.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_tl_intg_err.4163723266
Short name T810
Test name
Test status
Simulation time 389542369 ps
CPU time 0.85 seconds
Started Jun 30 04:21:55 PM PDT 24
Finished Jun 30 04:21:58 PM PDT 24
Peak memory 197384 kb
Host smart-fc3998e5-e2f0-46c4-866b-9f81df7294f7
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4163723266 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 10.gpio_tl_intg_err.4163723266
Directory /workspace/10.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_csr_mem_rw_with_rand_reset.1881636215
Short name T750
Test name
Test status
Simulation time 56958216 ps
CPU time 0.86 seconds
Started Jun 30 04:21:54 PM PDT 24
Finished Jun 30 04:21:57 PM PDT 24
Peak memory 197900 kb
Host smart-d572a481-284f-410c-a35a-7353d0da3bb9
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1881636215 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.gpio_csr_mem_rw_with_rand_reset.1881636215
Directory /workspace/11.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_csr_rw.3611145968
Short name T74
Test name
Test status
Simulation time 13562508 ps
CPU time 0.61 seconds
Started Jun 30 04:21:00 PM PDT 24
Finished Jun 30 04:21:00 PM PDT 24
Peak memory 195600 kb
Host smart-a1ac0891-a028-4c17-92ca-109347410625
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3611145968 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.gpi
o_csr_rw.3611145968
Directory /workspace/11.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_intr_test.821652815
Short name T766
Test name
Test status
Simulation time 35129031 ps
CPU time 0.58 seconds
Started Jun 30 04:21:55 PM PDT 24
Finished Jun 30 04:21:57 PM PDT 24
Peak memory 194532 kb
Host smart-a86932b6-2631-40bd-bed6-266fdbde569a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=821652815 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.gpio_intr_test.821652815
Directory /workspace/11.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_same_csr_outstanding.3195685438
Short name T803
Test name
Test status
Simulation time 20461851 ps
CPU time 0.77 seconds
Started Jun 30 04:22:15 PM PDT 24
Finished Jun 30 04:22:16 PM PDT 24
Peak memory 196628 kb
Host smart-fe8515c7-24f9-41d4-99ef-8b61d07bb6cb
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3195685438 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 11.gpio_same_csr_outstanding.3195685438
Directory /workspace/11.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_tl_errors.3189423696
Short name T739
Test name
Test status
Simulation time 38074985 ps
CPU time 1.86 seconds
Started Jun 30 04:20:26 PM PDT 24
Finished Jun 30 04:20:29 PM PDT 24
Peak memory 198564 kb
Host smart-01e0bff8-4916-4bba-847c-496540edf9cd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3189423696 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.gpio_tl_errors.3189423696
Directory /workspace/11.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_tl_intg_err.579957290
Short name T792
Test name
Test status
Simulation time 246362208 ps
CPU time 1.38 seconds
Started Jun 30 04:21:55 PM PDT 24
Finished Jun 30 04:21:58 PM PDT 24
Peak memory 197400 kb
Host smart-0afee23a-f026-43d0-abbd-aa5dc6609123
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=579957290 -assert nopostproc +UVM_TESTNAME=gpio_base_test +U
VM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 11.gpio_tl_intg_err.579957290
Directory /workspace/11.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_csr_mem_rw_with_rand_reset.3504451932
Short name T773
Test name
Test status
Simulation time 51024122 ps
CPU time 0.66 seconds
Started Jun 30 04:22:01 PM PDT 24
Finished Jun 30 04:22:03 PM PDT 24
Peak memory 197984 kb
Host smart-901d63db-7acb-41dd-be12-545aa02be580
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3504451932 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.gpio_csr_mem_rw_with_rand_reset.3504451932
Directory /workspace/12.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_csr_rw.569448955
Short name T82
Test name
Test status
Simulation time 16443427 ps
CPU time 0.6 seconds
Started Jun 30 04:21:57 PM PDT 24
Finished Jun 30 04:21:59 PM PDT 24
Peak memory 194064 kb
Host smart-12203f8e-54f3-49a9-92c1-49de72e0c745
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=569448955 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.gpio
_csr_rw.569448955
Directory /workspace/12.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_intr_test.2564375432
Short name T763
Test name
Test status
Simulation time 24090815 ps
CPU time 0.65 seconds
Started Jun 30 04:22:29 PM PDT 24
Finished Jun 30 04:22:30 PM PDT 24
Peak memory 194972 kb
Host smart-c4e27d17-7cf8-4ccf-81de-362a1a7354e1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2564375432 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.gpio_intr_test.2564375432
Directory /workspace/12.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_same_csr_outstanding.3571660106
Short name T839
Test name
Test status
Simulation time 270422307 ps
CPU time 0.79 seconds
Started Jun 30 04:20:59 PM PDT 24
Finished Jun 30 04:21:00 PM PDT 24
Peak memory 197860 kb
Host smart-608505e5-dd2a-4943-bace-26f82f796f61
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3571660106 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 12.gpio_same_csr_outstanding.3571660106
Directory /workspace/12.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_tl_errors.3201178671
Short name T746
Test name
Test status
Simulation time 543608781 ps
CPU time 2.51 seconds
Started Jun 30 04:22:32 PM PDT 24
Finished Jun 30 04:22:34 PM PDT 24
Peak memory 198556 kb
Host smart-a4a77347-52f5-4be8-8a97-366655a7d1be
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3201178671 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.gpio_tl_errors.3201178671
Directory /workspace/12.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_csr_mem_rw_with_rand_reset.3567488140
Short name T718
Test name
Test status
Simulation time 21495075 ps
CPU time 1.03 seconds
Started Jun 30 04:22:37 PM PDT 24
Finished Jun 30 04:22:39 PM PDT 24
Peak memory 198384 kb
Host smart-f0af3ae9-48ed-413e-9c48-528ef5c038be
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3567488140 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.gpio_csr_mem_rw_with_rand_reset.3567488140
Directory /workspace/13.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_csr_rw.3466754114
Short name T787
Test name
Test status
Simulation time 42849313 ps
CPU time 0.63 seconds
Started Jun 30 04:22:37 PM PDT 24
Finished Jun 30 04:22:39 PM PDT 24
Peak memory 195480 kb
Host smart-36222c6c-015a-4145-ba18-c4026ab45958
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3466754114 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.gpi
o_csr_rw.3466754114
Directory /workspace/13.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_intr_test.1057795493
Short name T758
Test name
Test status
Simulation time 77473247 ps
CPU time 0.66 seconds
Started Jun 30 04:22:41 PM PDT 24
Finished Jun 30 04:22:44 PM PDT 24
Peak memory 194724 kb
Host smart-07b9d302-77bc-4a9a-9064-f9f3014b28f0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1057795493 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.gpio_intr_test.1057795493
Directory /workspace/13.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_same_csr_outstanding.2185338709
Short name T87
Test name
Test status
Simulation time 18680193 ps
CPU time 0.7 seconds
Started Jun 30 04:22:35 PM PDT 24
Finished Jun 30 04:22:36 PM PDT 24
Peak memory 197360 kb
Host smart-34026422-0220-44b8-8cdd-311685ab5d56
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2185338709 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 13.gpio_same_csr_outstanding.2185338709
Directory /workspace/13.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_tl_errors.4172253767
Short name T733
Test name
Test status
Simulation time 225111292 ps
CPU time 1.5 seconds
Started Jun 30 04:22:31 PM PDT 24
Finished Jun 30 04:22:33 PM PDT 24
Peak memory 198576 kb
Host smart-65a69ab9-76c0-4799-bb3e-2792c050673d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4172253767 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.gpio_tl_errors.4172253767
Directory /workspace/13.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_tl_intg_err.2637290407
Short name T35
Test name
Test status
Simulation time 296246108 ps
CPU time 1.38 seconds
Started Jun 30 04:22:38 PM PDT 24
Finished Jun 30 04:22:40 PM PDT 24
Peak memory 198588 kb
Host smart-3d0a71b1-fff6-4f7b-a6ab-0d5abb06c36d
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2637290407 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 13.gpio_tl_intg_err.2637290407
Directory /workspace/13.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_csr_mem_rw_with_rand_reset.439711961
Short name T755
Test name
Test status
Simulation time 22847332 ps
CPU time 0.72 seconds
Started Jun 30 04:22:39 PM PDT 24
Finished Jun 30 04:22:42 PM PDT 24
Peak memory 198360 kb
Host smart-54500455-5f33-47a7-a744-b4f444af9aea
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=439711961 -asser
t nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.gpio_csr_mem_rw_with_rand_reset.439711961
Directory /workspace/14.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_csr_rw.2801058743
Short name T105
Test name
Test status
Simulation time 15521766 ps
CPU time 0.59 seconds
Started Jun 30 04:22:36 PM PDT 24
Finished Jun 30 04:22:37 PM PDT 24
Peak memory 195100 kb
Host smart-8855f558-d958-4acc-bb74-fddab0b217dd
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2801058743 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.gpi
o_csr_rw.2801058743
Directory /workspace/14.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_intr_test.579841922
Short name T764
Test name
Test status
Simulation time 12968549 ps
CPU time 0.65 seconds
Started Jun 30 04:22:40 PM PDT 24
Finished Jun 30 04:22:44 PM PDT 24
Peak memory 194216 kb
Host smart-fdd4ac68-94f4-4e70-b2fc-b42d35d43991
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=579841922 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.gpio_intr_test.579841922
Directory /workspace/14.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_same_csr_outstanding.3767380972
Short name T806
Test name
Test status
Simulation time 32473278 ps
CPU time 0.83 seconds
Started Jun 30 04:22:40 PM PDT 24
Finished Jun 30 04:22:43 PM PDT 24
Peak memory 196792 kb
Host smart-e516c685-46a2-423d-becc-c1ff57ead1df
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3767380972 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 14.gpio_same_csr_outstanding.3767380972
Directory /workspace/14.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_tl_errors.1545467938
Short name T775
Test name
Test status
Simulation time 208289457 ps
CPU time 3.35 seconds
Started Jun 30 04:22:42 PM PDT 24
Finished Jun 30 04:22:48 PM PDT 24
Peak memory 198612 kb
Host smart-cb56775d-9921-41bb-ba16-5d5d3e173169
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1545467938 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.gpio_tl_errors.1545467938
Directory /workspace/14.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_tl_intg_err.52173259
Short name T762
Test name
Test status
Simulation time 223728240 ps
CPU time 1.41 seconds
Started Jun 30 04:22:41 PM PDT 24
Finished Jun 30 04:22:46 PM PDT 24
Peak memory 198324 kb
Host smart-1f8f10d7-0689-46d4-9fd9-c880bd701e47
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52173259 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UV
M_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
14.gpio_tl_intg_err.52173259
Directory /workspace/14.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_csr_mem_rw_with_rand_reset.665317139
Short name T798
Test name
Test status
Simulation time 34921352 ps
CPU time 1.63 seconds
Started Jun 30 04:22:54 PM PDT 24
Finished Jun 30 04:22:58 PM PDT 24
Peak memory 198888 kb
Host smart-75504de7-3f22-4086-b3aa-0e0a73797902
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=665317139 -asser
t nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.gpio_csr_mem_rw_with_rand_reset.665317139
Directory /workspace/15.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_csr_rw.2509305867
Short name T790
Test name
Test status
Simulation time 23267495 ps
CPU time 0.59 seconds
Started Jun 30 04:22:40 PM PDT 24
Finished Jun 30 04:22:43 PM PDT 24
Peak memory 195120 kb
Host smart-2e7617d7-7fe9-430d-bea3-6399d73b9514
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2509305867 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.gpi
o_csr_rw.2509305867
Directory /workspace/15.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_intr_test.1475466192
Short name T801
Test name
Test status
Simulation time 11742620 ps
CPU time 0.58 seconds
Started Jun 30 04:22:38 PM PDT 24
Finished Jun 30 04:22:40 PM PDT 24
Peak memory 194228 kb
Host smart-1ee483c4-3b1d-42c6-93a4-099bee286395
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1475466192 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.gpio_intr_test.1475466192
Directory /workspace/15.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_same_csr_outstanding.348050977
Short name T830
Test name
Test status
Simulation time 34658297 ps
CPU time 0.75 seconds
Started Jun 30 04:22:40 PM PDT 24
Finished Jun 30 04:22:44 PM PDT 24
Peak memory 196624 kb
Host smart-366a8e36-35ed-4b07-ad83-86044f687581
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=348050977 -assert nopostproc +UVM_TESTNAME=gpio_bas
e_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 15.gpio_same_csr_outstanding.348050977
Directory /workspace/15.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_tl_errors.925427407
Short name T740
Test name
Test status
Simulation time 38649387 ps
CPU time 1.2 seconds
Started Jun 30 04:22:54 PM PDT 24
Finished Jun 30 04:22:58 PM PDT 24
Peak memory 198736 kb
Host smart-f8ffe7be-6513-4669-867c-07b454113ff3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=925427407 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.gpio_tl_errors.925427407
Directory /workspace/15.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_tl_intg_err.3723329272
Short name T825
Test name
Test status
Simulation time 457983709 ps
CPU time 1.31 seconds
Started Jun 30 04:22:36 PM PDT 24
Finished Jun 30 04:22:38 PM PDT 24
Peak memory 198448 kb
Host smart-9ed003ad-ceee-4238-b322-d23e6fa2400c
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3723329272 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 15.gpio_tl_intg_err.3723329272
Directory /workspace/15.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_csr_mem_rw_with_rand_reset.3990194169
Short name T822
Test name
Test status
Simulation time 15198735 ps
CPU time 0.71 seconds
Started Jun 30 04:22:38 PM PDT 24
Finished Jun 30 04:22:40 PM PDT 24
Peak memory 197444 kb
Host smart-02ac9069-6fdf-4240-b3c9-52d678774e82
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3990194169 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.gpio_csr_mem_rw_with_rand_reset.3990194169
Directory /workspace/16.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_csr_rw.2057378814
Short name T70
Test name
Test status
Simulation time 57556464 ps
CPU time 0.64 seconds
Started Jun 30 04:22:42 PM PDT 24
Finished Jun 30 04:22:46 PM PDT 24
Peak memory 195348 kb
Host smart-632aad07-d22a-4e1c-9a3f-ced1fc2fa05f
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2057378814 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.gpi
o_csr_rw.2057378814
Directory /workspace/16.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_intr_test.553978031
Short name T772
Test name
Test status
Simulation time 14455088 ps
CPU time 0.62 seconds
Started Jun 30 04:22:39 PM PDT 24
Finished Jun 30 04:22:42 PM PDT 24
Peak memory 194248 kb
Host smart-8633df48-ca06-4e3b-9bf7-d2cf875862b5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=553978031 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.gpio_intr_test.553978031
Directory /workspace/16.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_same_csr_outstanding.1129589143
Short name T840
Test name
Test status
Simulation time 36356757 ps
CPU time 0.71 seconds
Started Jun 30 04:22:54 PM PDT 24
Finished Jun 30 04:22:58 PM PDT 24
Peak memory 195788 kb
Host smart-4b5d6e05-6119-492f-a370-eead5003a683
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1129589143 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 16.gpio_same_csr_outstanding.1129589143
Directory /workspace/16.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_tl_errors.1255284205
Short name T738
Test name
Test status
Simulation time 171349222 ps
CPU time 2.3 seconds
Started Jun 30 04:22:39 PM PDT 24
Finished Jun 30 04:22:43 PM PDT 24
Peak memory 198488 kb
Host smart-713b1b37-26e0-4c1a-a62a-f24f3d5fdaa1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1255284205 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.gpio_tl_errors.1255284205
Directory /workspace/16.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_tl_intg_err.291760082
Short name T44
Test name
Test status
Simulation time 1786150831 ps
CPU time 1.37 seconds
Started Jun 30 04:22:39 PM PDT 24
Finished Jun 30 04:22:43 PM PDT 24
Peak memory 198516 kb
Host smart-ea1dba7f-8178-4bd7-8b18-4de2eb903c5d
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=291760082 -assert nopostproc +UVM_TESTNAME=gpio_base_test +U
VM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 16.gpio_tl_intg_err.291760082
Directory /workspace/16.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_csr_mem_rw_with_rand_reset.151726502
Short name T759
Test name
Test status
Simulation time 68341670 ps
CPU time 1.03 seconds
Started Jun 30 04:22:41 PM PDT 24
Finished Jun 30 04:22:45 PM PDT 24
Peak memory 198796 kb
Host smart-edaaf96c-4018-4aee-b0de-ab2f909a4f88
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=151726502 -asser
t nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.gpio_csr_mem_rw_with_rand_reset.151726502
Directory /workspace/17.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_csr_rw.554975479
Short name T813
Test name
Test status
Simulation time 12739612 ps
CPU time 0.57 seconds
Started Jun 30 04:22:37 PM PDT 24
Finished Jun 30 04:22:38 PM PDT 24
Peak memory 193652 kb
Host smart-f1ee2f3d-c3ff-4bf9-a998-3726caeb48cb
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=554975479 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.gpio
_csr_rw.554975479
Directory /workspace/17.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_intr_test.1639927473
Short name T760
Test name
Test status
Simulation time 54171116 ps
CPU time 0.61 seconds
Started Jun 30 04:22:38 PM PDT 24
Finished Jun 30 04:22:41 PM PDT 24
Peak memory 194284 kb
Host smart-a339c775-2ced-4373-93cb-16ad779ae8e4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1639927473 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.gpio_intr_test.1639927473
Directory /workspace/17.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_same_csr_outstanding.1265092356
Short name T826
Test name
Test status
Simulation time 27637819 ps
CPU time 0.77 seconds
Started Jun 30 04:22:38 PM PDT 24
Finished Jun 30 04:22:41 PM PDT 24
Peak memory 196292 kb
Host smart-6a221fd1-4685-4989-b866-db72dd5d7650
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1265092356 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 17.gpio_same_csr_outstanding.1265092356
Directory /workspace/17.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_tl_errors.1060122844
Short name T827
Test name
Test status
Simulation time 72524509 ps
CPU time 1.52 seconds
Started Jun 30 04:22:54 PM PDT 24
Finished Jun 30 04:22:59 PM PDT 24
Peak memory 199012 kb
Host smart-244032e9-f5b3-42eb-9871-22ea3b53c5e0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1060122844 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.gpio_tl_errors.1060122844
Directory /workspace/17.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_tl_intg_err.1870790658
Short name T37
Test name
Test status
Simulation time 227447933 ps
CPU time 0.89 seconds
Started Jun 30 04:22:40 PM PDT 24
Finished Jun 30 04:22:44 PM PDT 24
Peak memory 198716 kb
Host smart-33eff08c-5ca7-4905-bad9-07f411bae99d
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1870790658 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 17.gpio_tl_intg_err.1870790658
Directory /workspace/17.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_csr_mem_rw_with_rand_reset.827947498
Short name T747
Test name
Test status
Simulation time 18024684 ps
CPU time 0.78 seconds
Started Jun 30 04:22:37 PM PDT 24
Finished Jun 30 04:22:39 PM PDT 24
Peak memory 198324 kb
Host smart-bb2c1e8a-0d94-4130-ac78-c8c2ce1a9410
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=827947498 -asser
t nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.gpio_csr_mem_rw_with_rand_reset.827947498
Directory /workspace/18.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_csr_rw.2964056761
Short name T76
Test name
Test status
Simulation time 122343181 ps
CPU time 0.63 seconds
Started Jun 30 04:22:42 PM PDT 24
Finished Jun 30 04:22:46 PM PDT 24
Peak memory 195412 kb
Host smart-b4ffd5cb-103b-4087-bcd5-b47cf76e216d
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2964056761 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.gpi
o_csr_rw.2964056761
Directory /workspace/18.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_intr_test.3148660795
Short name T719
Test name
Test status
Simulation time 27641760 ps
CPU time 0.62 seconds
Started Jun 30 04:22:54 PM PDT 24
Finished Jun 30 04:22:58 PM PDT 24
Peak memory 195100 kb
Host smart-eb0e9ee8-1a90-44b3-997d-3c07fa726904
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3148660795 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.gpio_intr_test.3148660795
Directory /workspace/18.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_same_csr_outstanding.1956481915
Short name T90
Test name
Test status
Simulation time 15417599 ps
CPU time 0.66 seconds
Started Jun 30 04:22:42 PM PDT 24
Finished Jun 30 04:22:46 PM PDT 24
Peak memory 194908 kb
Host smart-a7733367-970d-4f77-8b03-4268d7c9bfe8
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1956481915 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 18.gpio_same_csr_outstanding.1956481915
Directory /workspace/18.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_tl_errors.529780573
Short name T789
Test name
Test status
Simulation time 29983047 ps
CPU time 0.84 seconds
Started Jun 30 04:22:42 PM PDT 24
Finished Jun 30 04:22:46 PM PDT 24
Peak memory 198208 kb
Host smart-aac1e470-c787-41ed-94df-a41a3a80af02
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=529780573 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.gpio_tl_errors.529780573
Directory /workspace/18.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_csr_mem_rw_with_rand_reset.1578339319
Short name T779
Test name
Test status
Simulation time 55760227 ps
CPU time 0.89 seconds
Started Jun 30 04:22:41 PM PDT 24
Finished Jun 30 04:22:45 PM PDT 24
Peak memory 198352 kb
Host smart-456f6f5d-5779-46d6-8868-bfff83b8294e
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1578339319 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.gpio_csr_mem_rw_with_rand_reset.1578339319
Directory /workspace/19.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_csr_rw.25192735
Short name T814
Test name
Test status
Simulation time 12781543 ps
CPU time 0.6 seconds
Started Jun 30 04:22:54 PM PDT 24
Finished Jun 30 04:22:57 PM PDT 24
Peak memory 194084 kb
Host smart-62df2059-94e8-407e-a01d-efc7c6e316b0
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25192735 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SE
Q=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.gpio_
csr_rw.25192735
Directory /workspace/19.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_intr_test.781446869
Short name T802
Test name
Test status
Simulation time 25235742 ps
CPU time 0.65 seconds
Started Jun 30 04:22:54 PM PDT 24
Finished Jun 30 04:22:58 PM PDT 24
Peak memory 195356 kb
Host smart-98345691-be69-462d-bef6-617a7635e94d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=781446869 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.gpio_intr_test.781446869
Directory /workspace/19.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_same_csr_outstanding.134537090
Short name T807
Test name
Test status
Simulation time 26961014 ps
CPU time 0.77 seconds
Started Jun 30 04:22:38 PM PDT 24
Finished Jun 30 04:22:41 PM PDT 24
Peak memory 196564 kb
Host smart-ff2808f4-d9f0-4ace-b4c4-086f46ac2d65
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=134537090 -assert nopostproc +UVM_TESTNAME=gpio_bas
e_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 19.gpio_same_csr_outstanding.134537090
Directory /workspace/19.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_tl_errors.35856104
Short name T731
Test name
Test status
Simulation time 404675470 ps
CPU time 1.93 seconds
Started Jun 30 04:22:42 PM PDT 24
Finished Jun 30 04:22:47 PM PDT 24
Peak memory 198468 kb
Host smart-6ccad48f-979b-4790-9182-cb53e99345b8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35856104 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.gpio_tl_errors.35856104
Directory /workspace/19.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_tl_intg_err.341602361
Short name T793
Test name
Test status
Simulation time 262581451 ps
CPU time 1.41 seconds
Started Jun 30 04:22:36 PM PDT 24
Finished Jun 30 04:22:38 PM PDT 24
Peak memory 198468 kb
Host smart-ca3869bf-8726-49f8-ba90-40c6eb0b837b
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=341602361 -assert nopostproc +UVM_TESTNAME=gpio_base_test +U
VM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 19.gpio_tl_intg_err.341602361
Directory /workspace/19.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_csr_aliasing.2656991012
Short name T79
Test name
Test status
Simulation time 99607237 ps
CPU time 0.85 seconds
Started Jun 30 04:22:36 PM PDT 24
Finished Jun 30 04:22:38 PM PDT 24
Peak memory 197516 kb
Host smart-cd444387-5ed9-47f2-9c60-88567e3d5996
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2656991012 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM
_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
2.gpio_csr_aliasing.2656991012
Directory /workspace/2.gpio_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_csr_bit_bash.2921498786
Short name T812
Test name
Test status
Simulation time 1549321096 ps
CPU time 3.29 seconds
Started Jun 30 04:20:04 PM PDT 24
Finished Jun 30 04:20:07 PM PDT 24
Peak memory 197256 kb
Host smart-506a2b4b-b2a9-4014-84db-d7fd23dece60
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2921498786 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_csr_bit_bash.2921498786
Directory /workspace/2.gpio_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_csr_hw_reset.1216037625
Short name T816
Test name
Test status
Simulation time 23933594 ps
CPU time 0.6 seconds
Started Jun 30 04:23:09 PM PDT 24
Finished Jun 30 04:23:10 PM PDT 24
Peak memory 194936 kb
Host smart-40c0067a-256c-4426-8371-6634930d8314
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1216037625 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_csr_hw_reset.1216037625
Directory /workspace/2.gpio_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_csr_mem_rw_with_rand_reset.2875701876
Short name T743
Test name
Test status
Simulation time 61143253 ps
CPU time 0.95 seconds
Started Jun 30 04:22:07 PM PDT 24
Finished Jun 30 04:22:09 PM PDT 24
Peak memory 198392 kb
Host smart-0a0c982a-2a84-433a-8e80-e343e3d9267c
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2875701876 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_csr_mem_rw_with_rand_reset.2875701876
Directory /workspace/2.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_csr_rw.2959875344
Short name T843
Test name
Test status
Simulation time 13589903 ps
CPU time 0.59 seconds
Started Jun 30 04:22:50 PM PDT 24
Finished Jun 30 04:22:53 PM PDT 24
Peak memory 195224 kb
Host smart-803070df-f5c5-4746-9b9b-99860652da5b
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2959875344 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio
_csr_rw.2959875344
Directory /workspace/2.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_intr_test.2239767405
Short name T808
Test name
Test status
Simulation time 10580531 ps
CPU time 0.57 seconds
Started Jun 30 04:20:30 PM PDT 24
Finished Jun 30 04:20:31 PM PDT 24
Peak memory 194892 kb
Host smart-6aea3f87-7bc5-40ae-ad5c-33675ce4c129
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2239767405 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_intr_test.2239767405
Directory /workspace/2.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_same_csr_outstanding.1067042381
Short name T78
Test name
Test status
Simulation time 34568985 ps
CPU time 0.94 seconds
Started Jun 30 04:20:32 PM PDT 24
Finished Jun 30 04:20:33 PM PDT 24
Peak memory 196820 kb
Host smart-d58532a5-3c2c-43fa-8311-e9a19ac6bd91
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1067042381 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 2.gpio_same_csr_outstanding.1067042381
Directory /workspace/2.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_tl_errors.1031779922
Short name T795
Test name
Test status
Simulation time 226732970 ps
CPU time 1.12 seconds
Started Jun 30 04:22:49 PM PDT 24
Finished Jun 30 04:22:52 PM PDT 24
Peak memory 197276 kb
Host smart-fce93611-6c14-480f-800f-bfc0fa66a9bc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1031779922 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_tl_errors.1031779922
Directory /workspace/2.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_tl_intg_err.4180599640
Short name T769
Test name
Test status
Simulation time 85562831 ps
CPU time 1.1 seconds
Started Jun 30 04:21:52 PM PDT 24
Finished Jun 30 04:21:54 PM PDT 24
Peak memory 198164 kb
Host smart-802588e8-fc86-4384-baef-38e1027dbbb7
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4180599640 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 2.gpio_tl_intg_err.4180599640
Directory /workspace/2.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.gpio_intr_test.3181753651
Short name T745
Test name
Test status
Simulation time 24186727 ps
CPU time 0.64 seconds
Started Jun 30 04:22:54 PM PDT 24
Finished Jun 30 04:22:58 PM PDT 24
Peak memory 194692 kb
Host smart-0932228a-5a55-445f-8834-4acb2c3b41e5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3181753651 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.gpio_intr_test.3181753651
Directory /workspace/20.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.gpio_intr_test.3530786817
Short name T796
Test name
Test status
Simulation time 14041295 ps
CPU time 0.62 seconds
Started Jun 30 04:22:43 PM PDT 24
Finished Jun 30 04:22:47 PM PDT 24
Peak memory 194284 kb
Host smart-65b86c9e-e8b1-4e5e-8722-1f2a94f60a3b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3530786817 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.gpio_intr_test.3530786817
Directory /workspace/21.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.gpio_intr_test.53604993
Short name T736
Test name
Test status
Simulation time 18637191 ps
CPU time 0.6 seconds
Started Jun 30 04:22:41 PM PDT 24
Finished Jun 30 04:22:45 PM PDT 24
Peak memory 194180 kb
Host smart-06f2ea9b-69d1-494e-bff9-3a1aba3d7cd8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53604993 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.gpio_intr_test.53604993
Directory /workspace/22.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.gpio_intr_test.523395863
Short name T744
Test name
Test status
Simulation time 68419348 ps
CPU time 0.57 seconds
Started Jun 30 04:22:39 PM PDT 24
Finished Jun 30 04:22:41 PM PDT 24
Peak memory 194116 kb
Host smart-00c98d3a-762b-4157-b398-f9d5d57b0879
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=523395863 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.gpio_intr_test.523395863
Directory /workspace/23.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.gpio_intr_test.1549769217
Short name T784
Test name
Test status
Simulation time 14418837 ps
CPU time 0.56 seconds
Started Jun 30 04:22:41 PM PDT 24
Finished Jun 30 04:22:44 PM PDT 24
Peak memory 194148 kb
Host smart-2719c7ad-4c0c-4023-98e1-481ef818a742
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1549769217 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.gpio_intr_test.1549769217
Directory /workspace/24.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.gpio_intr_test.1273464288
Short name T749
Test name
Test status
Simulation time 13413124 ps
CPU time 0.57 seconds
Started Jun 30 04:22:42 PM PDT 24
Finished Jun 30 04:22:46 PM PDT 24
Peak memory 194156 kb
Host smart-bf1f7742-d1cb-4ba4-bf0a-576f23ecff48
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1273464288 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.gpio_intr_test.1273464288
Directory /workspace/25.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.gpio_intr_test.1891776081
Short name T778
Test name
Test status
Simulation time 53625014 ps
CPU time 0.58 seconds
Started Jun 30 04:22:38 PM PDT 24
Finished Jun 30 04:22:40 PM PDT 24
Peak memory 194828 kb
Host smart-69df1e0b-de38-4af6-88a2-c5134486e9cd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1891776081 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.gpio_intr_test.1891776081
Directory /workspace/26.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.gpio_intr_test.3836881700
Short name T800
Test name
Test status
Simulation time 21074527 ps
CPU time 0.59 seconds
Started Jun 30 04:22:49 PM PDT 24
Finished Jun 30 04:22:51 PM PDT 24
Peak memory 194256 kb
Host smart-7ce09dd2-adc7-4516-a6d6-5ba09057de2c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3836881700 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.gpio_intr_test.3836881700
Directory /workspace/27.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.gpio_intr_test.1790123835
Short name T720
Test name
Test status
Simulation time 20899221 ps
CPU time 0.6 seconds
Started Jun 30 04:22:43 PM PDT 24
Finished Jun 30 04:22:47 PM PDT 24
Peak memory 194288 kb
Host smart-f1061a30-a5d3-4069-b212-7cf3e8d34fe7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1790123835 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.gpio_intr_test.1790123835
Directory /workspace/28.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.gpio_intr_test.3997588121
Short name T780
Test name
Test status
Simulation time 53092022 ps
CPU time 0.59 seconds
Started Jun 30 04:22:42 PM PDT 24
Finished Jun 30 04:22:46 PM PDT 24
Peak memory 194220 kb
Host smart-0d87d23a-86d9-4668-9489-98ddbcfdcbfd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3997588121 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.gpio_intr_test.3997588121
Directory /workspace/29.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_csr_aliasing.2697225415
Short name T805
Test name
Test status
Simulation time 36054874 ps
CPU time 0.63 seconds
Started Jun 30 04:22:35 PM PDT 24
Finished Jun 30 04:22:37 PM PDT 24
Peak memory 194320 kb
Host smart-c457a658-da2d-4330-bf02-ae6f502ccdad
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2697225415 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM
_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
3.gpio_csr_aliasing.2697225415
Directory /workspace/3.gpio_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_csr_bit_bash.4063258047
Short name T734
Test name
Test status
Simulation time 152115933 ps
CPU time 1.45 seconds
Started Jun 30 04:20:46 PM PDT 24
Finished Jun 30 04:20:48 PM PDT 24
Peak memory 197428 kb
Host smart-89313668-93b5-4b6f-8e9d-8054a883d6ca
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4063258047 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_csr_bit_bash.4063258047
Directory /workspace/3.gpio_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_csr_hw_reset.508860544
Short name T104
Test name
Test status
Simulation time 13526139 ps
CPU time 0.63 seconds
Started Jun 30 04:22:15 PM PDT 24
Finished Jun 30 04:22:17 PM PDT 24
Peak memory 195172 kb
Host smart-7bc5ee03-ad67-4481-b538-68d28177c247
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=508860544 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_csr_hw_reset.508860544
Directory /workspace/3.gpio_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_csr_mem_rw_with_rand_reset.1437331770
Short name T768
Test name
Test status
Simulation time 162363827 ps
CPU time 1.62 seconds
Started Jun 30 04:21:03 PM PDT 24
Finished Jun 30 04:21:06 PM PDT 24
Peak memory 198496 kb
Host smart-185583ea-fde3-447f-b1fd-3f93347891f9
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1437331770 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_csr_mem_rw_with_rand_reset.1437331770
Directory /workspace/3.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_csr_rw.1031062945
Short name T831
Test name
Test status
Simulation time 58828671 ps
CPU time 0.67 seconds
Started Jun 30 04:18:29 PM PDT 24
Finished Jun 30 04:18:30 PM PDT 24
Peak memory 195844 kb
Host smart-f535384d-5ca4-4ac9-b880-3553686786c2
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1031062945 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio
_csr_rw.1031062945
Directory /workspace/3.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_intr_test.1717316915
Short name T819
Test name
Test status
Simulation time 108341566 ps
CPU time 0.58 seconds
Started Jun 30 04:22:09 PM PDT 24
Finished Jun 30 04:22:12 PM PDT 24
Peak memory 194236 kb
Host smart-f29bb7d1-9da2-4028-8408-1bcaf55a0fe4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1717316915 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_intr_test.1717316915
Directory /workspace/3.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_same_csr_outstanding.3694093026
Short name T85
Test name
Test status
Simulation time 18755413 ps
CPU time 0.63 seconds
Started Jun 30 04:19:46 PM PDT 24
Finished Jun 30 04:19:48 PM PDT 24
Peak memory 195384 kb
Host smart-cb95a400-cf1a-40b5-9276-cb07b4f64caf
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3694093026 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 3.gpio_same_csr_outstanding.3694093026
Directory /workspace/3.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_tl_errors.1063291810
Short name T767
Test name
Test status
Simulation time 128929415 ps
CPU time 2.09 seconds
Started Jun 30 04:21:55 PM PDT 24
Finished Jun 30 04:21:59 PM PDT 24
Peak memory 198100 kb
Host smart-0bbf78b1-78f6-4184-8be7-6e4585933aef
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1063291810 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_tl_errors.1063291810
Directory /workspace/3.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_tl_intg_err.1158075444
Short name T47
Test name
Test status
Simulation time 409527107 ps
CPU time 1.35 seconds
Started Jun 30 04:21:54 PM PDT 24
Finished Jun 30 04:21:58 PM PDT 24
Peak memory 198096 kb
Host smart-3600d1a0-6f71-4c2e-b392-71d90814f8b5
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1158075444 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 3.gpio_tl_intg_err.1158075444
Directory /workspace/3.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.gpio_intr_test.4208281646
Short name T834
Test name
Test status
Simulation time 12395090 ps
CPU time 0.56 seconds
Started Jun 30 04:22:50 PM PDT 24
Finished Jun 30 04:22:52 PM PDT 24
Peak memory 194256 kb
Host smart-bb60882f-447c-40a6-89c4-7052aa782aea
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4208281646 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.gpio_intr_test.4208281646
Directory /workspace/30.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.gpio_intr_test.1368145808
Short name T741
Test name
Test status
Simulation time 19297853 ps
CPU time 0.61 seconds
Started Jun 30 04:22:45 PM PDT 24
Finished Jun 30 04:22:48 PM PDT 24
Peak memory 194144 kb
Host smart-15bf3961-b54a-48fe-a96d-f60bba77aa6b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1368145808 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.gpio_intr_test.1368145808
Directory /workspace/31.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.gpio_intr_test.380712183
Short name T732
Test name
Test status
Simulation time 12497545 ps
CPU time 0.59 seconds
Started Jun 30 04:22:50 PM PDT 24
Finished Jun 30 04:22:52 PM PDT 24
Peak memory 194204 kb
Host smart-a28168e3-b102-4365-a62f-2eea3261e186
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=380712183 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.gpio_intr_test.380712183
Directory /workspace/32.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.gpio_intr_test.497639153
Short name T751
Test name
Test status
Simulation time 13601543 ps
CPU time 0.57 seconds
Started Jun 30 04:22:48 PM PDT 24
Finished Jun 30 04:22:51 PM PDT 24
Peak memory 194848 kb
Host smart-9194a36c-1ffa-400d-924f-244158de5149
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=497639153 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.gpio_intr_test.497639153
Directory /workspace/33.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.gpio_intr_test.1023452146
Short name T754
Test name
Test status
Simulation time 41328110 ps
CPU time 0.64 seconds
Started Jun 30 04:22:44 PM PDT 24
Finished Jun 30 04:22:47 PM PDT 24
Peak memory 194148 kb
Host smart-b426619d-1147-484b-9e8a-0d8c33843d21
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1023452146 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.gpio_intr_test.1023452146
Directory /workspace/34.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.gpio_intr_test.79627652
Short name T729
Test name
Test status
Simulation time 20714592 ps
CPU time 0.58 seconds
Started Jun 30 04:22:46 PM PDT 24
Finished Jun 30 04:22:49 PM PDT 24
Peak memory 194236 kb
Host smart-ec310f28-dc2a-4c02-8fb7-3c5c1a21eec9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79627652 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.gpio_intr_test.79627652
Directory /workspace/35.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.gpio_intr_test.3775766258
Short name T727
Test name
Test status
Simulation time 21925793 ps
CPU time 0.66 seconds
Started Jun 30 04:22:44 PM PDT 24
Finished Jun 30 04:22:48 PM PDT 24
Peak memory 194724 kb
Host smart-55b419d4-1b2c-4aab-9e50-ab6d88bd1d23
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3775766258 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.gpio_intr_test.3775766258
Directory /workspace/36.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.gpio_intr_test.3751092462
Short name T833
Test name
Test status
Simulation time 11123664 ps
CPU time 0.57 seconds
Started Jun 30 04:22:46 PM PDT 24
Finished Jun 30 04:22:49 PM PDT 24
Peak memory 194204 kb
Host smart-9bc033f8-3276-46d6-86dd-29ee4167eee8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3751092462 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.gpio_intr_test.3751092462
Directory /workspace/37.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.gpio_intr_test.2380563317
Short name T777
Test name
Test status
Simulation time 235721496 ps
CPU time 0.61 seconds
Started Jun 30 04:22:44 PM PDT 24
Finished Jun 30 04:22:48 PM PDT 24
Peak memory 194276 kb
Host smart-98881a29-edd6-463d-834c-c3b487953121
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2380563317 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.gpio_intr_test.2380563317
Directory /workspace/38.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.gpio_intr_test.2547674939
Short name T797
Test name
Test status
Simulation time 23266462 ps
CPU time 0.63 seconds
Started Jun 30 04:22:47 PM PDT 24
Finished Jun 30 04:22:50 PM PDT 24
Peak memory 194312 kb
Host smart-d086dcd2-14a3-4ffe-b1f6-655e0c3b176e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2547674939 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.gpio_intr_test.2547674939
Directory /workspace/39.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_csr_aliasing.2509362093
Short name T770
Test name
Test status
Simulation time 21832191 ps
CPU time 0.66 seconds
Started Jun 30 04:21:55 PM PDT 24
Finished Jun 30 04:21:57 PM PDT 24
Peak memory 193540 kb
Host smart-b87cf513-718a-46d1-9081-4fcaba800666
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2509362093 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM
_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
4.gpio_csr_aliasing.2509362093
Directory /workspace/4.gpio_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_csr_bit_bash.4192316556
Short name T107
Test name
Test status
Simulation time 81888434 ps
CPU time 2.94 seconds
Started Jun 30 04:22:18 PM PDT 24
Finished Jun 30 04:22:22 PM PDT 24
Peak memory 196044 kb
Host smart-6332bdd8-a2ca-46e6-a797-6d8927177d0f
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4192316556 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_csr_bit_bash.4192316556
Directory /workspace/4.gpio_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_csr_hw_reset.1161708513
Short name T81
Test name
Test status
Simulation time 14070212 ps
CPU time 0.59 seconds
Started Jun 30 04:22:16 PM PDT 24
Finished Jun 30 04:22:18 PM PDT 24
Peak memory 195128 kb
Host smart-f43877ce-e5c2-45aa-ab07-e1164c0ee1c7
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1161708513 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_csr_hw_reset.1161708513
Directory /workspace/4.gpio_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_csr_mem_rw_with_rand_reset.4042868214
Short name T742
Test name
Test status
Simulation time 26180457 ps
CPU time 0.61 seconds
Started Jun 30 04:22:15 PM PDT 24
Finished Jun 30 04:22:17 PM PDT 24
Peak memory 196884 kb
Host smart-3ed75866-d08e-4617-9381-de5a5b61eb75
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4042868214 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_csr_mem_rw_with_rand_reset.4042868214
Directory /workspace/4.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_csr_rw.3229812546
Short name T788
Test name
Test status
Simulation time 15363141 ps
CPU time 0.6 seconds
Started Jun 30 04:20:59 PM PDT 24
Finished Jun 30 04:21:00 PM PDT 24
Peak memory 195640 kb
Host smart-4d66e1ea-ae17-43b5-97b2-a57203c63a6e
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3229812546 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio
_csr_rw.3229812546
Directory /workspace/4.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_intr_test.1943318643
Short name T817
Test name
Test status
Simulation time 29101881 ps
CPU time 0.58 seconds
Started Jun 30 04:22:01 PM PDT 24
Finished Jun 30 04:22:02 PM PDT 24
Peak memory 194124 kb
Host smart-3779f433-973e-4759-9fb8-46d466ac676f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1943318643 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_intr_test.1943318643
Directory /workspace/4.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_same_csr_outstanding.814102760
Short name T72
Test name
Test status
Simulation time 33459562 ps
CPU time 0.84 seconds
Started Jun 30 04:19:22 PM PDT 24
Finished Jun 30 04:19:23 PM PDT 24
Peak memory 196804 kb
Host smart-f4c60276-bdce-484f-93c6-5d9ffb15e710
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=814102760 -assert nopostproc +UVM_TESTNAME=gpio_bas
e_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 4.gpio_same_csr_outstanding.814102760
Directory /workspace/4.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_tl_errors.4086435402
Short name T783
Test name
Test status
Simulation time 187392775 ps
CPU time 2.24 seconds
Started Jun 30 04:22:15 PM PDT 24
Finished Jun 30 04:22:19 PM PDT 24
Peak memory 198512 kb
Host smart-e1d2143d-0e16-4e48-8b8e-f2f17ee43e92
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4086435402 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_tl_errors.4086435402
Directory /workspace/4.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_tl_intg_err.224169766
Short name T842
Test name
Test status
Simulation time 55239891 ps
CPU time 0.91 seconds
Started Jun 30 04:21:54 PM PDT 24
Finished Jun 30 04:21:57 PM PDT 24
Peak memory 196948 kb
Host smart-defbd63c-f300-434c-8b20-52999e4abd0b
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=224169766 -assert nopostproc +UVM_TESTNAME=gpio_base_test +U
VM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 4.gpio_tl_intg_err.224169766
Directory /workspace/4.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.gpio_intr_test.3324609723
Short name T815
Test name
Test status
Simulation time 22873605 ps
CPU time 0.55 seconds
Started Jun 30 04:22:50 PM PDT 24
Finished Jun 30 04:22:52 PM PDT 24
Peak memory 194240 kb
Host smart-9debac94-ad2a-4206-8513-1236faea85cf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3324609723 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.gpio_intr_test.3324609723
Directory /workspace/40.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.gpio_intr_test.187216543
Short name T809
Test name
Test status
Simulation time 47213167 ps
CPU time 0.55 seconds
Started Jun 30 04:22:41 PM PDT 24
Finished Jun 30 04:22:45 PM PDT 24
Peak memory 194192 kb
Host smart-4006c705-13f1-475e-9562-b4f9d2320fba
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=187216543 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.gpio_intr_test.187216543
Directory /workspace/41.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.gpio_intr_test.4109891286
Short name T756
Test name
Test status
Simulation time 62887249 ps
CPU time 0.58 seconds
Started Jun 30 04:22:45 PM PDT 24
Finished Jun 30 04:22:48 PM PDT 24
Peak memory 194888 kb
Host smart-d72936a1-8920-4c98-bdef-bded019a120e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4109891286 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.gpio_intr_test.4109891286
Directory /workspace/42.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.gpio_intr_test.1382382761
Short name T723
Test name
Test status
Simulation time 16128328 ps
CPU time 0.57 seconds
Started Jun 30 04:22:45 PM PDT 24
Finished Jun 30 04:22:48 PM PDT 24
Peak memory 194932 kb
Host smart-4cd473d7-6dc2-4f43-a9ba-7e972771f577
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1382382761 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.gpio_intr_test.1382382761
Directory /workspace/43.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.gpio_intr_test.2082140799
Short name T721
Test name
Test status
Simulation time 12134326 ps
CPU time 0.56 seconds
Started Jun 30 04:22:46 PM PDT 24
Finished Jun 30 04:22:49 PM PDT 24
Peak memory 194188 kb
Host smart-5d15598c-4c5b-45fd-85e9-8a1582672c7e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2082140799 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.gpio_intr_test.2082140799
Directory /workspace/44.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.gpio_intr_test.1579116175
Short name T776
Test name
Test status
Simulation time 15583300 ps
CPU time 0.6 seconds
Started Jun 30 04:22:50 PM PDT 24
Finished Jun 30 04:22:52 PM PDT 24
Peak memory 194224 kb
Host smart-9f758aed-62b3-47ae-b5e8-782e32db4334
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1579116175 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.gpio_intr_test.1579116175
Directory /workspace/45.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.gpio_intr_test.490456117
Short name T725
Test name
Test status
Simulation time 16845900 ps
CPU time 0.59 seconds
Started Jun 30 04:22:43 PM PDT 24
Finished Jun 30 04:22:47 PM PDT 24
Peak memory 194284 kb
Host smart-f4c241e3-4a42-467a-8bc6-fda69bfc17c1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=490456117 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.gpio_intr_test.490456117
Directory /workspace/46.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.gpio_intr_test.3697200830
Short name T823
Test name
Test status
Simulation time 13462732 ps
CPU time 0.57 seconds
Started Jun 30 04:22:44 PM PDT 24
Finished Jun 30 04:22:48 PM PDT 24
Peak memory 194192 kb
Host smart-03e90179-12a6-4ef8-b88f-d821e4041704
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3697200830 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.gpio_intr_test.3697200830
Directory /workspace/47.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.gpio_intr_test.972728124
Short name T761
Test name
Test status
Simulation time 11782801 ps
CPU time 0.62 seconds
Started Jun 30 04:22:51 PM PDT 24
Finished Jun 30 04:22:53 PM PDT 24
Peak memory 194936 kb
Host smart-ad41cf69-6062-4c8a-a3c0-5c0bbb9b01a8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=972728124 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.gpio_intr_test.972728124
Directory /workspace/48.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.gpio_intr_test.1038618688
Short name T748
Test name
Test status
Simulation time 11962462 ps
CPU time 0.6 seconds
Started Jun 30 04:22:49 PM PDT 24
Finished Jun 30 04:22:52 PM PDT 24
Peak memory 194256 kb
Host smart-5391e92f-65c1-4520-91e9-b8138a9917fa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1038618688 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.gpio_intr_test.1038618688
Directory /workspace/49.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_csr_mem_rw_with_rand_reset.1497765905
Short name T824
Test name
Test status
Simulation time 44864254 ps
CPU time 0.65 seconds
Started Jun 30 04:20:42 PM PDT 24
Finished Jun 30 04:20:43 PM PDT 24
Peak memory 197472 kb
Host smart-c4071b39-c13d-44b4-b518-87297c33149f
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1497765905 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.gpio_csr_mem_rw_with_rand_reset.1497765905
Directory /workspace/5.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_csr_rw.3542572621
Short name T804
Test name
Test status
Simulation time 44426751 ps
CPU time 0.66 seconds
Started Jun 30 04:18:57 PM PDT 24
Finished Jun 30 04:18:58 PM PDT 24
Peak memory 195924 kb
Host smart-d7d05b54-49f4-4458-9126-19c8f7194764
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3542572621 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.gpio
_csr_rw.3542572621
Directory /workspace/5.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_intr_test.3985365382
Short name T771
Test name
Test status
Simulation time 64917513 ps
CPU time 0.6 seconds
Started Jun 30 04:22:18 PM PDT 24
Finished Jun 30 04:22:20 PM PDT 24
Peak memory 193156 kb
Host smart-1e85bb76-9c44-4b45-bc8b-ce20b549a025
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3985365382 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.gpio_intr_test.3985365382
Directory /workspace/5.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_same_csr_outstanding.2237872022
Short name T837
Test name
Test status
Simulation time 96960972 ps
CPU time 0.86 seconds
Started Jun 30 04:18:57 PM PDT 24
Finished Jun 30 04:18:58 PM PDT 24
Peak memory 198364 kb
Host smart-ca984f6b-3a6b-4ffe-a31b-1e30ffa02a20
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2237872022 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 5.gpio_same_csr_outstanding.2237872022
Directory /workspace/5.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_tl_errors.2909908307
Short name T794
Test name
Test status
Simulation time 242877766 ps
CPU time 2.56 seconds
Started Jun 30 04:22:18 PM PDT 24
Finished Jun 30 04:22:22 PM PDT 24
Peak memory 197136 kb
Host smart-abb84cfd-081e-4147-a61c-f2b9e2351c4d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2909908307 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.gpio_tl_errors.2909908307
Directory /workspace/5.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_tl_intg_err.1862160374
Short name T785
Test name
Test status
Simulation time 623841812 ps
CPU time 1.19 seconds
Started Jun 30 04:22:30 PM PDT 24
Finished Jun 30 04:22:32 PM PDT 24
Peak memory 197744 kb
Host smart-1c0505ec-7256-448a-a03e-c0ae3eddb009
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1862160374 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 5.gpio_tl_intg_err.1862160374
Directory /workspace/5.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_csr_mem_rw_with_rand_reset.2787133959
Short name T724
Test name
Test status
Simulation time 22588257 ps
CPU time 0.75 seconds
Started Jun 30 04:22:42 PM PDT 24
Finished Jun 30 04:22:46 PM PDT 24
Peak memory 198172 kb
Host smart-0d8a8443-6d77-4191-85ee-0b0cdb41d240
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2787133959 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.gpio_csr_mem_rw_with_rand_reset.2787133959
Directory /workspace/6.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_csr_rw.3605670918
Short name T71
Test name
Test status
Simulation time 52875845 ps
CPU time 0.58 seconds
Started Jun 30 04:22:05 PM PDT 24
Finished Jun 30 04:22:06 PM PDT 24
Peak memory 195192 kb
Host smart-5a4d40c8-991a-4e1d-93f5-8872af23cb57
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3605670918 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.gpio
_csr_rw.3605670918
Directory /workspace/6.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_intr_test.2154163919
Short name T774
Test name
Test status
Simulation time 56078795 ps
CPU time 0.6 seconds
Started Jun 30 04:22:12 PM PDT 24
Finished Jun 30 04:22:14 PM PDT 24
Peak memory 192956 kb
Host smart-9c71ebd9-2c54-453e-998b-efeb5f4a04fa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2154163919 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.gpio_intr_test.2154163919
Directory /workspace/6.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_same_csr_outstanding.396957779
Short name T828
Test name
Test status
Simulation time 51441463 ps
CPU time 0.81 seconds
Started Jun 30 04:22:05 PM PDT 24
Finished Jun 30 04:22:07 PM PDT 24
Peak memory 197408 kb
Host smart-0d869841-411b-454d-8736-6f80b0e33233
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=396957779 -assert nopostproc +UVM_TESTNAME=gpio_bas
e_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 6.gpio_same_csr_outstanding.396957779
Directory /workspace/6.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_tl_errors.3248369674
Short name T832
Test name
Test status
Simulation time 48073573 ps
CPU time 2.41 seconds
Started Jun 30 04:22:12 PM PDT 24
Finished Jun 30 04:22:15 PM PDT 24
Peak memory 197028 kb
Host smart-cf1eba40-089a-43a1-8848-501484afb209
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3248369674 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.gpio_tl_errors.3248369674
Directory /workspace/6.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_tl_intg_err.2575709462
Short name T835
Test name
Test status
Simulation time 302164285 ps
CPU time 1.28 seconds
Started Jun 30 04:18:47 PM PDT 24
Finished Jun 30 04:18:48 PM PDT 24
Peak memory 198524 kb
Host smart-4e095826-21ae-4368-8a66-062b4f5a1df9
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2575709462 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 6.gpio_tl_intg_err.2575709462
Directory /workspace/6.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_csr_mem_rw_with_rand_reset.372213546
Short name T728
Test name
Test status
Simulation time 19416964 ps
CPU time 0.72 seconds
Started Jun 30 04:20:34 PM PDT 24
Finished Jun 30 04:20:35 PM PDT 24
Peak memory 198032 kb
Host smart-659f7341-20d9-460b-a263-81598c6964f0
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=372213546 -asser
t nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.gpio_csr_mem_rw_with_rand_reset.372213546
Directory /workspace/7.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_csr_rw.3615098602
Short name T77
Test name
Test status
Simulation time 28594390 ps
CPU time 0.6 seconds
Started Jun 30 04:22:12 PM PDT 24
Finished Jun 30 04:22:14 PM PDT 24
Peak memory 193900 kb
Host smart-e57a06f2-9e9f-4c8b-896e-e80becfe6643
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3615098602 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.gpio
_csr_rw.3615098602
Directory /workspace/7.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_intr_test.3553184914
Short name T791
Test name
Test status
Simulation time 11490484 ps
CPU time 0.59 seconds
Started Jun 30 04:18:18 PM PDT 24
Finished Jun 30 04:18:19 PM PDT 24
Peak memory 194180 kb
Host smart-a28e6705-f685-4fc5-8968-093266bfc759
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3553184914 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.gpio_intr_test.3553184914
Directory /workspace/7.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_same_csr_outstanding.1960290524
Short name T91
Test name
Test status
Simulation time 45249404 ps
CPU time 0.6 seconds
Started Jun 30 04:22:10 PM PDT 24
Finished Jun 30 04:22:13 PM PDT 24
Peak memory 194568 kb
Host smart-d441c2a6-bc80-438d-bdd1-dfbd87a651f9
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1960290524 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 7.gpio_same_csr_outstanding.1960290524
Directory /workspace/7.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_tl_errors.3939867434
Short name T735
Test name
Test status
Simulation time 145129732 ps
CPU time 2.49 seconds
Started Jun 30 04:19:32 PM PDT 24
Finished Jun 30 04:19:35 PM PDT 24
Peak memory 198972 kb
Host smart-4f3ef5c8-3164-444c-91d7-9bd7306829b9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3939867434 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.gpio_tl_errors.3939867434
Directory /workspace/7.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_tl_intg_err.1005021304
Short name T36
Test name
Test status
Simulation time 633041324 ps
CPU time 1.56 seconds
Started Jun 30 04:22:13 PM PDT 24
Finished Jun 30 04:22:16 PM PDT 24
Peak memory 198328 kb
Host smart-d3119602-b7d0-4f5a-86cd-fc26c91fa88c
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1005021304 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 7.gpio_tl_intg_err.1005021304
Directory /workspace/7.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_csr_mem_rw_with_rand_reset.3974317256
Short name T722
Test name
Test status
Simulation time 341543272 ps
CPU time 1.1 seconds
Started Jun 30 04:22:52 PM PDT 24
Finished Jun 30 04:22:55 PM PDT 24
Peak memory 198520 kb
Host smart-5e17f5ff-1a9c-4c52-9436-ddbacb25cfea
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3974317256 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.gpio_csr_mem_rw_with_rand_reset.3974317256
Directory /workspace/8.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_csr_rw.1846046748
Short name T73
Test name
Test status
Simulation time 29609625 ps
CPU time 0.61 seconds
Started Jun 30 04:19:22 PM PDT 24
Finished Jun 30 04:19:23 PM PDT 24
Peak memory 195804 kb
Host smart-616aa442-accc-42d6-a9c9-ea9d93a6df25
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1846046748 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.gpio
_csr_rw.1846046748
Directory /workspace/8.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_intr_test.3671937120
Short name T786
Test name
Test status
Simulation time 21579119 ps
CPU time 0.63 seconds
Started Jun 30 04:21:53 PM PDT 24
Finished Jun 30 04:21:55 PM PDT 24
Peak memory 193880 kb
Host smart-3af009e8-4531-4a95-8c84-ce04f88b8b80
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3671937120 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.gpio_intr_test.3671937120
Directory /workspace/8.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_same_csr_outstanding.416081942
Short name T818
Test name
Test status
Simulation time 98721732 ps
CPU time 0.82 seconds
Started Jun 30 04:22:18 PM PDT 24
Finished Jun 30 04:22:20 PM PDT 24
Peak memory 194964 kb
Host smart-0825c713-01f2-47a9-bed4-37ede09fc24e
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=416081942 -assert nopostproc +UVM_TESTNAME=gpio_bas
e_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 8.gpio_same_csr_outstanding.416081942
Directory /workspace/8.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_tl_errors.2635075112
Short name T820
Test name
Test status
Simulation time 24203445 ps
CPU time 1.2 seconds
Started Jun 30 04:22:06 PM PDT 24
Finished Jun 30 04:22:09 PM PDT 24
Peak memory 198488 kb
Host smart-e53816d4-1c20-4f97-96db-533b5be18cb5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2635075112 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.gpio_tl_errors.2635075112
Directory /workspace/8.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_tl_intg_err.1448375329
Short name T836
Test name
Test status
Simulation time 42190356 ps
CPU time 0.9 seconds
Started Jun 30 04:18:59 PM PDT 24
Finished Jun 30 04:19:00 PM PDT 24
Peak memory 197812 kb
Host smart-623dd298-d30f-41ac-9aed-bf5c1a75916e
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1448375329 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 8.gpio_tl_intg_err.1448375329
Directory /workspace/8.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_csr_mem_rw_with_rand_reset.1586934280
Short name T841
Test name
Test status
Simulation time 20830978 ps
CPU time 0.71 seconds
Started Jun 30 04:23:08 PM PDT 24
Finished Jun 30 04:23:09 PM PDT 24
Peak memory 197656 kb
Host smart-7e4e2881-5c40-4d7e-95ff-1ddd66b427c0
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1586934280 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.gpio_csr_mem_rw_with_rand_reset.1586934280
Directory /workspace/9.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_csr_rw.2108701300
Short name T84
Test name
Test status
Simulation time 52146889 ps
CPU time 0.63 seconds
Started Jun 30 04:20:04 PM PDT 24
Finished Jun 30 04:20:05 PM PDT 24
Peak memory 195296 kb
Host smart-699b57be-af17-442d-a9ff-378c22d76dfd
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2108701300 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.gpio
_csr_rw.2108701300
Directory /workspace/9.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_intr_test.170637984
Short name T752
Test name
Test status
Simulation time 18128826 ps
CPU time 0.58 seconds
Started Jun 30 04:17:29 PM PDT 24
Finished Jun 30 04:17:30 PM PDT 24
Peak memory 194844 kb
Host smart-7851d4e5-49f1-4a4c-9a83-cacd79c6c70c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=170637984 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.gpio_intr_test.170637984
Directory /workspace/9.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_same_csr_outstanding.3170868338
Short name T75
Test name
Test status
Simulation time 21149008 ps
CPU time 0.88 seconds
Started Jun 30 04:20:02 PM PDT 24
Finished Jun 30 04:20:03 PM PDT 24
Peak memory 197184 kb
Host smart-e00d1210-7f6a-4fae-94c6-7ef9b3da8abd
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3170868338 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 9.gpio_same_csr_outstanding.3170868338
Directory /workspace/9.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_tl_errors.976259072
Short name T730
Test name
Test status
Simulation time 221280018 ps
CPU time 2.33 seconds
Started Jun 30 04:18:51 PM PDT 24
Finished Jun 30 04:18:53 PM PDT 24
Peak memory 198504 kb
Host smart-27e55d7e-f084-49b0-87f6-b26628deb5a7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=976259072 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.gpio_tl_errors.976259072
Directory /workspace/9.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_tl_intg_err.1084513928
Short name T109
Test name
Test status
Simulation time 120902535 ps
CPU time 1.46 seconds
Started Jun 30 04:21:52 PM PDT 24
Finished Jun 30 04:21:54 PM PDT 24
Peak memory 197340 kb
Host smart-aaec483c-c584-4811-b978-d4c54e6fb776
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1084513928 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 9.gpio_tl_intg_err.1084513928
Directory /workspace/9.gpio_tl_intg_err/latest

Test location /workspace/coverage/default/0.gpio_alert_test.3499113834
Short name T569
Test name
Test status
Simulation time 25868617 ps
CPU time 0.59 seconds
Started Jun 30 04:19:05 PM PDT 24
Finished Jun 30 04:19:06 PM PDT 24
Peak memory 195192 kb
Host smart-f5036dee-043c-4065-a38e-5efc7e307bc5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3499113834 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_alert_test.3499113834
Directory /workspace/0.gpio_alert_test/latest

Test location /workspace/coverage/default/0.gpio_dout_din_regs_random_rw.4009050178
Short name T435
Test name
Test status
Simulation time 18080543 ps
CPU time 0.67 seconds
Started Jun 30 04:20:46 PM PDT 24
Finished Jun 30 04:20:48 PM PDT 24
Peak memory 194516 kb
Host smart-307116ee-ec7b-4d36-a10c-0a8facb5d394
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4009050178 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_dout_din_regs_random_rw.4009050178
Directory /workspace/0.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/0.gpio_filter_stress.11524106
Short name T204
Test name
Test status
Simulation time 3697916689 ps
CPU time 27.1 seconds
Started Jun 30 04:22:42 PM PDT 24
Finished Jun 30 04:23:13 PM PDT 24
Peak memory 198368 kb
Host smart-3036fe8c-746e-48e0-87ae-8a0086007a20
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11524106 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter_
stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_filter_stress.11524106
Directory /workspace/0.gpio_filter_stress/latest

Test location /workspace/coverage/default/0.gpio_full_random.420363504
Short name T524
Test name
Test status
Simulation time 57075023 ps
CPU time 0.85 seconds
Started Jun 30 04:20:16 PM PDT 24
Finished Jun 30 04:20:17 PM PDT 24
Peak memory 197212 kb
Host smart-5fb36329-1278-4621-be66-6c8a55934015
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=420363504 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_full_random.420363504
Directory /workspace/0.gpio_full_random/latest

Test location /workspace/coverage/default/0.gpio_intr_rand_pgm.4170177446
Short name T329
Test name
Test status
Simulation time 39012909 ps
CPU time 0.87 seconds
Started Jun 30 04:21:52 PM PDT 24
Finished Jun 30 04:21:54 PM PDT 24
Peak memory 196724 kb
Host smart-b837f53e-c0c4-41fc-b4ef-bffc92dbadcc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4170177446 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_intr_rand_pgm.4170177446
Directory /workspace/0.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/0.gpio_intr_with_filter_rand_intr_event.21509250
Short name T717
Test name
Test status
Simulation time 260214761 ps
CPU time 2.9 seconds
Started Jun 30 04:22:50 PM PDT 24
Finished Jun 30 04:22:54 PM PDT 24
Peak memory 198584 kb
Host smart-9171d7e1-34a8-4243-95b4-5120a06675c5
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21509250 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 0.gpio_intr_with_filter_rand_intr_event.21509250
Directory /workspace/0.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/0.gpio_rand_intr_trigger.1040970065
Short name T676
Test name
Test status
Simulation time 122370326 ps
CPU time 3.14 seconds
Started Jun 30 04:22:16 PM PDT 24
Finished Jun 30 04:22:20 PM PDT 24
Peak memory 197192 kb
Host smart-985d25f4-a889-4e89-8cb2-9ef2e615d9c9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1040970065 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_rand_intr_trigger.
1040970065
Directory /workspace/0.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/0.gpio_random_dout_din.641967162
Short name T155
Test name
Test status
Simulation time 236320704 ps
CPU time 0.72 seconds
Started Jun 30 04:18:49 PM PDT 24
Finished Jun 30 04:18:50 PM PDT 24
Peak memory 195860 kb
Host smart-c9e0ca20-3d49-4fff-b7f0-03b7f4d0aa5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=641967162 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_random_dout_din.641967162
Directory /workspace/0.gpio_random_dout_din/latest

Test location /workspace/coverage/default/0.gpio_random_dout_din_no_pullup_pulldown.508934273
Short name T259
Test name
Test status
Simulation time 61914740 ps
CPU time 0.88 seconds
Started Jun 30 04:19:52 PM PDT 24
Finished Jun 30 04:19:53 PM PDT 24
Peak memory 196416 kb
Host smart-2716072c-8fd5-4255-a861-d1d0e0d5cfde
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=508934273 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_random_dout_din_no_pullup_
pulldown.508934273
Directory /workspace/0.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/0.gpio_random_long_reg_writes_reg_reads.93155609
Short name T640
Test name
Test status
Simulation time 504810633 ps
CPU time 3 seconds
Started Jun 30 04:20:09 PM PDT 24
Finished Jun 30 04:20:13 PM PDT 24
Peak memory 198452 kb
Host smart-1f212167-0b37-45ef-bf45-669ceb1140d5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93155609 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_w
rites_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_rando
m_long_reg_writes_reg_reads.93155609
Directory /workspace/0.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/0.gpio_smoke.1408890689
Short name T675
Test name
Test status
Simulation time 104699475 ps
CPU time 1.22 seconds
Started Jun 30 04:22:52 PM PDT 24
Finished Jun 30 04:22:55 PM PDT 24
Peak memory 196420 kb
Host smart-aba6ac49-5334-4f3a-984e-4b727e34002e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1408890689 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_smoke.1408890689
Directory /workspace/0.gpio_smoke/latest

Test location /workspace/coverage/default/0.gpio_smoke_no_pullup_pulldown.4053822827
Short name T606
Test name
Test status
Simulation time 39460471 ps
CPU time 1.08 seconds
Started Jun 30 04:22:52 PM PDT 24
Finished Jun 30 04:22:55 PM PDT 24
Peak memory 196204 kb
Host smart-b9be7689-7c80-4ab3-b14b-491fbc97be98
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4053822827 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_smoke_no_pullup_pulldown.4053822827
Directory /workspace/0.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/0.gpio_stress_all.3000728857
Short name T577
Test name
Test status
Simulation time 5701344288 ps
CPU time 137.17 seconds
Started Jun 30 04:22:08 PM PDT 24
Finished Jun 30 04:24:28 PM PDT 24
Peak memory 198260 kb
Host smart-cce8812f-87e4-444a-9993-2c2c26224af1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3000728857 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.g
pio_stress_all.3000728857
Directory /workspace/0.gpio_stress_all/latest

Test location /workspace/coverage/default/1.gpio_alert_test.3604452117
Short name T358
Test name
Test status
Simulation time 37966089 ps
CPU time 0.59 seconds
Started Jun 30 04:19:04 PM PDT 24
Finished Jun 30 04:19:05 PM PDT 24
Peak memory 194488 kb
Host smart-1ce1db1c-f19e-48c9-8b57-5936812e3d25
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3604452117 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_alert_test.3604452117
Directory /workspace/1.gpio_alert_test/latest

Test location /workspace/coverage/default/1.gpio_dout_din_regs_random_rw.4089074202
Short name T499
Test name
Test status
Simulation time 22499827 ps
CPU time 0.76 seconds
Started Jun 30 04:21:57 PM PDT 24
Finished Jun 30 04:21:59 PM PDT 24
Peak memory 195528 kb
Host smart-8dc85fb0-6a2f-43e7-adbc-e6a336ef6182
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4089074202 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_dout_din_regs_random_rw.4089074202
Directory /workspace/1.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/1.gpio_filter_stress.2555075474
Short name T389
Test name
Test status
Simulation time 441219396 ps
CPU time 15.83 seconds
Started Jun 30 04:18:29 PM PDT 24
Finished Jun 30 04:18:46 PM PDT 24
Peak memory 198504 kb
Host smart-8c2e5244-5e26-4b8b-a948-92bf81ae756e
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2555075474 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_filter_stres
s.2555075474
Directory /workspace/1.gpio_filter_stress/latest

Test location /workspace/coverage/default/1.gpio_full_random.1728567089
Short name T22
Test name
Test status
Simulation time 172657934 ps
CPU time 0.75 seconds
Started Jun 30 04:22:19 PM PDT 24
Finished Jun 30 04:22:21 PM PDT 24
Peak memory 196172 kb
Host smart-e509e5ae-68f0-4f47-a9dd-7ef04d63b006
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1728567089 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_full_random.1728567089
Directory /workspace/1.gpio_full_random/latest

Test location /workspace/coverage/default/1.gpio_intr_rand_pgm.1608650700
Short name T441
Test name
Test status
Simulation time 210781150 ps
CPU time 1.43 seconds
Started Jun 30 04:20:01 PM PDT 24
Finished Jun 30 04:20:02 PM PDT 24
Peak memory 197584 kb
Host smart-751ad1be-dc79-42d8-9ef4-7ffa204fdc96
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1608650700 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_intr_rand_pgm.1608650700
Directory /workspace/1.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/1.gpio_intr_with_filter_rand_intr_event.1816822918
Short name T371
Test name
Test status
Simulation time 213041023 ps
CPU time 2.13 seconds
Started Jun 30 04:22:13 PM PDT 24
Finished Jun 30 04:22:16 PM PDT 24
Peak memory 198320 kb
Host smart-416334b5-2236-4949-abc9-bc2fbded03f1
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1816822918 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 1.gpio_intr_with_filter_rand_intr_event.1816822918
Directory /workspace/1.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/1.gpio_rand_intr_trigger.3081842596
Short name T177
Test name
Test status
Simulation time 66888664 ps
CPU time 1.5 seconds
Started Jun 30 04:22:13 PM PDT 24
Finished Jun 30 04:22:15 PM PDT 24
Peak memory 196292 kb
Host smart-6bbe3fe2-2913-47d0-8467-f684d0f44f44
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3081842596 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_rand_intr_trigger.
3081842596
Directory /workspace/1.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/1.gpio_random_dout_din.2546108488
Short name T637
Test name
Test status
Simulation time 217238401 ps
CPU time 1.07 seconds
Started Jun 30 04:22:41 PM PDT 24
Finished Jun 30 04:22:46 PM PDT 24
Peak memory 198020 kb
Host smart-826aefa0-275d-4449-a6d9-3e9a603ad6e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2546108488 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_random_dout_din.2546108488
Directory /workspace/1.gpio_random_dout_din/latest

Test location /workspace/coverage/default/1.gpio_random_dout_din_no_pullup_pulldown.4075385301
Short name T130
Test name
Test status
Simulation time 23822459 ps
CPU time 0.87 seconds
Started Jun 30 04:22:41 PM PDT 24
Finished Jun 30 04:22:46 PM PDT 24
Peak memory 196024 kb
Host smart-2ce388ca-d234-4dfa-9ffb-4f540a43092b
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4075385301 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_random_dout_din_no_pullup
_pulldown.4075385301
Directory /workspace/1.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/1.gpio_random_long_reg_writes_reg_reads.23076146
Short name T665
Test name
Test status
Simulation time 476567999 ps
CPU time 3.17 seconds
Started Jun 30 04:20:55 PM PDT 24
Finished Jun 30 04:20:58 PM PDT 24
Peak memory 198484 kb
Host smart-ddc91875-fb68-43fa-a064-c639a42edf65
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23076146 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_w
rites_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_rando
m_long_reg_writes_reg_reads.23076146
Directory /workspace/1.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/1.gpio_sec_cm.4073063277
Short name T49
Test name
Test status
Simulation time 55495847 ps
CPU time 0.91 seconds
Started Jun 30 04:22:18 PM PDT 24
Finished Jun 30 04:22:20 PM PDT 24
Peak memory 212604 kb
Host smart-4cebbe71-80e9-4ba8-9acb-388e52989bc5
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4073063277 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_sec_cm.4073063277
Directory /workspace/1.gpio_sec_cm/latest

Test location /workspace/coverage/default/1.gpio_smoke.2185970057
Short name T233
Test name
Test status
Simulation time 122960055 ps
CPU time 1.17 seconds
Started Jun 30 04:22:15 PM PDT 24
Finished Jun 30 04:22:18 PM PDT 24
Peak memory 195976 kb
Host smart-603aec15-01a5-4956-911c-3d316a4be6f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2185970057 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_smoke.2185970057
Directory /workspace/1.gpio_smoke/latest

Test location /workspace/coverage/default/1.gpio_smoke_no_pullup_pulldown.1096339820
Short name T696
Test name
Test status
Simulation time 247274948 ps
CPU time 1.44 seconds
Started Jun 30 04:20:42 PM PDT 24
Finished Jun 30 04:20:44 PM PDT 24
Peak memory 197272 kb
Host smart-04e4f71b-b154-415c-96b9-19833ee51691
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1096339820 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_smoke_no_pullup_pulldown.1096339820
Directory /workspace/1.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/1.gpio_stress_all.1087889229
Short name T448
Test name
Test status
Simulation time 7192848500 ps
CPU time 85.71 seconds
Started Jun 30 04:19:42 PM PDT 24
Finished Jun 30 04:21:09 PM PDT 24
Peak memory 198600 kb
Host smart-59c13204-2559-4250-8de2-fed05a3bfa00
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1087889229 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.g
pio_stress_all.1087889229
Directory /workspace/1.gpio_stress_all/latest

Test location /workspace/coverage/default/10.gpio_alert_test.1933590259
Short name T228
Test name
Test status
Simulation time 19632885 ps
CPU time 0.56 seconds
Started Jun 30 04:23:16 PM PDT 24
Finished Jun 30 04:23:18 PM PDT 24
Peak memory 195352 kb
Host smart-fd6afbf1-9ead-4f8a-a96b-a88acd722170
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1933590259 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_alert_test.1933590259
Directory /workspace/10.gpio_alert_test/latest

Test location /workspace/coverage/default/10.gpio_dout_din_regs_random_rw.1243914018
Short name T473
Test name
Test status
Simulation time 31238134 ps
CPU time 0.79 seconds
Started Jun 30 04:23:26 PM PDT 24
Finished Jun 30 04:23:27 PM PDT 24
Peak memory 196536 kb
Host smart-74a98284-9365-4b32-8dad-ab18f313aac7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1243914018 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_dout_din_regs_random_rw.1243914018
Directory /workspace/10.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/10.gpio_filter_stress.3157171125
Short name T192
Test name
Test status
Simulation time 130292939 ps
CPU time 6.98 seconds
Started Jun 30 04:23:14 PM PDT 24
Finished Jun 30 04:23:22 PM PDT 24
Peak memory 196004 kb
Host smart-24ff0a7c-ca85-429c-b58a-54fab23667d6
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3157171125 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_filter_stre
ss.3157171125
Directory /workspace/10.gpio_filter_stress/latest

Test location /workspace/coverage/default/10.gpio_full_random.2328063547
Short name T242
Test name
Test status
Simulation time 278089660 ps
CPU time 0.72 seconds
Started Jun 30 04:23:17 PM PDT 24
Finished Jun 30 04:23:19 PM PDT 24
Peak memory 195108 kb
Host smart-12749c33-80f8-4698-92a4-dcfa96b8cd36
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2328063547 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_full_random.2328063547
Directory /workspace/10.gpio_full_random/latest

Test location /workspace/coverage/default/10.gpio_intr_rand_pgm.2979986983
Short name T465
Test name
Test status
Simulation time 33318476 ps
CPU time 0.79 seconds
Started Jun 30 04:23:16 PM PDT 24
Finished Jun 30 04:23:19 PM PDT 24
Peak memory 196052 kb
Host smart-8ae19ce6-3685-45a3-9c0a-e5b10b45e163
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2979986983 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_intr_rand_pgm.2979986983
Directory /workspace/10.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/10.gpio_intr_with_filter_rand_intr_event.1126599355
Short name T346
Test name
Test status
Simulation time 26881149 ps
CPU time 1.13 seconds
Started Jun 30 04:23:16 PM PDT 24
Finished Jun 30 04:23:19 PM PDT 24
Peak memory 197692 kb
Host smart-d8886f9c-62ad-4da9-9e38-df700e4de570
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1126599355 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 10.gpio_intr_with_filter_rand_intr_event.1126599355
Directory /workspace/10.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/10.gpio_rand_intr_trigger.2121401503
Short name T319
Test name
Test status
Simulation time 95121815 ps
CPU time 1.55 seconds
Started Jun 30 04:23:19 PM PDT 24
Finished Jun 30 04:23:25 PM PDT 24
Peak memory 197216 kb
Host smart-56733805-6fe2-4d54-81f8-5c51458b4f8e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2121401503 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_rand_intr_trigger
.2121401503
Directory /workspace/10.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/10.gpio_random_dout_din.3160581748
Short name T276
Test name
Test status
Simulation time 68471932 ps
CPU time 0.8 seconds
Started Jun 30 04:23:09 PM PDT 24
Finished Jun 30 04:23:10 PM PDT 24
Peak memory 197356 kb
Host smart-76919759-0e54-4ba4-9b35-01a73bb2a83e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3160581748 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_random_dout_din.3160581748
Directory /workspace/10.gpio_random_dout_din/latest

Test location /workspace/coverage/default/10.gpio_random_dout_din_no_pullup_pulldown.4194850538
Short name T310
Test name
Test status
Simulation time 44135993 ps
CPU time 0.9 seconds
Started Jun 30 04:23:17 PM PDT 24
Finished Jun 30 04:23:20 PM PDT 24
Peak memory 196384 kb
Host smart-94992638-7721-473f-b5b6-ce7884acab83
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4194850538 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_random_dout_din_no_pullu
p_pulldown.4194850538
Directory /workspace/10.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/10.gpio_random_long_reg_writes_reg_reads.3223736372
Short name T292
Test name
Test status
Simulation time 48070180 ps
CPU time 2.29 seconds
Started Jun 30 04:23:18 PM PDT 24
Finished Jun 30 04:23:22 PM PDT 24
Peak memory 198492 kb
Host smart-53d09109-1be7-4c87-b0ac-ee69f50d4117
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3223736372 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_ra
ndom_long_reg_writes_reg_reads.3223736372
Directory /workspace/10.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/10.gpio_smoke.433054149
Short name T595
Test name
Test status
Simulation time 78472587 ps
CPU time 0.79 seconds
Started Jun 30 04:23:15 PM PDT 24
Finished Jun 30 04:23:17 PM PDT 24
Peak memory 195624 kb
Host smart-bc78449c-c471-46f3-bd29-71a900b474ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=433054149 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_smoke.433054149
Directory /workspace/10.gpio_smoke/latest

Test location /workspace/coverage/default/10.gpio_smoke_no_pullup_pulldown.1468351427
Short name T98
Test name
Test status
Simulation time 162391578 ps
CPU time 1.09 seconds
Started Jun 30 04:23:21 PM PDT 24
Finished Jun 30 04:23:23 PM PDT 24
Peak memory 196396 kb
Host smart-fb1e574d-11fa-4136-b959-c198bbefdf4c
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1468351427 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_smoke_no_pullup_pulldown.1468351427
Directory /workspace/10.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/10.gpio_stress_all.2076082315
Short name T479
Test name
Test status
Simulation time 3874020601 ps
CPU time 52.41 seconds
Started Jun 30 04:23:18 PM PDT 24
Finished Jun 30 04:24:12 PM PDT 24
Peak memory 198552 kb
Host smart-7ad62d73-0c6b-4d19-9c77-78b0e30bdf01
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2076082315 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.
gpio_stress_all.2076082315
Directory /workspace/10.gpio_stress_all/latest

Test location /workspace/coverage/default/11.gpio_alert_test.149808234
Short name T620
Test name
Test status
Simulation time 97325792 ps
CPU time 0.54 seconds
Started Jun 30 04:23:14 PM PDT 24
Finished Jun 30 04:23:16 PM PDT 24
Peak memory 194332 kb
Host smart-e6361e38-0760-4c9c-9fce-cf4920395340
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=149808234 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_alert_test.149808234
Directory /workspace/11.gpio_alert_test/latest

Test location /workspace/coverage/default/11.gpio_dout_din_regs_random_rw.428567580
Short name T96
Test name
Test status
Simulation time 21205711 ps
CPU time 0.72 seconds
Started Jun 30 04:23:16 PM PDT 24
Finished Jun 30 04:23:18 PM PDT 24
Peak memory 195764 kb
Host smart-30ba53b1-5276-4d1d-b4b1-faa1a57a1675
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=428567580 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_dout_din_regs_random_rw.428567580
Directory /workspace/11.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/11.gpio_filter_stress.1302639700
Short name T142
Test name
Test status
Simulation time 310184972 ps
CPU time 15.54 seconds
Started Jun 30 04:23:22 PM PDT 24
Finished Jun 30 04:23:38 PM PDT 24
Peak memory 197308 kb
Host smart-7333b12c-c7eb-48d0-837f-48116af4ba6a
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1302639700 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_filter_stre
ss.1302639700
Directory /workspace/11.gpio_filter_stress/latest

Test location /workspace/coverage/default/11.gpio_full_random.1756953782
Short name T374
Test name
Test status
Simulation time 137268605 ps
CPU time 0.96 seconds
Started Jun 30 04:23:24 PM PDT 24
Finished Jun 30 04:23:26 PM PDT 24
Peak memory 198332 kb
Host smart-9fe3c063-15c0-4438-8275-8a1e9d5a04a8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1756953782 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_full_random.1756953782
Directory /workspace/11.gpio_full_random/latest

Test location /workspace/coverage/default/11.gpio_intr_rand_pgm.2628264962
Short name T62
Test name
Test status
Simulation time 14677352 ps
CPU time 0.63 seconds
Started Jun 30 04:23:16 PM PDT 24
Finished Jun 30 04:23:18 PM PDT 24
Peak memory 194720 kb
Host smart-9b783603-2a0b-45a6-acf3-97ff55387065
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2628264962 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_intr_rand_pgm.2628264962
Directory /workspace/11.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/11.gpio_intr_with_filter_rand_intr_event.3667927656
Short name T467
Test name
Test status
Simulation time 255961129 ps
CPU time 1.83 seconds
Started Jun 30 04:23:21 PM PDT 24
Finished Jun 30 04:23:24 PM PDT 24
Peak memory 198608 kb
Host smart-8ed0bd48-f9e9-4386-b4c4-79b3eea9b4b1
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3667927656 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 11.gpio_intr_with_filter_rand_intr_event.3667927656
Directory /workspace/11.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/11.gpio_rand_intr_trigger.258875863
Short name T559
Test name
Test status
Simulation time 207754169 ps
CPU time 1.6 seconds
Started Jun 30 04:23:14 PM PDT 24
Finished Jun 30 04:23:17 PM PDT 24
Peak memory 196476 kb
Host smart-4bee0589-464e-4557-bfb6-008c7f5f9198
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=258875863 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_rand_intr_trigger.
258875863
Directory /workspace/11.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/11.gpio_random_dout_din.3278391703
Short name T530
Test name
Test status
Simulation time 30315790 ps
CPU time 1.03 seconds
Started Jun 30 04:23:16 PM PDT 24
Finished Jun 30 04:23:19 PM PDT 24
Peak memory 197284 kb
Host smart-6e90c3fc-8ff8-4ff3-8737-ce860d8db4a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3278391703 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_random_dout_din.3278391703
Directory /workspace/11.gpio_random_dout_din/latest

Test location /workspace/coverage/default/11.gpio_random_dout_din_no_pullup_pulldown.262763941
Short name T313
Test name
Test status
Simulation time 70768139 ps
CPU time 0.91 seconds
Started Jun 30 04:23:19 PM PDT 24
Finished Jun 30 04:23:21 PM PDT 24
Peak memory 196476 kb
Host smart-d361bc8d-fe49-459c-bea5-8c321c045b5d
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=262763941 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_random_dout_din_no_pullup
_pulldown.262763941
Directory /workspace/11.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/11.gpio_random_long_reg_writes_reg_reads.575456122
Short name T218
Test name
Test status
Simulation time 49488205 ps
CPU time 2.07 seconds
Started Jun 30 04:23:11 PM PDT 24
Finished Jun 30 04:23:14 PM PDT 24
Peak memory 198432 kb
Host smart-788443e3-60f6-4e02-a230-385f2f4c4788
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=575456122 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_ran
dom_long_reg_writes_reg_reads.575456122
Directory /workspace/11.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/11.gpio_smoke.2268958654
Short name T143
Test name
Test status
Simulation time 92501080 ps
CPU time 0.92 seconds
Started Jun 30 04:23:13 PM PDT 24
Finished Jun 30 04:23:15 PM PDT 24
Peak memory 196208 kb
Host smart-2d8c53a0-06a0-4631-9035-55178ad8eb5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2268958654 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_smoke.2268958654
Directory /workspace/11.gpio_smoke/latest

Test location /workspace/coverage/default/11.gpio_smoke_no_pullup_pulldown.1292937338
Short name T114
Test name
Test status
Simulation time 125109142 ps
CPU time 0.74 seconds
Started Jun 30 04:23:15 PM PDT 24
Finished Jun 30 04:23:22 PM PDT 24
Peak memory 196452 kb
Host smart-46ebf0fc-87da-40c4-8831-882fc525281a
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1292937338 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_smoke_no_pullup_pulldown.1292937338
Directory /workspace/11.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/11.gpio_stress_all.1960604372
Short name T363
Test name
Test status
Simulation time 1717753760 ps
CPU time 18.88 seconds
Started Jun 30 04:23:12 PM PDT 24
Finished Jun 30 04:23:32 PM PDT 24
Peak memory 198284 kb
Host smart-36fdd6c1-f987-4f2f-832f-6842309c740a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1960604372 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.
gpio_stress_all.1960604372
Directory /workspace/11.gpio_stress_all/latest

Test location /workspace/coverage/default/12.gpio_alert_test.1032012
Short name T716
Test name
Test status
Simulation time 16967352 ps
CPU time 0.55 seconds
Started Jun 30 04:23:18 PM PDT 24
Finished Jun 30 04:23:20 PM PDT 24
Peak memory 194728 kb
Host smart-a73126de-e2ee-4dfa-afb4-24bfc73db19f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1032012 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_alert_test.1032012
Directory /workspace/12.gpio_alert_test/latest

Test location /workspace/coverage/default/12.gpio_dout_din_regs_random_rw.1147606816
Short name T179
Test name
Test status
Simulation time 27551293 ps
CPU time 0.84 seconds
Started Jun 30 04:23:10 PM PDT 24
Finished Jun 30 04:23:11 PM PDT 24
Peak memory 196976 kb
Host smart-22b8b292-4215-43ef-a53b-128f86bb82ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1147606816 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_dout_din_regs_random_rw.1147606816
Directory /workspace/12.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/12.gpio_filter_stress.537936381
Short name T632
Test name
Test status
Simulation time 442753975 ps
CPU time 7.83 seconds
Started Jun 30 04:23:14 PM PDT 24
Finished Jun 30 04:23:23 PM PDT 24
Peak memory 197508 kb
Host smart-7a6821ef-a13e-4c7c-928b-729d1f45f3a2
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=537936381 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_filter_stres
s.537936381
Directory /workspace/12.gpio_filter_stress/latest

Test location /workspace/coverage/default/12.gpio_full_random.1043159495
Short name T293
Test name
Test status
Simulation time 88373722 ps
CPU time 1.01 seconds
Started Jun 30 04:23:14 PM PDT 24
Finished Jun 30 04:23:16 PM PDT 24
Peak memory 198344 kb
Host smart-ebd3e40d-0df4-4186-af7d-ab662adb8be3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1043159495 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_full_random.1043159495
Directory /workspace/12.gpio_full_random/latest

Test location /workspace/coverage/default/12.gpio_intr_rand_pgm.1972148203
Short name T517
Test name
Test status
Simulation time 153459561 ps
CPU time 1.11 seconds
Started Jun 30 04:23:18 PM PDT 24
Finished Jun 30 04:23:25 PM PDT 24
Peak memory 196212 kb
Host smart-9f0dd552-4380-45ff-a063-9f13c1c985a9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1972148203 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_intr_rand_pgm.1972148203
Directory /workspace/12.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/12.gpio_intr_with_filter_rand_intr_event.222643440
Short name T386
Test name
Test status
Simulation time 165455278 ps
CPU time 0.91 seconds
Started Jun 30 04:23:18 PM PDT 24
Finished Jun 30 04:23:20 PM PDT 24
Peak memory 196604 kb
Host smart-bb1e2f72-3aa9-4d78-a715-e949cb80d098
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=222643440 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 12.gpio_intr_with_filter_rand_intr_event.222643440
Directory /workspace/12.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/12.gpio_rand_intr_trigger.2451642382
Short name T424
Test name
Test status
Simulation time 88544257 ps
CPU time 2.57 seconds
Started Jun 30 04:23:15 PM PDT 24
Finished Jun 30 04:23:18 PM PDT 24
Peak memory 197612 kb
Host smart-fda783a9-9a90-410f-9905-7a6bbef33d69
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2451642382 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_rand_intr_trigger
.2451642382
Directory /workspace/12.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/12.gpio_random_dout_din.3419471356
Short name T509
Test name
Test status
Simulation time 19571030 ps
CPU time 0.86 seconds
Started Jun 30 04:23:16 PM PDT 24
Finished Jun 30 04:23:18 PM PDT 24
Peak memory 197044 kb
Host smart-9f24fafc-72ab-4ba7-978a-fbc4efe94d36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3419471356 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_random_dout_din.3419471356
Directory /workspace/12.gpio_random_dout_din/latest

Test location /workspace/coverage/default/12.gpio_random_dout_din_no_pullup_pulldown.3140601807
Short name T669
Test name
Test status
Simulation time 104705230 ps
CPU time 1.13 seconds
Started Jun 30 04:23:07 PM PDT 24
Finished Jun 30 04:23:09 PM PDT 24
Peak memory 196580 kb
Host smart-20ac725e-f332-452a-b359-0663c6bf89d4
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3140601807 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_random_dout_din_no_pullu
p_pulldown.3140601807
Directory /workspace/12.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/12.gpio_smoke.772392061
Short name T209
Test name
Test status
Simulation time 123070211 ps
CPU time 0.75 seconds
Started Jun 30 04:23:24 PM PDT 24
Finished Jun 30 04:23:25 PM PDT 24
Peak memory 195724 kb
Host smart-c747c801-0b3b-4bdb-9461-85529a1ed855
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=772392061 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_smoke.772392061
Directory /workspace/12.gpio_smoke/latest

Test location /workspace/coverage/default/12.gpio_smoke_no_pullup_pulldown.2185684243
Short name T685
Test name
Test status
Simulation time 67801677 ps
CPU time 1.11 seconds
Started Jun 30 04:23:15 PM PDT 24
Finished Jun 30 04:23:17 PM PDT 24
Peak memory 196840 kb
Host smart-7e8c9254-8587-457c-9e2a-ace558296da1
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2185684243 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_smoke_no_pullup_pulldown.2185684243
Directory /workspace/12.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/12.gpio_stress_all.3909484301
Short name T306
Test name
Test status
Simulation time 15076603019 ps
CPU time 97.02 seconds
Started Jun 30 04:23:11 PM PDT 24
Finished Jun 30 04:24:49 PM PDT 24
Peak memory 198552 kb
Host smart-94102259-59db-40f1-b09f-3f9edbf2c7c6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3909484301 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.
gpio_stress_all.3909484301
Directory /workspace/12.gpio_stress_all/latest

Test location /workspace/coverage/default/13.gpio_alert_test.3331291934
Short name T387
Test name
Test status
Simulation time 12932496 ps
CPU time 0.59 seconds
Started Jun 30 04:23:21 PM PDT 24
Finished Jun 30 04:23:22 PM PDT 24
Peak memory 195136 kb
Host smart-07b1a4b7-e49c-4223-8bc0-a59f95146fe9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3331291934 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_alert_test.3331291934
Directory /workspace/13.gpio_alert_test/latest

Test location /workspace/coverage/default/13.gpio_dout_din_regs_random_rw.2142574608
Short name T327
Test name
Test status
Simulation time 23807867 ps
CPU time 0.69 seconds
Started Jun 30 04:23:16 PM PDT 24
Finished Jun 30 04:23:18 PM PDT 24
Peak memory 196420 kb
Host smart-10c42669-2e4a-40c3-ae8e-4ef105ddb65b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2142574608 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_dout_din_regs_random_rw.2142574608
Directory /workspace/13.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/13.gpio_filter_stress.3262704021
Short name T240
Test name
Test status
Simulation time 120460410 ps
CPU time 5.84 seconds
Started Jun 30 04:23:12 PM PDT 24
Finished Jun 30 04:23:24 PM PDT 24
Peak memory 198468 kb
Host smart-62775bef-1fde-4565-a67c-c465793e8b3a
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3262704021 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_filter_stre
ss.3262704021
Directory /workspace/13.gpio_filter_stress/latest

Test location /workspace/coverage/default/13.gpio_full_random.722872631
Short name T496
Test name
Test status
Simulation time 96201976 ps
CPU time 0.82 seconds
Started Jun 30 04:23:23 PM PDT 24
Finished Jun 30 04:23:24 PM PDT 24
Peak memory 197144 kb
Host smart-43b43ed5-d54f-4c07-9086-b9a3e7b820e5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=722872631 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_full_random.722872631
Directory /workspace/13.gpio_full_random/latest

Test location /workspace/coverage/default/13.gpio_intr_rand_pgm.368378283
Short name T506
Test name
Test status
Simulation time 1172156923 ps
CPU time 1.08 seconds
Started Jun 30 04:23:24 PM PDT 24
Finished Jun 30 04:23:26 PM PDT 24
Peak memory 197236 kb
Host smart-777ae6d6-d965-4e93-96f1-df3389307c13
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=368378283 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_intr_rand_pgm.368378283
Directory /workspace/13.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/13.gpio_intr_with_filter_rand_intr_event.3020368712
Short name T196
Test name
Test status
Simulation time 122935333 ps
CPU time 0.92 seconds
Started Jun 30 04:23:26 PM PDT 24
Finished Jun 30 04:23:28 PM PDT 24
Peak memory 196408 kb
Host smart-63b1a51a-f6c8-4429-aa68-202b26738702
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3020368712 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 13.gpio_intr_with_filter_rand_intr_event.3020368712
Directory /workspace/13.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/13.gpio_rand_intr_trigger.3163442720
Short name T429
Test name
Test status
Simulation time 79300010 ps
CPU time 1.53 seconds
Started Jun 30 04:23:14 PM PDT 24
Finished Jun 30 04:23:17 PM PDT 24
Peak memory 196308 kb
Host smart-85fcd931-7f6d-4512-9c4c-b5ed64422f48
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3163442720 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_rand_intr_trigger
.3163442720
Directory /workspace/13.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/13.gpio_random_dout_din.1532893525
Short name T175
Test name
Test status
Simulation time 48581903 ps
CPU time 1.08 seconds
Started Jun 30 04:23:09 PM PDT 24
Finished Jun 30 04:23:17 PM PDT 24
Peak memory 196532 kb
Host smart-668d4e19-6bb8-447f-b492-42b2ddbb3a6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1532893525 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_random_dout_din.1532893525
Directory /workspace/13.gpio_random_dout_din/latest

Test location /workspace/coverage/default/13.gpio_random_dout_din_no_pullup_pulldown.2588907814
Short name T583
Test name
Test status
Simulation time 31254939 ps
CPU time 1.05 seconds
Started Jun 30 04:23:23 PM PDT 24
Finished Jun 30 04:23:25 PM PDT 24
Peak memory 197652 kb
Host smart-fba4cfa3-a380-4ea9-9ff7-e5a30362747e
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2588907814 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_random_dout_din_no_pullu
p_pulldown.2588907814
Directory /workspace/13.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/13.gpio_random_long_reg_writes_reg_reads.2118775189
Short name T457
Test name
Test status
Simulation time 272746574 ps
CPU time 4.3 seconds
Started Jun 30 04:23:26 PM PDT 24
Finished Jun 30 04:23:31 PM PDT 24
Peak memory 198400 kb
Host smart-23d65896-1cbe-413d-a71a-99f733c0cf80
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2118775189 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_ra
ndom_long_reg_writes_reg_reads.2118775189
Directory /workspace/13.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/13.gpio_smoke.1722946688
Short name T551
Test name
Test status
Simulation time 227624198 ps
CPU time 1.32 seconds
Started Jun 30 04:23:24 PM PDT 24
Finished Jun 30 04:23:26 PM PDT 24
Peak memory 198464 kb
Host smart-3eb0a26d-9623-4b89-b95e-06acaf86b311
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1722946688 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_smoke.1722946688
Directory /workspace/13.gpio_smoke/latest

Test location /workspace/coverage/default/13.gpio_smoke_no_pullup_pulldown.777180661
Short name T566
Test name
Test status
Simulation time 38500701 ps
CPU time 1.01 seconds
Started Jun 30 04:23:32 PM PDT 24
Finished Jun 30 04:23:34 PM PDT 24
Peak memory 196392 kb
Host smart-c15af1f7-dfdc-461b-82ae-b4e0cc525f47
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=777180661 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_smoke_no_pullup_pulldown.777180661
Directory /workspace/13.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/13.gpio_stress_all.2592023943
Short name T333
Test name
Test status
Simulation time 24373150729 ps
CPU time 136.91 seconds
Started Jun 30 04:23:15 PM PDT 24
Finished Jun 30 04:25:34 PM PDT 24
Peak memory 198680 kb
Host smart-0b5e4f74-b095-4e92-8402-ab21d1a57362
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2592023943 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.
gpio_stress_all.2592023943
Directory /workspace/13.gpio_stress_all/latest

Test location /workspace/coverage/default/13.gpio_stress_all_with_rand_reset.504240186
Short name T593
Test name
Test status
Simulation time 331469934941 ps
CPU time 1649.22 seconds
Started Jun 30 04:23:16 PM PDT 24
Finished Jun 30 04:50:47 PM PDT 24
Peak memory 198788 kb
Host smart-d58891c6-92e1-497e-a150-096e7e55e29f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=504240186 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_stress_all_with_rand_reset.504240186
Directory /workspace/13.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.gpio_alert_test.1143797958
Short name T639
Test name
Test status
Simulation time 44116506 ps
CPU time 0.55 seconds
Started Jun 30 04:23:28 PM PDT 24
Finished Jun 30 04:23:30 PM PDT 24
Peak memory 195096 kb
Host smart-82a798f9-a5d6-42ec-be4b-b0f522b8cea4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1143797958 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_alert_test.1143797958
Directory /workspace/14.gpio_alert_test/latest

Test location /workspace/coverage/default/14.gpio_dout_din_regs_random_rw.3451590852
Short name T452
Test name
Test status
Simulation time 42019317 ps
CPU time 0.74 seconds
Started Jun 30 04:23:28 PM PDT 24
Finished Jun 30 04:23:30 PM PDT 24
Peak memory 195720 kb
Host smart-67d8d694-df8e-4452-8fe0-db657d15a753
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3451590852 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_dout_din_regs_random_rw.3451590852
Directory /workspace/14.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/14.gpio_filter_stress.1319112193
Short name T139
Test name
Test status
Simulation time 1435060972 ps
CPU time 13.52 seconds
Started Jun 30 04:23:28 PM PDT 24
Finished Jun 30 04:23:42 PM PDT 24
Peak memory 198452 kb
Host smart-627e34c0-e7b9-4051-af9b-79a05bfa6f22
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1319112193 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_filter_stre
ss.1319112193
Directory /workspace/14.gpio_filter_stress/latest

Test location /workspace/coverage/default/14.gpio_full_random.3144866517
Short name T552
Test name
Test status
Simulation time 48604469 ps
CPU time 0.87 seconds
Started Jun 30 04:23:45 PM PDT 24
Finished Jun 30 04:23:47 PM PDT 24
Peak memory 196392 kb
Host smart-6faafef1-b501-4a6a-9c49-f83634dabba0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3144866517 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_full_random.3144866517
Directory /workspace/14.gpio_full_random/latest

Test location /workspace/coverage/default/14.gpio_intr_rand_pgm.2100547577
Short name T278
Test name
Test status
Simulation time 98879421 ps
CPU time 1.24 seconds
Started Jun 30 04:23:23 PM PDT 24
Finished Jun 30 04:23:24 PM PDT 24
Peak memory 198580 kb
Host smart-cb78eb32-d069-4ba9-9dd4-7318776d6c7a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2100547577 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_intr_rand_pgm.2100547577
Directory /workspace/14.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/14.gpio_intr_with_filter_rand_intr_event.1346164859
Short name T172
Test name
Test status
Simulation time 45337397 ps
CPU time 1.64 seconds
Started Jun 30 04:23:30 PM PDT 24
Finished Jun 30 04:23:32 PM PDT 24
Peak memory 198532 kb
Host smart-0bdddf28-2e33-495b-910c-af8c4fcb9add
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1346164859 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 14.gpio_intr_with_filter_rand_intr_event.1346164859
Directory /workspace/14.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/14.gpio_rand_intr_trigger.2749281913
Short name T466
Test name
Test status
Simulation time 96616852 ps
CPU time 1.77 seconds
Started Jun 30 04:23:28 PM PDT 24
Finished Jun 30 04:23:31 PM PDT 24
Peak memory 196232 kb
Host smart-24ce68f6-7b08-41e1-bc5b-0744af78522a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2749281913 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_rand_intr_trigger
.2749281913
Directory /workspace/14.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/14.gpio_random_dout_din.550134222
Short name T650
Test name
Test status
Simulation time 96606697 ps
CPU time 0.96 seconds
Started Jun 30 04:23:21 PM PDT 24
Finished Jun 30 04:23:23 PM PDT 24
Peak memory 196468 kb
Host smart-b8972e05-6f6b-40d5-86a3-0b2f2b3665eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=550134222 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_random_dout_din.550134222
Directory /workspace/14.gpio_random_dout_din/latest

Test location /workspace/coverage/default/14.gpio_random_dout_din_no_pullup_pulldown.1948168266
Short name T546
Test name
Test status
Simulation time 214113757 ps
CPU time 1.26 seconds
Started Jun 30 04:23:24 PM PDT 24
Finished Jun 30 04:23:26 PM PDT 24
Peak memory 197420 kb
Host smart-3236ffe6-a08b-400c-a867-bb8cdcc38cdd
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1948168266 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_random_dout_din_no_pullu
p_pulldown.1948168266
Directory /workspace/14.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/14.gpio_random_long_reg_writes_reg_reads.3737602873
Short name T140
Test name
Test status
Simulation time 588887299 ps
CPU time 4.17 seconds
Started Jun 30 04:23:24 PM PDT 24
Finished Jun 30 04:23:29 PM PDT 24
Peak memory 198432 kb
Host smart-b6bd4f74-0fb5-4e4f-9827-a5037c865b90
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3737602873 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_ra
ndom_long_reg_writes_reg_reads.3737602873
Directory /workspace/14.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/14.gpio_smoke.1337004913
Short name T536
Test name
Test status
Simulation time 62912947 ps
CPU time 1.25 seconds
Started Jun 30 04:23:13 PM PDT 24
Finished Jun 30 04:23:15 PM PDT 24
Peak memory 197336 kb
Host smart-ec4a9fe9-0ec3-4bf3-bd90-d22c0eb29609
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1337004913 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_smoke.1337004913
Directory /workspace/14.gpio_smoke/latest

Test location /workspace/coverage/default/14.gpio_smoke_no_pullup_pulldown.807186781
Short name T199
Test name
Test status
Simulation time 44306656 ps
CPU time 1.05 seconds
Started Jun 30 04:23:37 PM PDT 24
Finished Jun 30 04:23:39 PM PDT 24
Peak memory 196284 kb
Host smart-bf71ee68-f58f-4bf0-acbc-21b1095a4ced
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=807186781 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_smoke_no_pullup_pulldown.807186781
Directory /workspace/14.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/14.gpio_stress_all.941266472
Short name T635
Test name
Test status
Simulation time 17070988101 ps
CPU time 42.46 seconds
Started Jun 30 04:23:29 PM PDT 24
Finished Jun 30 04:24:13 PM PDT 24
Peak memory 198544 kb
Host smart-1fbe984d-c012-4e62-89cd-89e9c189f477
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=941266472 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.g
pio_stress_all.941266472
Directory /workspace/14.gpio_stress_all/latest

Test location /workspace/coverage/default/14.gpio_stress_all_with_rand_reset.2721229153
Short name T55
Test name
Test status
Simulation time 492772204120 ps
CPU time 2348.96 seconds
Started Jun 30 04:23:37 PM PDT 24
Finished Jun 30 05:02:47 PM PDT 24
Peak memory 198748 kb
Host smart-7a011198-a52d-4f62-9cab-c4590afdb3ea
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2721229153 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_stress_all_with_rand_reset.2721229153
Directory /workspace/14.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.gpio_alert_test.4071293958
Short name T222
Test name
Test status
Simulation time 10774013 ps
CPU time 0.56 seconds
Started Jun 30 04:23:28 PM PDT 24
Finished Jun 30 04:23:29 PM PDT 24
Peak memory 194388 kb
Host smart-fd596ff2-b321-4f61-b879-83eb352b6d88
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4071293958 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_alert_test.4071293958
Directory /workspace/15.gpio_alert_test/latest

Test location /workspace/coverage/default/15.gpio_dout_din_regs_random_rw.1604862646
Short name T544
Test name
Test status
Simulation time 19839526 ps
CPU time 0.67 seconds
Started Jun 30 04:23:19 PM PDT 24
Finished Jun 30 04:23:24 PM PDT 24
Peak memory 195600 kb
Host smart-af6a961c-03d4-4697-a366-814efe4e95bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1604862646 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_dout_din_regs_random_rw.1604862646
Directory /workspace/15.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/15.gpio_filter_stress.1210197714
Short name T608
Test name
Test status
Simulation time 6858894053 ps
CPU time 20.92 seconds
Started Jun 30 04:23:25 PM PDT 24
Finished Jun 30 04:23:47 PM PDT 24
Peak memory 197380 kb
Host smart-36db0ebd-57d7-40d5-9d64-57d061722d62
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1210197714 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_filter_stre
ss.1210197714
Directory /workspace/15.gpio_filter_stress/latest

Test location /workspace/coverage/default/15.gpio_full_random.3918226232
Short name T498
Test name
Test status
Simulation time 67962494 ps
CPU time 0.78 seconds
Started Jun 30 04:23:28 PM PDT 24
Finished Jun 30 04:23:29 PM PDT 24
Peak memory 196376 kb
Host smart-1f64b8fd-0631-4851-b9e0-d060f13e3aa9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3918226232 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_full_random.3918226232
Directory /workspace/15.gpio_full_random/latest

Test location /workspace/coverage/default/15.gpio_intr_rand_pgm.552412167
Short name T359
Test name
Test status
Simulation time 55387271 ps
CPU time 0.66 seconds
Started Jun 30 04:23:38 PM PDT 24
Finished Jun 30 04:23:39 PM PDT 24
Peak memory 194728 kb
Host smart-6a53d378-21e2-441d-8f04-e573fe330849
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=552412167 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_intr_rand_pgm.552412167
Directory /workspace/15.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/15.gpio_intr_with_filter_rand_intr_event.4021119779
Short name T547
Test name
Test status
Simulation time 151272680 ps
CPU time 2.87 seconds
Started Jun 30 04:23:28 PM PDT 24
Finished Jun 30 04:23:31 PM PDT 24
Peak memory 198472 kb
Host smart-8941109b-3400-4da7-83b6-0c6240a499b6
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4021119779 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 15.gpio_intr_with_filter_rand_intr_event.4021119779
Directory /workspace/15.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/15.gpio_rand_intr_trigger.4094532284
Short name T127
Test name
Test status
Simulation time 70690416 ps
CPU time 1.19 seconds
Started Jun 30 04:23:26 PM PDT 24
Finished Jun 30 04:23:28 PM PDT 24
Peak memory 197228 kb
Host smart-e3e629eb-49a3-4089-9a59-b00e9af5f5c8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4094532284 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_rand_intr_trigger
.4094532284
Directory /workspace/15.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/15.gpio_random_dout_din.2565509922
Short name T570
Test name
Test status
Simulation time 464436517 ps
CPU time 0.95 seconds
Started Jun 30 04:23:24 PM PDT 24
Finished Jun 30 04:23:26 PM PDT 24
Peak memory 196296 kb
Host smart-495056e8-54df-4dbe-8957-bbf21fe6362f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2565509922 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_random_dout_din.2565509922
Directory /workspace/15.gpio_random_dout_din/latest

Test location /workspace/coverage/default/15.gpio_random_dout_din_no_pullup_pulldown.745299816
Short name T63
Test name
Test status
Simulation time 121756433 ps
CPU time 1.1 seconds
Started Jun 30 04:23:25 PM PDT 24
Finished Jun 30 04:23:27 PM PDT 24
Peak memory 197072 kb
Host smart-c3bcbcbe-2285-4a1e-8277-75b0c855e2d7
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=745299816 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_random_dout_din_no_pullup
_pulldown.745299816
Directory /workspace/15.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/15.gpio_random_long_reg_writes_reg_reads.2152823739
Short name T643
Test name
Test status
Simulation time 2102498483 ps
CPU time 5.1 seconds
Started Jun 30 04:23:34 PM PDT 24
Finished Jun 30 04:23:40 PM PDT 24
Peak memory 198496 kb
Host smart-b1ff9839-8d5b-425a-b1b1-5835f376dfed
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2152823739 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_ra
ndom_long_reg_writes_reg_reads.2152823739
Directory /workspace/15.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/15.gpio_smoke.1372799269
Short name T173
Test name
Test status
Simulation time 28425923 ps
CPU time 0.86 seconds
Started Jun 30 04:23:27 PM PDT 24
Finished Jun 30 04:23:28 PM PDT 24
Peak memory 196304 kb
Host smart-5e355119-4bb5-462a-a940-e93dc96ccc79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1372799269 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_smoke.1372799269
Directory /workspace/15.gpio_smoke/latest

Test location /workspace/coverage/default/15.gpio_smoke_no_pullup_pulldown.4018348138
Short name T381
Test name
Test status
Simulation time 49342693 ps
CPU time 1.28 seconds
Started Jun 30 04:23:17 PM PDT 24
Finished Jun 30 04:23:19 PM PDT 24
Peak memory 197184 kb
Host smart-73090514-3548-4eed-8f01-96954e029031
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4018348138 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_smoke_no_pullup_pulldown.4018348138
Directory /workspace/15.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/15.gpio_stress_all.559361412
Short name T364
Test name
Test status
Simulation time 12471922701 ps
CPU time 77.39 seconds
Started Jun 30 04:23:23 PM PDT 24
Finished Jun 30 04:24:41 PM PDT 24
Peak memory 198616 kb
Host smart-74c5fc64-b489-45d3-834b-c0f26f3c194e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=559361412 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.g
pio_stress_all.559361412
Directory /workspace/15.gpio_stress_all/latest

Test location /workspace/coverage/default/15.gpio_stress_all_with_rand_reset.1175771999
Short name T644
Test name
Test status
Simulation time 9190215794 ps
CPU time 143.27 seconds
Started Jun 30 04:23:17 PM PDT 24
Finished Jun 30 04:25:41 PM PDT 24
Peak memory 198680 kb
Host smart-ce5b5891-736e-493a-9aec-ae9fe83dd289
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1175771999 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_stress_all_with_rand_reset.1175771999
Directory /workspace/15.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.gpio_alert_test.2297976841
Short name T436
Test name
Test status
Simulation time 18463377 ps
CPU time 0.54 seconds
Started Jun 30 04:23:22 PM PDT 24
Finished Jun 30 04:23:23 PM PDT 24
Peak memory 194452 kb
Host smart-195387a0-f87d-43e3-83ff-ad21e2350ea7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2297976841 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_alert_test.2297976841
Directory /workspace/16.gpio_alert_test/latest

Test location /workspace/coverage/default/16.gpio_dout_din_regs_random_rw.3943558692
Short name T574
Test name
Test status
Simulation time 50472508 ps
CPU time 0.88 seconds
Started Jun 30 04:23:33 PM PDT 24
Finished Jun 30 04:23:35 PM PDT 24
Peak memory 196516 kb
Host smart-dc28bdfd-a48d-4fad-b640-887eb0674e95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3943558692 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_dout_din_regs_random_rw.3943558692
Directory /workspace/16.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/16.gpio_filter_stress.1531533826
Short name T610
Test name
Test status
Simulation time 1625194448 ps
CPU time 19.33 seconds
Started Jun 30 04:23:23 PM PDT 24
Finished Jun 30 04:23:43 PM PDT 24
Peak memory 197004 kb
Host smart-db881213-e423-4c4a-8d9a-59a0c6e78481
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1531533826 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_filter_stre
ss.1531533826
Directory /workspace/16.gpio_filter_stress/latest

Test location /workspace/coverage/default/16.gpio_full_random.1497254117
Short name T633
Test name
Test status
Simulation time 445684427 ps
CPU time 0.75 seconds
Started Jun 30 04:23:33 PM PDT 24
Finished Jun 30 04:23:35 PM PDT 24
Peak memory 196348 kb
Host smart-60456509-647a-4992-945a-0e30de9374b4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1497254117 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_full_random.1497254117
Directory /workspace/16.gpio_full_random/latest

Test location /workspace/coverage/default/16.gpio_intr_rand_pgm.4084975148
Short name T29
Test name
Test status
Simulation time 215221706 ps
CPU time 1.35 seconds
Started Jun 30 04:23:23 PM PDT 24
Finished Jun 30 04:23:24 PM PDT 24
Peak memory 197540 kb
Host smart-2d5f3aaf-b557-4e75-902e-27607f557fb9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4084975148 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_intr_rand_pgm.4084975148
Directory /workspace/16.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/16.gpio_intr_with_filter_rand_intr_event.1230651698
Short name T698
Test name
Test status
Simulation time 904646954 ps
CPU time 3.23 seconds
Started Jun 30 04:23:49 PM PDT 24
Finished Jun 30 04:23:54 PM PDT 24
Peak memory 198892 kb
Host smart-6609052e-700f-4477-92ef-f90322a21d82
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1230651698 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 16.gpio_intr_with_filter_rand_intr_event.1230651698
Directory /workspace/16.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/16.gpio_rand_intr_trigger.2069099644
Short name T289
Test name
Test status
Simulation time 1259191877 ps
CPU time 2.49 seconds
Started Jun 30 04:23:21 PM PDT 24
Finished Jun 30 04:23:24 PM PDT 24
Peak memory 197648 kb
Host smart-21e4802c-6c85-4072-90cf-c273d53d45e2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2069099644 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_rand_intr_trigger
.2069099644
Directory /workspace/16.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/16.gpio_random_dout_din.2054483886
Short name T641
Test name
Test status
Simulation time 111093077 ps
CPU time 1.21 seconds
Started Jun 30 04:23:26 PM PDT 24
Finished Jun 30 04:23:28 PM PDT 24
Peak memory 197476 kb
Host smart-b583b4ac-1d4c-40d0-88a1-fbc2e8822900
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2054483886 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_random_dout_din.2054483886
Directory /workspace/16.gpio_random_dout_din/latest

Test location /workspace/coverage/default/16.gpio_random_dout_din_no_pullup_pulldown.3251521879
Short name T65
Test name
Test status
Simulation time 44148833 ps
CPU time 0.66 seconds
Started Jun 30 04:23:26 PM PDT 24
Finished Jun 30 04:23:28 PM PDT 24
Peak memory 195456 kb
Host smart-f9ca82cd-c03c-4d8f-977c-988d92c77998
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3251521879 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_random_dout_din_no_pullu
p_pulldown.3251521879
Directory /workspace/16.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/16.gpio_random_long_reg_writes_reg_reads.1999812835
Short name T254
Test name
Test status
Simulation time 222655061 ps
CPU time 2.68 seconds
Started Jun 30 04:23:29 PM PDT 24
Finished Jun 30 04:23:32 PM PDT 24
Peak memory 198432 kb
Host smart-db3fd4e3-595a-4f96-980f-beb82b048b87
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1999812835 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_ra
ndom_long_reg_writes_reg_reads.1999812835
Directory /workspace/16.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/16.gpio_smoke.2978722763
Short name T54
Test name
Test status
Simulation time 259221099 ps
CPU time 1.17 seconds
Started Jun 30 04:23:53 PM PDT 24
Finished Jun 30 04:23:55 PM PDT 24
Peak memory 196356 kb
Host smart-1d394a3b-5c35-46aa-9eef-c9628378386f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2978722763 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_smoke.2978722763
Directory /workspace/16.gpio_smoke/latest

Test location /workspace/coverage/default/16.gpio_smoke_no_pullup_pulldown.4030812718
Short name T224
Test name
Test status
Simulation time 250693848 ps
CPU time 1.33 seconds
Started Jun 30 04:23:32 PM PDT 24
Finished Jun 30 04:23:34 PM PDT 24
Peak memory 197316 kb
Host smart-43f4bc7a-4e49-4f8c-91fc-81409be30f18
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4030812718 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_smoke_no_pullup_pulldown.4030812718
Directory /workspace/16.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/16.gpio_stress_all.3998599146
Short name T323
Test name
Test status
Simulation time 20194536109 ps
CPU time 127.02 seconds
Started Jun 30 04:23:32 PM PDT 24
Finished Jun 30 04:25:39 PM PDT 24
Peak memory 198556 kb
Host smart-dc6d52f6-0a80-4d2c-a3f0-0fe02b5aeb59
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3998599146 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.
gpio_stress_all.3998599146
Directory /workspace/16.gpio_stress_all/latest

Test location /workspace/coverage/default/17.gpio_alert_test.3296876197
Short name T217
Test name
Test status
Simulation time 36161984 ps
CPU time 0.62 seconds
Started Jun 30 04:23:28 PM PDT 24
Finished Jun 30 04:23:29 PM PDT 24
Peak memory 194596 kb
Host smart-c0b81fc5-2171-4e8e-8fca-48a67e3be898
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3296876197 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_alert_test.3296876197
Directory /workspace/17.gpio_alert_test/latest

Test location /workspace/coverage/default/17.gpio_dout_din_regs_random_rw.3675678372
Short name T687
Test name
Test status
Simulation time 80088949 ps
CPU time 0.62 seconds
Started Jun 30 04:23:33 PM PDT 24
Finished Jun 30 04:23:34 PM PDT 24
Peak memory 194488 kb
Host smart-03927fb9-2556-4a85-8289-3cddbf6307d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3675678372 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_dout_din_regs_random_rw.3675678372
Directory /workspace/17.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/17.gpio_filter_stress.2415249542
Short name T152
Test name
Test status
Simulation time 365037042 ps
CPU time 16.51 seconds
Started Jun 30 04:23:42 PM PDT 24
Finished Jun 30 04:24:04 PM PDT 24
Peak memory 196720 kb
Host smart-f96eb980-2411-46a7-a2d2-4064d9525f6d
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2415249542 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_filter_stre
ss.2415249542
Directory /workspace/17.gpio_filter_stress/latest

Test location /workspace/coverage/default/17.gpio_full_random.1753937009
Short name T134
Test name
Test status
Simulation time 35993262 ps
CPU time 0.62 seconds
Started Jun 30 04:23:43 PM PDT 24
Finished Jun 30 04:23:44 PM PDT 24
Peak memory 194912 kb
Host smart-11df6798-10e8-428c-836b-511cb78e727f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1753937009 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_full_random.1753937009
Directory /workspace/17.gpio_full_random/latest

Test location /workspace/coverage/default/17.gpio_intr_rand_pgm.492577916
Short name T368
Test name
Test status
Simulation time 93219450 ps
CPU time 0.88 seconds
Started Jun 30 04:23:21 PM PDT 24
Finished Jun 30 04:23:23 PM PDT 24
Peak memory 196156 kb
Host smart-4ebad83f-98b0-421c-af13-c5e8b6fd689a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=492577916 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_intr_rand_pgm.492577916
Directory /workspace/17.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/17.gpio_intr_with_filter_rand_intr_event.691221068
Short name T299
Test name
Test status
Simulation time 82422107 ps
CPU time 2.97 seconds
Started Jun 30 04:23:28 PM PDT 24
Finished Jun 30 04:23:31 PM PDT 24
Peak memory 198508 kb
Host smart-6998f60f-a643-416d-9af9-5cdf2a8f2420
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=691221068 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 17.gpio_intr_with_filter_rand_intr_event.691221068
Directory /workspace/17.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/17.gpio_rand_intr_trigger.98305862
Short name T612
Test name
Test status
Simulation time 55807802 ps
CPU time 1.71 seconds
Started Jun 30 04:23:29 PM PDT 24
Finished Jun 30 04:23:31 PM PDT 24
Peak memory 197040 kb
Host smart-a1e2e711-8dcd-4c4f-97e7-d22920794899
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98305862 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigger
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_rand_intr_trigger.98305862
Directory /workspace/17.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/17.gpio_random_dout_din.387197283
Short name T402
Test name
Test status
Simulation time 78423170 ps
CPU time 0.89 seconds
Started Jun 30 04:23:21 PM PDT 24
Finished Jun 30 04:23:22 PM PDT 24
Peak memory 196516 kb
Host smart-f2f713ba-3d93-4b3d-b373-278825980e0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=387197283 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_random_dout_din.387197283
Directory /workspace/17.gpio_random_dout_din/latest

Test location /workspace/coverage/default/17.gpio_random_dout_din_no_pullup_pulldown.2488583780
Short name T649
Test name
Test status
Simulation time 55303931 ps
CPU time 1.05 seconds
Started Jun 30 04:23:27 PM PDT 24
Finished Jun 30 04:23:29 PM PDT 24
Peak memory 196520 kb
Host smart-afb19e1d-779a-4690-813d-df479f7010c4
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2488583780 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_random_dout_din_no_pullu
p_pulldown.2488583780
Directory /workspace/17.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/17.gpio_random_long_reg_writes_reg_reads.1075645005
Short name T503
Test name
Test status
Simulation time 462662038 ps
CPU time 2.13 seconds
Started Jun 30 04:23:27 PM PDT 24
Finished Jun 30 04:23:30 PM PDT 24
Peak memory 198384 kb
Host smart-d36273bb-9314-4480-9a29-eec432926f96
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1075645005 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_ra
ndom_long_reg_writes_reg_reads.1075645005
Directory /workspace/17.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/17.gpio_smoke.2765723245
Short name T272
Test name
Test status
Simulation time 174739515 ps
CPU time 1.23 seconds
Started Jun 30 04:23:29 PM PDT 24
Finished Jun 30 04:23:31 PM PDT 24
Peak memory 197292 kb
Host smart-2d9ec8b3-96fe-41e1-b294-a60d44d633e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2765723245 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_smoke.2765723245
Directory /workspace/17.gpio_smoke/latest

Test location /workspace/coverage/default/17.gpio_smoke_no_pullup_pulldown.3984526366
Short name T677
Test name
Test status
Simulation time 40888626 ps
CPU time 1.21 seconds
Started Jun 30 04:24:01 PM PDT 24
Finished Jun 30 04:24:05 PM PDT 24
Peak memory 195916 kb
Host smart-b93191fe-9c14-4ace-af5a-35f291fb0418
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3984526366 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_smoke_no_pullup_pulldown.3984526366
Directory /workspace/17.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/17.gpio_stress_all.2014954873
Short name T622
Test name
Test status
Simulation time 23551965240 ps
CPU time 145.54 seconds
Started Jun 30 04:23:26 PM PDT 24
Finished Jun 30 04:25:52 PM PDT 24
Peak memory 198512 kb
Host smart-1294b23b-f2e5-4354-a394-1cec78f3d3a3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2014954873 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.
gpio_stress_all.2014954873
Directory /workspace/17.gpio_stress_all/latest

Test location /workspace/coverage/default/18.gpio_alert_test.4172306159
Short name T594
Test name
Test status
Simulation time 245121764 ps
CPU time 0.56 seconds
Started Jun 30 04:23:32 PM PDT 24
Finished Jun 30 04:23:33 PM PDT 24
Peak memory 194612 kb
Host smart-bedb38ad-b96e-4c60-8c1c-5226cb6c3e44
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4172306159 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_alert_test.4172306159
Directory /workspace/18.gpio_alert_test/latest

Test location /workspace/coverage/default/18.gpio_dout_din_regs_random_rw.4046449448
Short name T587
Test name
Test status
Simulation time 36380488 ps
CPU time 0.62 seconds
Started Jun 30 04:23:33 PM PDT 24
Finished Jun 30 04:23:35 PM PDT 24
Peak memory 195224 kb
Host smart-bf543d85-de33-4ae0-afba-f2fade993ba2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4046449448 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_dout_din_regs_random_rw.4046449448
Directory /workspace/18.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/18.gpio_filter_stress.1927714874
Short name T603
Test name
Test status
Simulation time 1648402798 ps
CPU time 22.62 seconds
Started Jun 30 04:23:32 PM PDT 24
Finished Jun 30 04:23:56 PM PDT 24
Peak memory 196732 kb
Host smart-15b7eab2-5d26-46f8-b580-b11163929f37
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1927714874 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_filter_stre
ss.1927714874
Directory /workspace/18.gpio_filter_stress/latest

Test location /workspace/coverage/default/18.gpio_full_random.2620976444
Short name T689
Test name
Test status
Simulation time 66863923 ps
CPU time 0.92 seconds
Started Jun 30 04:23:48 PM PDT 24
Finished Jun 30 04:23:50 PM PDT 24
Peak memory 196920 kb
Host smart-abde08e0-97a6-4d08-b154-db15c5cf9009
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2620976444 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_full_random.2620976444
Directory /workspace/18.gpio_full_random/latest

Test location /workspace/coverage/default/18.gpio_intr_rand_pgm.2347540464
Short name T180
Test name
Test status
Simulation time 92043612 ps
CPU time 0.85 seconds
Started Jun 30 04:23:36 PM PDT 24
Finished Jun 30 04:23:38 PM PDT 24
Peak memory 196528 kb
Host smart-449433f8-f137-47d8-88c2-b66fbc2a8d3e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2347540464 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_intr_rand_pgm.2347540464
Directory /workspace/18.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/18.gpio_intr_with_filter_rand_intr_event.3187787001
Short name T131
Test name
Test status
Simulation time 92813654 ps
CPU time 1.01 seconds
Started Jun 30 04:23:31 PM PDT 24
Finished Jun 30 04:23:33 PM PDT 24
Peak memory 197496 kb
Host smart-cb9abb52-00c0-4abd-b947-393a17b3a80e
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3187787001 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 18.gpio_intr_with_filter_rand_intr_event.3187787001
Directory /workspace/18.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/18.gpio_rand_intr_trigger.67765069
Short name T147
Test name
Test status
Simulation time 159653334 ps
CPU time 1.62 seconds
Started Jun 30 04:23:26 PM PDT 24
Finished Jun 30 04:23:29 PM PDT 24
Peak memory 196584 kb
Host smart-469068bd-0dcf-4794-9315-0e8c557e2770
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67765069 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigger
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_rand_intr_trigger.67765069
Directory /workspace/18.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/18.gpio_random_dout_din.1310791576
Short name T376
Test name
Test status
Simulation time 154336204 ps
CPU time 0.94 seconds
Started Jun 30 04:23:34 PM PDT 24
Finished Jun 30 04:23:36 PM PDT 24
Peak memory 197192 kb
Host smart-f0a0f0a4-d375-45f4-b1d9-4e07b3a657a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1310791576 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_random_dout_din.1310791576
Directory /workspace/18.gpio_random_dout_din/latest

Test location /workspace/coverage/default/18.gpio_random_dout_din_no_pullup_pulldown.2944188142
Short name T678
Test name
Test status
Simulation time 128601293 ps
CPU time 1.14 seconds
Started Jun 30 04:23:44 PM PDT 24
Finished Jun 30 04:23:45 PM PDT 24
Peak memory 197128 kb
Host smart-6ad11a65-af1e-4f39-858a-42b41ff0b5e4
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2944188142 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_random_dout_din_no_pullu
p_pulldown.2944188142
Directory /workspace/18.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/18.gpio_random_long_reg_writes_reg_reads.4097301977
Short name T115
Test name
Test status
Simulation time 1294185169 ps
CPU time 4.93 seconds
Started Jun 30 04:23:33 PM PDT 24
Finished Jun 30 04:23:39 PM PDT 24
Peak memory 198348 kb
Host smart-09614715-0825-4507-bd7f-d8edf63195bb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4097301977 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_ra
ndom_long_reg_writes_reg_reads.4097301977
Directory /workspace/18.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/18.gpio_smoke.976272159
Short name T463
Test name
Test status
Simulation time 593286157 ps
CPU time 0.9 seconds
Started Jun 30 04:23:28 PM PDT 24
Finished Jun 30 04:23:30 PM PDT 24
Peak memory 196864 kb
Host smart-aef261cd-473c-4e5f-99c7-17fd75f99000
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=976272159 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_smoke.976272159
Directory /workspace/18.gpio_smoke/latest

Test location /workspace/coverage/default/18.gpio_smoke_no_pullup_pulldown.3029428282
Short name T150
Test name
Test status
Simulation time 82594776 ps
CPU time 1.14 seconds
Started Jun 30 04:23:39 PM PDT 24
Finished Jun 30 04:23:41 PM PDT 24
Peak memory 197120 kb
Host smart-948278bd-2059-4d3b-9139-066166a1f1b8
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3029428282 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_smoke_no_pullup_pulldown.3029428282
Directory /workspace/18.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/18.gpio_stress_all.1454395903
Short name T497
Test name
Test status
Simulation time 14255033289 ps
CPU time 66.61 seconds
Started Jun 30 04:23:57 PM PDT 24
Finished Jun 30 04:25:05 PM PDT 24
Peak memory 198580 kb
Host smart-fc775872-25c7-4cb8-8a1b-c0a62e3caa37
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1454395903 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.
gpio_stress_all.1454395903
Directory /workspace/18.gpio_stress_all/latest

Test location /workspace/coverage/default/19.gpio_alert_test.1987918524
Short name T207
Test name
Test status
Simulation time 76252049 ps
CPU time 0.56 seconds
Started Jun 30 04:23:24 PM PDT 24
Finished Jun 30 04:23:25 PM PDT 24
Peak memory 194464 kb
Host smart-a4ef7c77-043d-4130-ab4b-b7243786c260
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1987918524 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_alert_test.1987918524
Directory /workspace/19.gpio_alert_test/latest

Test location /workspace/coverage/default/19.gpio_dout_din_regs_random_rw.2252049355
Short name T623
Test name
Test status
Simulation time 31002799 ps
CPU time 0.83 seconds
Started Jun 30 04:23:56 PM PDT 24
Finished Jun 30 04:23:58 PM PDT 24
Peak memory 197736 kb
Host smart-e19cf7f1-07b3-4583-a7bf-08c429d36746
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2252049355 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_dout_din_regs_random_rw.2252049355
Directory /workspace/19.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/19.gpio_filter_stress.1767680643
Short name T707
Test name
Test status
Simulation time 1119535825 ps
CPU time 13.74 seconds
Started Jun 30 04:23:28 PM PDT 24
Finished Jun 30 04:23:42 PM PDT 24
Peak memory 198424 kb
Host smart-1592347c-4810-4d08-a116-c24c3442f925
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1767680643 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_filter_stre
ss.1767680643
Directory /workspace/19.gpio_filter_stress/latest

Test location /workspace/coverage/default/19.gpio_full_random.2382963988
Short name T300
Test name
Test status
Simulation time 83478182 ps
CPU time 0.99 seconds
Started Jun 30 04:23:34 PM PDT 24
Finished Jun 30 04:23:36 PM PDT 24
Peak memory 198328 kb
Host smart-5b29fcc2-fe62-41bb-adce-8bcd868fa54c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2382963988 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_full_random.2382963988
Directory /workspace/19.gpio_full_random/latest

Test location /workspace/coverage/default/19.gpio_intr_rand_pgm.1573156403
Short name T662
Test name
Test status
Simulation time 22869589 ps
CPU time 0.66 seconds
Started Jun 30 04:23:25 PM PDT 24
Finished Jun 30 04:23:27 PM PDT 24
Peak memory 194704 kb
Host smart-3c0fccbf-70a2-4552-b200-41001dc9ec5a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1573156403 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_intr_rand_pgm.1573156403
Directory /workspace/19.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/19.gpio_intr_with_filter_rand_intr_event.2951854805
Short name T631
Test name
Test status
Simulation time 166498176 ps
CPU time 3.26 seconds
Started Jun 30 04:23:55 PM PDT 24
Finished Jun 30 04:24:00 PM PDT 24
Peak memory 198224 kb
Host smart-d018b597-8b85-4d98-bc55-24ec3466be3c
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2951854805 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 19.gpio_intr_with_filter_rand_intr_event.2951854805
Directory /workspace/19.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/19.gpio_rand_intr_trigger.3912853187
Short name T67
Test name
Test status
Simulation time 108641012 ps
CPU time 3.06 seconds
Started Jun 30 04:23:29 PM PDT 24
Finished Jun 30 04:23:33 PM PDT 24
Peak memory 196304 kb
Host smart-14217ec8-2eaf-4309-a3b7-811a4eb0cb2f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3912853187 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_rand_intr_trigger
.3912853187
Directory /workspace/19.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/19.gpio_random_dout_din.1999938678
Short name T673
Test name
Test status
Simulation time 23901876 ps
CPU time 0.88 seconds
Started Jun 30 04:23:25 PM PDT 24
Finished Jun 30 04:23:26 PM PDT 24
Peak memory 196512 kb
Host smart-2b0cd6f3-62be-442d-8a3e-787ea7bb1aae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1999938678 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_random_dout_din.1999938678
Directory /workspace/19.gpio_random_dout_din/latest

Test location /workspace/coverage/default/19.gpio_random_dout_din_no_pullup_pulldown.2627134163
Short name T598
Test name
Test status
Simulation time 118231574 ps
CPU time 1.11 seconds
Started Jun 30 04:23:38 PM PDT 24
Finished Jun 30 04:23:45 PM PDT 24
Peak memory 196572 kb
Host smart-aad7a095-5dc8-427d-95f0-6132c77f5b98
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2627134163 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_random_dout_din_no_pullu
p_pulldown.2627134163
Directory /workspace/19.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/19.gpio_random_long_reg_writes_reg_reads.1987049847
Short name T462
Test name
Test status
Simulation time 968981731 ps
CPU time 5.21 seconds
Started Jun 30 04:23:31 PM PDT 24
Finished Jun 30 04:23:36 PM PDT 24
Peak memory 198508 kb
Host smart-483b6600-6f23-4973-aef2-a920c9c3a0cc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1987049847 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_ra
ndom_long_reg_writes_reg_reads.1987049847
Directory /workspace/19.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/19.gpio_smoke.2506609463
Short name T373
Test name
Test status
Simulation time 180174958 ps
CPU time 1.1 seconds
Started Jun 30 04:23:48 PM PDT 24
Finished Jun 30 04:23:51 PM PDT 24
Peak memory 196368 kb
Host smart-0a6f9e8e-eeef-4861-8e08-76c13676b32f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2506609463 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_smoke.2506609463
Directory /workspace/19.gpio_smoke/latest

Test location /workspace/coverage/default/19.gpio_smoke_no_pullup_pulldown.1026644382
Short name T489
Test name
Test status
Simulation time 33184021 ps
CPU time 0.94 seconds
Started Jun 30 04:23:44 PM PDT 24
Finished Jun 30 04:23:45 PM PDT 24
Peak memory 196172 kb
Host smart-0de6e535-e30e-45e5-a2e0-bad549621389
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1026644382 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_smoke_no_pullup_pulldown.1026644382
Directory /workspace/19.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/19.gpio_stress_all.2284245943
Short name T237
Test name
Test status
Simulation time 3545642624 ps
CPU time 86.69 seconds
Started Jun 30 04:23:48 PM PDT 24
Finished Jun 30 04:25:16 PM PDT 24
Peak memory 198592 kb
Host smart-bb5c1b32-7dac-44d3-8637-f4d8c5f5db99
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2284245943 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.
gpio_stress_all.2284245943
Directory /workspace/19.gpio_stress_all/latest

Test location /workspace/coverage/default/2.gpio_alert_test.1776591300
Short name T210
Test name
Test status
Simulation time 169319473 ps
CPU time 0.55 seconds
Started Jun 30 04:22:42 PM PDT 24
Finished Jun 30 04:22:46 PM PDT 24
Peak memory 194248 kb
Host smart-b9c824e5-294e-4006-b1e9-54a3ef925581
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1776591300 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_alert_test.1776591300
Directory /workspace/2.gpio_alert_test/latest

Test location /workspace/coverage/default/2.gpio_dout_din_regs_random_rw.39166895
Short name T529
Test name
Test status
Simulation time 30194503 ps
CPU time 0.74 seconds
Started Jun 30 04:22:39 PM PDT 24
Finished Jun 30 04:22:42 PM PDT 24
Peak memory 195432 kb
Host smart-63763932-41e9-4304-8bd3-6c4f1bb1fa09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=39166895 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_dout_din_regs_random_rw.39166895
Directory /workspace/2.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/2.gpio_filter_stress.3200567809
Short name T331
Test name
Test status
Simulation time 978538343 ps
CPU time 8.21 seconds
Started Jun 30 04:18:54 PM PDT 24
Finished Jun 30 04:19:03 PM PDT 24
Peak memory 196444 kb
Host smart-c0c2a3af-45fb-46d7-98f5-a23d7a2b312d
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3200567809 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_filter_stres
s.3200567809
Directory /workspace/2.gpio_filter_stress/latest

Test location /workspace/coverage/default/2.gpio_full_random.1440593013
Short name T454
Test name
Test status
Simulation time 64016383 ps
CPU time 0.63 seconds
Started Jun 30 04:18:13 PM PDT 24
Finished Jun 30 04:18:14 PM PDT 24
Peak memory 194804 kb
Host smart-2ce5cdd9-af8d-4621-80f9-1d74c98eb569
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1440593013 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_full_random.1440593013
Directory /workspace/2.gpio_full_random/latest

Test location /workspace/coverage/default/2.gpio_intr_rand_pgm.607630107
Short name T370
Test name
Test status
Simulation time 49568724 ps
CPU time 1.28 seconds
Started Jun 30 04:22:07 PM PDT 24
Finished Jun 30 04:22:10 PM PDT 24
Peak memory 197628 kb
Host smart-9ded159d-d65b-4085-8310-b2cf870dbf2f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=607630107 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_intr_rand_pgm.607630107
Directory /workspace/2.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/2.gpio_intr_with_filter_rand_intr_event.558708258
Short name T268
Test name
Test status
Simulation time 29041590 ps
CPU time 1.22 seconds
Started Jun 30 04:21:53 PM PDT 24
Finished Jun 30 04:21:56 PM PDT 24
Peak memory 196936 kb
Host smart-55f616e3-de1a-4d9c-98a0-33a3fb3971df
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=558708258 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 2.gpio_intr_with_filter_rand_intr_event.558708258
Directory /workspace/2.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/2.gpio_rand_intr_trigger.3638596990
Short name T611
Test name
Test status
Simulation time 385832202 ps
CPU time 2.37 seconds
Started Jun 30 04:21:53 PM PDT 24
Finished Jun 30 04:21:57 PM PDT 24
Peak memory 197404 kb
Host smart-6e9c07a1-92d4-4e87-a272-d1e72752cb49
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3638596990 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_rand_intr_trigger.
3638596990
Directory /workspace/2.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/2.gpio_random_dout_din.3083292269
Short name T684
Test name
Test status
Simulation time 47314192 ps
CPU time 0.87 seconds
Started Jun 30 04:23:05 PM PDT 24
Finished Jun 30 04:23:06 PM PDT 24
Peak memory 196320 kb
Host smart-bcf86fce-fed5-43d8-8aac-640fc4500567
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3083292269 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_random_dout_din.3083292269
Directory /workspace/2.gpio_random_dout_din/latest

Test location /workspace/coverage/default/2.gpio_random_dout_din_no_pullup_pulldown.2727416475
Short name T262
Test name
Test status
Simulation time 178002496 ps
CPU time 0.95 seconds
Started Jun 30 04:20:43 PM PDT 24
Finished Jun 30 04:20:44 PM PDT 24
Peak memory 197232 kb
Host smart-d949abb1-d299-4a4e-836d-a85c5f3e8269
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2727416475 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_random_dout_din_no_pullup
_pulldown.2727416475
Directory /workspace/2.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/2.gpio_random_long_reg_writes_reg_reads.2532453279
Short name T605
Test name
Test status
Simulation time 114273695 ps
CPU time 1.11 seconds
Started Jun 30 04:22:01 PM PDT 24
Finished Jun 30 04:22:03 PM PDT 24
Peak memory 196656 kb
Host smart-f567d8f4-eba7-4740-8288-b88536ca0cbb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2532453279 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_ran
dom_long_reg_writes_reg_reads.2532453279
Directory /workspace/2.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/2.gpio_sec_cm.4170992023
Short name T40
Test name
Test status
Simulation time 627733427 ps
CPU time 0.99 seconds
Started Jun 30 04:22:44 PM PDT 24
Finished Jun 30 04:22:48 PM PDT 24
Peak memory 214700 kb
Host smart-6c0d35b9-755b-41f6-a717-453bae4945e5
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4170992023 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_sec_cm.4170992023
Directory /workspace/2.gpio_sec_cm/latest

Test location /workspace/coverage/default/2.gpio_smoke.3594446083
Short name T481
Test name
Test status
Simulation time 104814732 ps
CPU time 1.33 seconds
Started Jun 30 04:20:24 PM PDT 24
Finished Jun 30 04:20:25 PM PDT 24
Peak memory 196768 kb
Host smart-169d4874-abec-4158-b450-7bfc1f11b781
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3594446083 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_smoke.3594446083
Directory /workspace/2.gpio_smoke/latest

Test location /workspace/coverage/default/2.gpio_smoke_no_pullup_pulldown.193142267
Short name T253
Test name
Test status
Simulation time 86035111 ps
CPU time 1.15 seconds
Started Jun 30 04:22:52 PM PDT 24
Finished Jun 30 04:22:55 PM PDT 24
Peak memory 197200 kb
Host smart-9e48efaa-3b7a-4e72-b9d6-f9fe52597deb
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=193142267 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_smoke_no_pullup_pulldown.193142267
Directory /workspace/2.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/2.gpio_stress_all.1817691406
Short name T591
Test name
Test status
Simulation time 2778422428 ps
CPU time 27.36 seconds
Started Jun 30 04:22:42 PM PDT 24
Finished Jun 30 04:23:14 PM PDT 24
Peak memory 198444 kb
Host smart-66628b84-6dff-4b64-8234-398a09716c6b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1817691406 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.g
pio_stress_all.1817691406
Directory /workspace/2.gpio_stress_all/latest

Test location /workspace/coverage/default/20.gpio_dout_din_regs_random_rw.885695827
Short name T412
Test name
Test status
Simulation time 31189260 ps
CPU time 0.87 seconds
Started Jun 30 04:23:39 PM PDT 24
Finished Jun 30 04:23:41 PM PDT 24
Peak memory 196408 kb
Host smart-f0e1f869-0cf5-4742-8581-8c980e5f71b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=885695827 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_dout_din_regs_random_rw.885695827
Directory /workspace/20.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/20.gpio_filter_stress.4227326219
Short name T216
Test name
Test status
Simulation time 914935110 ps
CPU time 15.33 seconds
Started Jun 30 04:23:55 PM PDT 24
Finished Jun 30 04:24:12 PM PDT 24
Peak memory 197480 kb
Host smart-58083dfd-e44f-4c71-a243-9493832931b6
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4227326219 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_filter_stre
ss.4227326219
Directory /workspace/20.gpio_filter_stress/latest

Test location /workspace/coverage/default/20.gpio_full_random.3304790430
Short name T349
Test name
Test status
Simulation time 204815018 ps
CPU time 0.83 seconds
Started Jun 30 04:23:44 PM PDT 24
Finished Jun 30 04:23:45 PM PDT 24
Peak memory 197408 kb
Host smart-8fa50c1d-56b3-414c-b575-ebed7fee157e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3304790430 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_full_random.3304790430
Directory /workspace/20.gpio_full_random/latest

Test location /workspace/coverage/default/20.gpio_intr_rand_pgm.3881512119
Short name T295
Test name
Test status
Simulation time 94972996 ps
CPU time 0.72 seconds
Started Jun 30 04:23:57 PM PDT 24
Finished Jun 30 04:23:59 PM PDT 24
Peak memory 195604 kb
Host smart-2646b6dc-1e47-42ce-bb7d-106516e1ffd5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3881512119 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_intr_rand_pgm.3881512119
Directory /workspace/20.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/20.gpio_intr_with_filter_rand_intr_event.2303585661
Short name T61
Test name
Test status
Simulation time 33886538 ps
CPU time 0.88 seconds
Started Jun 30 04:23:28 PM PDT 24
Finished Jun 30 04:23:30 PM PDT 24
Peak memory 196540 kb
Host smart-f8b06085-581a-4b1c-9881-a1dfe9f43ae9
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2303585661 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 20.gpio_intr_with_filter_rand_intr_event.2303585661
Directory /workspace/20.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/20.gpio_rand_intr_trigger.4070704747
Short name T408
Test name
Test status
Simulation time 155056970 ps
CPU time 2.79 seconds
Started Jun 30 04:23:33 PM PDT 24
Finished Jun 30 04:23:37 PM PDT 24
Peak memory 197444 kb
Host smart-959441e3-4590-42a9-b771-89ce528d2d5a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4070704747 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_rand_intr_trigger
.4070704747
Directory /workspace/20.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/20.gpio_random_dout_din.2687967022
Short name T401
Test name
Test status
Simulation time 54709801 ps
CPU time 1.11 seconds
Started Jun 30 04:23:42 PM PDT 24
Finished Jun 30 04:23:44 PM PDT 24
Peak memory 197240 kb
Host smart-91d44cbc-6b78-43cf-ba5a-cb9a29254464
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2687967022 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_random_dout_din.2687967022
Directory /workspace/20.gpio_random_dout_din/latest

Test location /workspace/coverage/default/20.gpio_random_dout_din_no_pullup_pulldown.2354539301
Short name T579
Test name
Test status
Simulation time 32908565 ps
CPU time 1.08 seconds
Started Jun 30 04:23:33 PM PDT 24
Finished Jun 30 04:23:34 PM PDT 24
Peak memory 197020 kb
Host smart-477c423f-5e82-4e16-b0d0-d2af69c49f0e
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2354539301 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_random_dout_din_no_pullu
p_pulldown.2354539301
Directory /workspace/20.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/20.gpio_random_long_reg_writes_reg_reads.3164228164
Short name T281
Test name
Test status
Simulation time 4579429431 ps
CPU time 5.13 seconds
Started Jun 30 04:23:39 PM PDT 24
Finished Jun 30 04:23:45 PM PDT 24
Peak memory 198468 kb
Host smart-d64f4455-fb31-463b-bbb7-468a521f76dd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3164228164 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_ra
ndom_long_reg_writes_reg_reads.3164228164
Directory /workspace/20.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/20.gpio_smoke.852225638
Short name T383
Test name
Test status
Simulation time 19573726 ps
CPU time 0.71 seconds
Started Jun 30 04:23:32 PM PDT 24
Finished Jun 30 04:23:39 PM PDT 24
Peak memory 196412 kb
Host smart-a4bd63d8-6c28-450a-8e2d-af59aae09ebc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=852225638 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_smoke.852225638
Directory /workspace/20.gpio_smoke/latest

Test location /workspace/coverage/default/20.gpio_smoke_no_pullup_pulldown.338018407
Short name T307
Test name
Test status
Simulation time 30404170 ps
CPU time 0.9 seconds
Started Jun 30 04:23:32 PM PDT 24
Finished Jun 30 04:23:34 PM PDT 24
Peak memory 196184 kb
Host smart-e0245373-4c8b-4941-a369-76dcff7323f0
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=338018407 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_smoke_no_pullup_pulldown.338018407
Directory /workspace/20.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/20.gpio_stress_all.102134869
Short name T156
Test name
Test status
Simulation time 13717724867 ps
CPU time 179.65 seconds
Started Jun 30 04:23:35 PM PDT 24
Finished Jun 30 04:26:36 PM PDT 24
Peak memory 198588 kb
Host smart-8add8a34-4310-4c5f-aa16-514760be9afe
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=102134869 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.g
pio_stress_all.102134869
Directory /workspace/20.gpio_stress_all/latest

Test location /workspace/coverage/default/21.gpio_alert_test.8520806
Short name T464
Test name
Test status
Simulation time 29904059 ps
CPU time 0.57 seconds
Started Jun 30 04:24:05 PM PDT 24
Finished Jun 30 04:24:09 PM PDT 24
Peak memory 195584 kb
Host smart-d6ca02b4-6fe4-4c29-a93a-4f2238d34825
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=8520806 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_alert_test.8520806
Directory /workspace/21.gpio_alert_test/latest

Test location /workspace/coverage/default/21.gpio_dout_din_regs_random_rw.499513294
Short name T423
Test name
Test status
Simulation time 22858323 ps
CPU time 0.77 seconds
Started Jun 30 04:23:51 PM PDT 24
Finished Jun 30 04:23:52 PM PDT 24
Peak memory 195956 kb
Host smart-a6d823dc-7ffc-4f56-8e22-c75e707afbd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=499513294 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_dout_din_regs_random_rw.499513294
Directory /workspace/21.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/21.gpio_filter_stress.3453389659
Short name T288
Test name
Test status
Simulation time 332535769 ps
CPU time 5.4 seconds
Started Jun 30 04:23:49 PM PDT 24
Finished Jun 30 04:23:56 PM PDT 24
Peak memory 197440 kb
Host smart-0cc66969-db5a-4e5a-a68f-91b5c24a5009
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3453389659 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_filter_stre
ss.3453389659
Directory /workspace/21.gpio_filter_stress/latest

Test location /workspace/coverage/default/21.gpio_full_random.2211148378
Short name T366
Test name
Test status
Simulation time 33624669 ps
CPU time 0.76 seconds
Started Jun 30 04:23:38 PM PDT 24
Finished Jun 30 04:23:39 PM PDT 24
Peak memory 196288 kb
Host smart-b2b4d279-0984-45f2-8b65-35d350a94bee
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2211148378 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_full_random.2211148378
Directory /workspace/21.gpio_full_random/latest

Test location /workspace/coverage/default/21.gpio_intr_rand_pgm.3779010074
Short name T275
Test name
Test status
Simulation time 127448644 ps
CPU time 0.76 seconds
Started Jun 30 04:23:48 PM PDT 24
Finished Jun 30 04:23:51 PM PDT 24
Peak memory 196040 kb
Host smart-2f5d568b-0d33-468f-b069-fedd31b4b238
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3779010074 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_intr_rand_pgm.3779010074
Directory /workspace/21.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/21.gpio_intr_with_filter_rand_intr_event.4028532612
Short name T241
Test name
Test status
Simulation time 48900111 ps
CPU time 1.13 seconds
Started Jun 30 04:23:30 PM PDT 24
Finished Jun 30 04:23:32 PM PDT 24
Peak memory 197912 kb
Host smart-e3df1650-e1bc-403f-8bff-694b137cd855
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4028532612 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 21.gpio_intr_with_filter_rand_intr_event.4028532612
Directory /workspace/21.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/21.gpio_rand_intr_trigger.3640859799
Short name T562
Test name
Test status
Simulation time 353965508 ps
CPU time 2.55 seconds
Started Jun 30 04:23:35 PM PDT 24
Finished Jun 30 04:23:38 PM PDT 24
Peak memory 198488 kb
Host smart-5ed9f27e-e630-4e7f-b33b-c6906d2dd287
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3640859799 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_rand_intr_trigger
.3640859799
Directory /workspace/21.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/21.gpio_random_dout_din.669938258
Short name T405
Test name
Test status
Simulation time 25637155 ps
CPU time 0.97 seconds
Started Jun 30 04:23:45 PM PDT 24
Finished Jun 30 04:23:46 PM PDT 24
Peak memory 196284 kb
Host smart-3fe55bfd-b9e5-4a32-bf70-b6deaea385b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=669938258 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_random_dout_din.669938258
Directory /workspace/21.gpio_random_dout_din/latest

Test location /workspace/coverage/default/21.gpio_random_dout_din_no_pullup_pulldown.1362791709
Short name T599
Test name
Test status
Simulation time 106227402 ps
CPU time 1.08 seconds
Started Jun 30 04:23:55 PM PDT 24
Finished Jun 30 04:23:57 PM PDT 24
Peak memory 197560 kb
Host smart-5e626be8-fa91-44c7-b34a-eaf53c798ebb
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1362791709 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_random_dout_din_no_pullu
p_pulldown.1362791709
Directory /workspace/21.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/21.gpio_random_long_reg_writes_reg_reads.2796523100
Short name T337
Test name
Test status
Simulation time 443642900 ps
CPU time 4.8 seconds
Started Jun 30 04:23:30 PM PDT 24
Finished Jun 30 04:23:35 PM PDT 24
Peak memory 198388 kb
Host smart-770cb3cd-aa0e-4340-8842-ccc6276f42df
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2796523100 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_ra
ndom_long_reg_writes_reg_reads.2796523100
Directory /workspace/21.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/21.gpio_smoke.1241000898
Short name T160
Test name
Test status
Simulation time 173402450 ps
CPU time 0.98 seconds
Started Jun 30 04:23:44 PM PDT 24
Finished Jun 30 04:23:45 PM PDT 24
Peak memory 196048 kb
Host smart-3d00f022-2833-46e6-b55c-552f7355a123
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1241000898 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_smoke.1241000898
Directory /workspace/21.gpio_smoke/latest

Test location /workspace/coverage/default/21.gpio_smoke_no_pullup_pulldown.1159504776
Short name T178
Test name
Test status
Simulation time 58597135 ps
CPU time 1.13 seconds
Started Jun 30 04:23:42 PM PDT 24
Finished Jun 30 04:23:43 PM PDT 24
Peak memory 196764 kb
Host smart-154a946e-e8ec-4cca-bd1c-d0726d317258
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1159504776 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_smoke_no_pullup_pulldown.1159504776
Directory /workspace/21.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/21.gpio_stress_all.1357903093
Short name T332
Test name
Test status
Simulation time 5669378458 ps
CPU time 70.61 seconds
Started Jun 30 04:23:33 PM PDT 24
Finished Jun 30 04:24:44 PM PDT 24
Peak memory 198564 kb
Host smart-53b0663f-0217-42ba-8c81-0bf2de32517c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1357903093 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.
gpio_stress_all.1357903093
Directory /workspace/21.gpio_stress_all/latest

Test location /workspace/coverage/default/21.gpio_stress_all_with_rand_reset.4188715873
Short name T648
Test name
Test status
Simulation time 17075083676 ps
CPU time 317.53 seconds
Started Jun 30 04:23:48 PM PDT 24
Finished Jun 30 04:29:07 PM PDT 24
Peak memory 198792 kb
Host smart-9970ea71-5e20-4bb1-9f7d-38b51ef8539f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=4188715873 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_stress_all_with_rand_reset.4188715873
Directory /workspace/21.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.gpio_alert_test.4052215764
Short name T336
Test name
Test status
Simulation time 16741690 ps
CPU time 0.58 seconds
Started Jun 30 04:23:58 PM PDT 24
Finished Jun 30 04:23:59 PM PDT 24
Peak memory 195416 kb
Host smart-d4e777ad-0138-409b-b083-7d99efac4a8e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4052215764 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_alert_test.4052215764
Directory /workspace/22.gpio_alert_test/latest

Test location /workspace/coverage/default/22.gpio_dout_din_regs_random_rw.1153702177
Short name T398
Test name
Test status
Simulation time 42468398 ps
CPU time 0.72 seconds
Started Jun 30 04:23:40 PM PDT 24
Finished Jun 30 04:23:42 PM PDT 24
Peak memory 196488 kb
Host smart-7e9c675d-b04a-4021-b8ab-69a724760733
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1153702177 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_dout_din_regs_random_rw.1153702177
Directory /workspace/22.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/22.gpio_filter_stress.4000172314
Short name T474
Test name
Test status
Simulation time 1243069936 ps
CPU time 7.82 seconds
Started Jun 30 04:23:52 PM PDT 24
Finished Jun 30 04:24:01 PM PDT 24
Peak memory 197216 kb
Host smart-6e8e86e8-1fbf-48bf-a3a5-dc6e4814512c
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4000172314 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_filter_stre
ss.4000172314
Directory /workspace/22.gpio_filter_stress/latest

Test location /workspace/coverage/default/22.gpio_full_random.3692096310
Short name T409
Test name
Test status
Simulation time 33146626 ps
CPU time 0.67 seconds
Started Jun 30 04:23:34 PM PDT 24
Finished Jun 30 04:23:36 PM PDT 24
Peak memory 195128 kb
Host smart-b8374c01-a7fa-4ba3-8acc-f045d40c6a5d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3692096310 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_full_random.3692096310
Directory /workspace/22.gpio_full_random/latest

Test location /workspace/coverage/default/22.gpio_intr_rand_pgm.4188946932
Short name T248
Test name
Test status
Simulation time 215494848 ps
CPU time 1.13 seconds
Started Jun 30 04:24:00 PM PDT 24
Finished Jun 30 04:24:04 PM PDT 24
Peak memory 196568 kb
Host smart-90694a42-5934-4b10-9308-43d6a83aa0de
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4188946932 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_intr_rand_pgm.4188946932
Directory /workspace/22.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/22.gpio_intr_with_filter_rand_intr_event.3740226205
Short name T31
Test name
Test status
Simulation time 241293913 ps
CPU time 1.26 seconds
Started Jun 30 04:23:30 PM PDT 24
Finished Jun 30 04:23:32 PM PDT 24
Peak memory 198412 kb
Host smart-045b1038-9978-457c-9222-feb63165f340
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3740226205 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 22.gpio_intr_with_filter_rand_intr_event.3740226205
Directory /workspace/22.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/22.gpio_rand_intr_trigger.2144790760
Short name T558
Test name
Test status
Simulation time 166503199 ps
CPU time 2.4 seconds
Started Jun 30 04:23:38 PM PDT 24
Finished Jun 30 04:23:41 PM PDT 24
Peak memory 197660 kb
Host smart-0d2c79f0-585e-4f56-b6ec-e32de43ba9d1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2144790760 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_rand_intr_trigger
.2144790760
Directory /workspace/22.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/22.gpio_random_dout_din.650952546
Short name T27
Test name
Test status
Simulation time 66785826 ps
CPU time 0.88 seconds
Started Jun 30 04:23:52 PM PDT 24
Finished Jun 30 04:23:54 PM PDT 24
Peak memory 197204 kb
Host smart-4d08087e-531e-40fd-a9d8-f0482b9c9b7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=650952546 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_random_dout_din.650952546
Directory /workspace/22.gpio_random_dout_din/latest

Test location /workspace/coverage/default/22.gpio_random_dout_din_no_pullup_pulldown.387517827
Short name T440
Test name
Test status
Simulation time 154692516 ps
CPU time 0.94 seconds
Started Jun 30 04:23:49 PM PDT 24
Finished Jun 30 04:23:51 PM PDT 24
Peak memory 196512 kb
Host smart-ebab5ade-bc9f-46ab-bc3c-5e280bb364ed
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=387517827 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_random_dout_din_no_pullup
_pulldown.387517827
Directory /workspace/22.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/22.gpio_random_long_reg_writes_reg_reads.1415154937
Short name T528
Test name
Test status
Simulation time 116364832 ps
CPU time 2.57 seconds
Started Jun 30 04:23:39 PM PDT 24
Finished Jun 30 04:23:42 PM PDT 24
Peak memory 198496 kb
Host smart-773e2aed-f8de-4512-9bf4-e3a31068acb8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1415154937 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_ra
ndom_long_reg_writes_reg_reads.1415154937
Directory /workspace/22.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/22.gpio_smoke.1471565592
Short name T491
Test name
Test status
Simulation time 43900795 ps
CPU time 0.99 seconds
Started Jun 30 04:23:46 PM PDT 24
Finished Jun 30 04:23:48 PM PDT 24
Peak memory 195816 kb
Host smart-2b4fe8f0-7179-4a2a-9fa0-fae7d512dbd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1471565592 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_smoke.1471565592
Directory /workspace/22.gpio_smoke/latest

Test location /workspace/coverage/default/22.gpio_smoke_no_pullup_pulldown.2740891433
Short name T286
Test name
Test status
Simulation time 182325610 ps
CPU time 0.9 seconds
Started Jun 30 04:23:44 PM PDT 24
Finished Jun 30 04:23:45 PM PDT 24
Peak memory 195724 kb
Host smart-ac87e5ac-7803-4a47-9ef2-620e366c015b
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2740891433 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_smoke_no_pullup_pulldown.2740891433
Directory /workspace/22.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/22.gpio_stress_all.355364634
Short name T282
Test name
Test status
Simulation time 5286841977 ps
CPU time 28.03 seconds
Started Jun 30 04:23:42 PM PDT 24
Finished Jun 30 04:24:11 PM PDT 24
Peak memory 198584 kb
Host smart-b70299e1-691b-4ac3-bc0c-7f1a1eb8fbd1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=355364634 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.g
pio_stress_all.355364634
Directory /workspace/22.gpio_stress_all/latest

Test location /workspace/coverage/default/23.gpio_alert_test.2611107545
Short name T534
Test name
Test status
Simulation time 39863623 ps
CPU time 0.55 seconds
Started Jun 30 04:23:39 PM PDT 24
Finished Jun 30 04:23:40 PM PDT 24
Peak memory 195348 kb
Host smart-3f24baf8-04ff-4abb-9137-13f4b2aed131
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2611107545 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_alert_test.2611107545
Directory /workspace/23.gpio_alert_test/latest

Test location /workspace/coverage/default/23.gpio_dout_din_regs_random_rw.3155365974
Short name T225
Test name
Test status
Simulation time 23558568 ps
CPU time 0.81 seconds
Started Jun 30 04:23:26 PM PDT 24
Finished Jun 30 04:23:28 PM PDT 24
Peak memory 196400 kb
Host smart-e1c1a487-6a75-4eda-9455-2d906da53e07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3155365974 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_dout_din_regs_random_rw.3155365974
Directory /workspace/23.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/23.gpio_filter_stress.2166704918
Short name T16
Test name
Test status
Simulation time 83857136 ps
CPU time 4.25 seconds
Started Jun 30 04:23:29 PM PDT 24
Finished Jun 30 04:23:34 PM PDT 24
Peak memory 196236 kb
Host smart-b3b2aca1-c637-4a4c-9003-15d8afc35e94
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2166704918 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_filter_stre
ss.2166704918
Directory /workspace/23.gpio_filter_stress/latest

Test location /workspace/coverage/default/23.gpio_full_random.3503050018
Short name T264
Test name
Test status
Simulation time 87292301 ps
CPU time 0.98 seconds
Started Jun 30 04:23:43 PM PDT 24
Finished Jun 30 04:23:44 PM PDT 24
Peak memory 197056 kb
Host smart-a0a5f657-381f-4a25-88dc-d52044058231
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3503050018 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_full_random.3503050018
Directory /workspace/23.gpio_full_random/latest

Test location /workspace/coverage/default/23.gpio_intr_rand_pgm.1733030303
Short name T193
Test name
Test status
Simulation time 219821986 ps
CPU time 1.43 seconds
Started Jun 30 04:23:30 PM PDT 24
Finished Jun 30 04:23:32 PM PDT 24
Peak memory 197552 kb
Host smart-5283a387-702a-4368-89de-c738bf91bf49
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1733030303 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_intr_rand_pgm.1733030303
Directory /workspace/23.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/23.gpio_intr_with_filter_rand_intr_event.3176957084
Short name T185
Test name
Test status
Simulation time 53624372 ps
CPU time 2.05 seconds
Started Jun 30 04:23:50 PM PDT 24
Finished Jun 30 04:23:53 PM PDT 24
Peak memory 198532 kb
Host smart-917d79da-7881-4c13-8348-4822be6a6e5b
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3176957084 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 23.gpio_intr_with_filter_rand_intr_event.3176957084
Directory /workspace/23.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/23.gpio_rand_intr_trigger.3300917224
Short name T23
Test name
Test status
Simulation time 264107313 ps
CPU time 2.74 seconds
Started Jun 30 04:23:48 PM PDT 24
Finished Jun 30 04:23:53 PM PDT 24
Peak memory 198428 kb
Host smart-3301e145-df8a-4418-9c97-03e3538d67e7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3300917224 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_rand_intr_trigger
.3300917224
Directory /workspace/23.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/23.gpio_random_dout_din.3054411485
Short name T434
Test name
Test status
Simulation time 142595988 ps
CPU time 1.18 seconds
Started Jun 30 04:23:34 PM PDT 24
Finished Jun 30 04:23:36 PM PDT 24
Peak memory 197544 kb
Host smart-a754c2ed-8641-4cb0-9277-7de5efc683e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3054411485 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_random_dout_din.3054411485
Directory /workspace/23.gpio_random_dout_din/latest

Test location /workspace/coverage/default/23.gpio_random_dout_din_no_pullup_pulldown.2429673337
Short name T597
Test name
Test status
Simulation time 25048838 ps
CPU time 0.79 seconds
Started Jun 30 04:23:43 PM PDT 24
Finished Jun 30 04:23:44 PM PDT 24
Peak memory 196280 kb
Host smart-39246856-9266-4e8c-a3a5-318457259a2a
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2429673337 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_random_dout_din_no_pullu
p_pulldown.2429673337
Directory /workspace/23.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/23.gpio_random_long_reg_writes_reg_reads.3146940658
Short name T151
Test name
Test status
Simulation time 72793015 ps
CPU time 1.43 seconds
Started Jun 30 04:23:33 PM PDT 24
Finished Jun 30 04:23:35 PM PDT 24
Peak memory 198408 kb
Host smart-c9a497dd-e182-4d85-a3b3-55a5b9738271
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3146940658 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_ra
ndom_long_reg_writes_reg_reads.3146940658
Directory /workspace/23.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/23.gpio_smoke.2395462083
Short name T251
Test name
Test status
Simulation time 209513349 ps
CPU time 1.34 seconds
Started Jun 30 04:23:35 PM PDT 24
Finished Jun 30 04:23:37 PM PDT 24
Peak memory 198452 kb
Host smart-007be079-5ec9-4e4b-85a4-8108b1e53043
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2395462083 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_smoke.2395462083
Directory /workspace/23.gpio_smoke/latest

Test location /workspace/coverage/default/23.gpio_smoke_no_pullup_pulldown.3697132488
Short name T244
Test name
Test status
Simulation time 396522227 ps
CPU time 1.37 seconds
Started Jun 30 04:23:52 PM PDT 24
Finished Jun 30 04:23:55 PM PDT 24
Peak memory 197196 kb
Host smart-d439a061-7dfb-4bb5-9d7a-c29a02e0a3a3
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3697132488 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_smoke_no_pullup_pulldown.3697132488
Directory /workspace/23.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/23.gpio_stress_all.501742358
Short name T427
Test name
Test status
Simulation time 8207722890 ps
CPU time 216.93 seconds
Started Jun 30 04:23:58 PM PDT 24
Finished Jun 30 04:27:36 PM PDT 24
Peak memory 198996 kb
Host smart-08056342-d01b-4c7f-bf28-e5d81ac94079
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=501742358 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.g
pio_stress_all.501742358
Directory /workspace/23.gpio_stress_all/latest

Test location /workspace/coverage/default/23.gpio_stress_all_with_rand_reset.3184805569
Short name T581
Test name
Test status
Simulation time 36988766867 ps
CPU time 979.07 seconds
Started Jun 30 04:23:36 PM PDT 24
Finished Jun 30 04:39:56 PM PDT 24
Peak memory 198748 kb
Host smart-d54cea8d-75e7-4609-b88f-15888b992792
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3184805569 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_stress_all_with_rand_reset.3184805569
Directory /workspace/23.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.gpio_alert_test.1010106614
Short name T428
Test name
Test status
Simulation time 13121999 ps
CPU time 0.58 seconds
Started Jun 30 04:23:57 PM PDT 24
Finished Jun 30 04:23:58 PM PDT 24
Peak memory 195108 kb
Host smart-159588d8-877d-46fb-a068-13926400be52
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1010106614 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_alert_test.1010106614
Directory /workspace/24.gpio_alert_test/latest

Test location /workspace/coverage/default/24.gpio_dout_din_regs_random_rw.1494672277
Short name T654
Test name
Test status
Simulation time 40668110 ps
CPU time 0.83 seconds
Started Jun 30 04:23:40 PM PDT 24
Finished Jun 30 04:23:41 PM PDT 24
Peak memory 196136 kb
Host smart-255fe202-39b3-4de6-b8dd-c86e37531a8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1494672277 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_dout_din_regs_random_rw.1494672277
Directory /workspace/24.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/24.gpio_filter_stress.3035084992
Short name T255
Test name
Test status
Simulation time 604744808 ps
CPU time 20.11 seconds
Started Jun 30 04:23:39 PM PDT 24
Finished Jun 30 04:24:00 PM PDT 24
Peak memory 198408 kb
Host smart-fe56461f-7b05-4436-b044-b6baac356b1b
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3035084992 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_filter_stre
ss.3035084992
Directory /workspace/24.gpio_filter_stress/latest

Test location /workspace/coverage/default/24.gpio_full_random.1314888704
Short name T324
Test name
Test status
Simulation time 71017824 ps
CPU time 0.9 seconds
Started Jun 30 04:24:03 PM PDT 24
Finished Jun 30 04:24:07 PM PDT 24
Peak memory 197456 kb
Host smart-c8004bf6-4a2b-4d02-b6ac-2b5614f20dc9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1314888704 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_full_random.1314888704
Directory /workspace/24.gpio_full_random/latest

Test location /workspace/coverage/default/24.gpio_intr_rand_pgm.2601032172
Short name T318
Test name
Test status
Simulation time 19807701 ps
CPU time 0.67 seconds
Started Jun 30 04:23:49 PM PDT 24
Finished Jun 30 04:23:51 PM PDT 24
Peak memory 194792 kb
Host smart-9b11775b-60b6-4163-a122-bb6fda9beba7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2601032172 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_intr_rand_pgm.2601032172
Directory /workspace/24.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/24.gpio_intr_with_filter_rand_intr_event.2539457654
Short name T541
Test name
Test status
Simulation time 21094990 ps
CPU time 0.91 seconds
Started Jun 30 04:23:54 PM PDT 24
Finished Jun 30 04:23:56 PM PDT 24
Peak memory 197396 kb
Host smart-e4b298d0-dfd4-4efb-949d-0e1d74875173
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2539457654 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 24.gpio_intr_with_filter_rand_intr_event.2539457654
Directory /workspace/24.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/24.gpio_rand_intr_trigger.1496204067
Short name T15
Test name
Test status
Simulation time 474142701 ps
CPU time 2.53 seconds
Started Jun 30 04:23:56 PM PDT 24
Finished Jun 30 04:24:00 PM PDT 24
Peak memory 198480 kb
Host smart-5c22ff50-db64-490f-9e7a-6e99b14c70b6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1496204067 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_rand_intr_trigger
.1496204067
Directory /workspace/24.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/24.gpio_random_dout_din.3894316100
Short name T668
Test name
Test status
Simulation time 109344548 ps
CPU time 1.28 seconds
Started Jun 30 04:23:42 PM PDT 24
Finished Jun 30 04:23:44 PM PDT 24
Peak memory 198472 kb
Host smart-3ff0b4f2-aa64-435e-8c39-b3fc892053e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3894316100 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_random_dout_din.3894316100
Directory /workspace/24.gpio_random_dout_din/latest

Test location /workspace/coverage/default/24.gpio_random_dout_din_no_pullup_pulldown.4097077481
Short name T375
Test name
Test status
Simulation time 180388633 ps
CPU time 1.08 seconds
Started Jun 30 04:23:38 PM PDT 24
Finished Jun 30 04:23:40 PM PDT 24
Peak memory 196280 kb
Host smart-f6df8514-260f-4b93-81c5-cc441d508e50
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4097077481 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_random_dout_din_no_pullu
p_pulldown.4097077481
Directory /workspace/24.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/24.gpio_random_long_reg_writes_reg_reads.4068460458
Short name T521
Test name
Test status
Simulation time 1439109006 ps
CPU time 5.74 seconds
Started Jun 30 04:24:01 PM PDT 24
Finished Jun 30 04:24:09 PM PDT 24
Peak memory 198328 kb
Host smart-b2ed4d04-7c08-4f24-9ce1-1b0f8a791aab
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4068460458 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_ra
ndom_long_reg_writes_reg_reads.4068460458
Directory /workspace/24.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/24.gpio_smoke.3485637472
Short name T646
Test name
Test status
Simulation time 58861539 ps
CPU time 0.92 seconds
Started Jun 30 04:23:29 PM PDT 24
Finished Jun 30 04:23:31 PM PDT 24
Peak memory 197284 kb
Host smart-e4fc1122-997d-4576-9050-308d8f129959
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3485637472 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_smoke.3485637472
Directory /workspace/24.gpio_smoke/latest

Test location /workspace/coverage/default/24.gpio_smoke_no_pullup_pulldown.187614526
Short name T691
Test name
Test status
Simulation time 192787022 ps
CPU time 1.29 seconds
Started Jun 30 04:23:35 PM PDT 24
Finished Jun 30 04:23:37 PM PDT 24
Peak memory 198448 kb
Host smart-0172cce6-40ac-4bda-9854-f0bb84c3e84a
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=187614526 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_smoke_no_pullup_pulldown.187614526
Directory /workspace/24.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/24.gpio_stress_all.3819884911
Short name T697
Test name
Test status
Simulation time 2616377183 ps
CPU time 61.58 seconds
Started Jun 30 04:23:53 PM PDT 24
Finished Jun 30 04:24:56 PM PDT 24
Peak memory 198596 kb
Host smart-69373d1b-7ad6-4ea7-a546-3fd68ec7a4bb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3819884911 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.
gpio_stress_all.3819884911
Directory /workspace/24.gpio_stress_all/latest

Test location /workspace/coverage/default/25.gpio_alert_test.1717462394
Short name T129
Test name
Test status
Simulation time 43827486 ps
CPU time 0.57 seconds
Started Jun 30 04:23:48 PM PDT 24
Finished Jun 30 04:23:50 PM PDT 24
Peak memory 194732 kb
Host smart-57735630-024b-4ca4-9a2b-edfe2e87a8a6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1717462394 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_alert_test.1717462394
Directory /workspace/25.gpio_alert_test/latest

Test location /workspace/coverage/default/25.gpio_dout_din_regs_random_rw.2635880445
Short name T571
Test name
Test status
Simulation time 39267565 ps
CPU time 0.88 seconds
Started Jun 30 04:23:37 PM PDT 24
Finished Jun 30 04:23:38 PM PDT 24
Peak memory 197084 kb
Host smart-16806674-e04e-4d73-bc9d-ccadfbc53f34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2635880445 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_dout_din_regs_random_rw.2635880445
Directory /workspace/25.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/25.gpio_filter_stress.2562880403
Short name T357
Test name
Test status
Simulation time 215140798 ps
CPU time 10.34 seconds
Started Jun 30 04:23:32 PM PDT 24
Finished Jun 30 04:23:43 PM PDT 24
Peak memory 197440 kb
Host smart-f0c1a655-8b9f-4e00-acb6-8fbf6002a14c
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2562880403 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_filter_stre
ss.2562880403
Directory /workspace/25.gpio_filter_stress/latest

Test location /workspace/coverage/default/25.gpio_full_random.2986973315
Short name T443
Test name
Test status
Simulation time 579690599 ps
CPU time 0.84 seconds
Started Jun 30 04:23:44 PM PDT 24
Finished Jun 30 04:23:45 PM PDT 24
Peak memory 196844 kb
Host smart-22f9fc23-3480-42f2-8bbf-dba7ac99a720
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2986973315 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_full_random.2986973315
Directory /workspace/25.gpio_full_random/latest

Test location /workspace/coverage/default/25.gpio_intr_rand_pgm.3096127074
Short name T512
Test name
Test status
Simulation time 86384577 ps
CPU time 1.36 seconds
Started Jun 30 04:23:50 PM PDT 24
Finished Jun 30 04:23:52 PM PDT 24
Peak memory 197656 kb
Host smart-9002f07a-3494-4df8-b244-f70394adb8fe
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3096127074 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_intr_rand_pgm.3096127074
Directory /workspace/25.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/25.gpio_intr_with_filter_rand_intr_event.3509174626
Short name T636
Test name
Test status
Simulation time 349565180 ps
CPU time 3.23 seconds
Started Jun 30 04:23:53 PM PDT 24
Finished Jun 30 04:23:58 PM PDT 24
Peak memory 196900 kb
Host smart-155fd680-274b-4783-8bf5-cbdc8b3e635d
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3509174626 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 25.gpio_intr_with_filter_rand_intr_event.3509174626
Directory /workspace/25.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/25.gpio_rand_intr_trigger.3202841610
Short name T656
Test name
Test status
Simulation time 62718203 ps
CPU time 1.39 seconds
Started Jun 30 04:24:00 PM PDT 24
Finished Jun 30 04:24:03 PM PDT 24
Peak memory 196520 kb
Host smart-602a36a1-87e0-4a13-9a71-3501f907bd94
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3202841610 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_rand_intr_trigger
.3202841610
Directory /workspace/25.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/25.gpio_random_dout_din.369456394
Short name T135
Test name
Test status
Simulation time 21011739 ps
CPU time 0.71 seconds
Started Jun 30 04:23:41 PM PDT 24
Finished Jun 30 04:23:42 PM PDT 24
Peak memory 195880 kb
Host smart-dcdbaa76-fc19-4399-9654-e8475a6e878b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=369456394 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_random_dout_din.369456394
Directory /workspace/25.gpio_random_dout_din/latest

Test location /workspace/coverage/default/25.gpio_random_dout_din_no_pullup_pulldown.2143967661
Short name T113
Test name
Test status
Simulation time 61488517 ps
CPU time 1.06 seconds
Started Jun 30 04:23:42 PM PDT 24
Finished Jun 30 04:23:44 PM PDT 24
Peak memory 196556 kb
Host smart-33535cfa-8325-4d2a-bc58-4ff012b04ca6
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2143967661 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_random_dout_din_no_pullu
p_pulldown.2143967661
Directory /workspace/25.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/25.gpio_random_long_reg_writes_reg_reads.3522973069
Short name T588
Test name
Test status
Simulation time 94332631 ps
CPU time 1.91 seconds
Started Jun 30 04:23:52 PM PDT 24
Finished Jun 30 04:23:54 PM PDT 24
Peak memory 198388 kb
Host smart-93171be5-0a07-4f3e-a22f-2e5443133dc9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3522973069 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_ra
ndom_long_reg_writes_reg_reads.3522973069
Directory /workspace/25.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/25.gpio_smoke.2460532804
Short name T252
Test name
Test status
Simulation time 86497901 ps
CPU time 0.97 seconds
Started Jun 30 04:23:48 PM PDT 24
Finished Jun 30 04:23:49 PM PDT 24
Peak memory 196048 kb
Host smart-bb042f22-9330-470a-8d9c-bd6ed19a9fc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2460532804 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_smoke.2460532804
Directory /workspace/25.gpio_smoke/latest

Test location /workspace/coverage/default/25.gpio_smoke_no_pullup_pulldown.668338771
Short name T407
Test name
Test status
Simulation time 69986385 ps
CPU time 0.85 seconds
Started Jun 30 04:23:41 PM PDT 24
Finished Jun 30 04:23:43 PM PDT 24
Peak memory 196800 kb
Host smart-1006e958-d62d-4646-af74-7b0b28475fa6
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=668338771 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_smoke_no_pullup_pulldown.668338771
Directory /workspace/25.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/25.gpio_stress_all.704414737
Short name T191
Test name
Test status
Simulation time 5256061392 ps
CPU time 128.95 seconds
Started Jun 30 04:23:39 PM PDT 24
Finished Jun 30 04:25:49 PM PDT 24
Peak memory 198568 kb
Host smart-f576f44b-518a-4ae2-91e4-f9b8623572e9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=704414737 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.g
pio_stress_all.704414737
Directory /workspace/25.gpio_stress_all/latest

Test location /workspace/coverage/default/26.gpio_alert_test.2195864667
Short name T575
Test name
Test status
Simulation time 43598614 ps
CPU time 0.61 seconds
Started Jun 30 04:23:52 PM PDT 24
Finished Jun 30 04:23:54 PM PDT 24
Peak memory 194588 kb
Host smart-bdc8ebdc-da88-4277-b140-b9e84e90683f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2195864667 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_alert_test.2195864667
Directory /workspace/26.gpio_alert_test/latest

Test location /workspace/coverage/default/26.gpio_dout_din_regs_random_rw.2933015351
Short name T202
Test name
Test status
Simulation time 51248582 ps
CPU time 0.99 seconds
Started Jun 30 04:23:53 PM PDT 24
Finished Jun 30 04:23:55 PM PDT 24
Peak memory 197056 kb
Host smart-081e4880-5fac-4d94-b1df-ff353d1d7c59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2933015351 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_dout_din_regs_random_rw.2933015351
Directory /workspace/26.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/26.gpio_filter_stress.2998265229
Short name T712
Test name
Test status
Simulation time 6904493210 ps
CPU time 12.42 seconds
Started Jun 30 04:23:55 PM PDT 24
Finished Jun 30 04:24:09 PM PDT 24
Peak memory 197428 kb
Host smart-4f03a456-dfbb-4ab7-98e9-8316104d8015
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2998265229 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_filter_stre
ss.2998265229
Directory /workspace/26.gpio_filter_stress/latest

Test location /workspace/coverage/default/26.gpio_full_random.340295212
Short name T414
Test name
Test status
Simulation time 30026113 ps
CPU time 0.64 seconds
Started Jun 30 04:23:51 PM PDT 24
Finished Jun 30 04:23:52 PM PDT 24
Peak memory 195080 kb
Host smart-0d8e8da5-07d5-420d-99a3-951f92415ac5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=340295212 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_full_random.340295212
Directory /workspace/26.gpio_full_random/latest

Test location /workspace/coverage/default/26.gpio_intr_rand_pgm.3209350726
Short name T711
Test name
Test status
Simulation time 148443488 ps
CPU time 1.17 seconds
Started Jun 30 04:23:50 PM PDT 24
Finished Jun 30 04:23:52 PM PDT 24
Peak memory 197304 kb
Host smart-647b8be8-38b0-4ad4-96fc-aa9c5c6dcefe
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3209350726 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_intr_rand_pgm.3209350726
Directory /workspace/26.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/26.gpio_intr_with_filter_rand_intr_event.2312513851
Short name T444
Test name
Test status
Simulation time 225761068 ps
CPU time 1.37 seconds
Started Jun 30 04:23:56 PM PDT 24
Finished Jun 30 04:23:59 PM PDT 24
Peak memory 196912 kb
Host smart-349483d0-7914-4b1c-bf4f-0b309902b5ca
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2312513851 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 26.gpio_intr_with_filter_rand_intr_event.2312513851
Directory /workspace/26.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/26.gpio_rand_intr_trigger.3019296716
Short name T667
Test name
Test status
Simulation time 930863580 ps
CPU time 2.79 seconds
Started Jun 30 04:23:55 PM PDT 24
Finished Jun 30 04:23:59 PM PDT 24
Peak memory 197584 kb
Host smart-1efcd7bf-9c6e-4314-82df-a4e8a9bfb930
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3019296716 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_rand_intr_trigger
.3019296716
Directory /workspace/26.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/26.gpio_random_dout_din.2807841116
Short name T328
Test name
Test status
Simulation time 110049676 ps
CPU time 0.62 seconds
Started Jun 30 04:24:02 PM PDT 24
Finished Jun 30 04:24:06 PM PDT 24
Peak memory 195368 kb
Host smart-f777477d-4cc3-44c8-bc4c-698defdefaf2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2807841116 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_random_dout_din.2807841116
Directory /workspace/26.gpio_random_dout_din/latest

Test location /workspace/coverage/default/26.gpio_random_dout_din_no_pullup_pulldown.3701504015
Short name T522
Test name
Test status
Simulation time 36683797 ps
CPU time 0.68 seconds
Started Jun 30 04:23:46 PM PDT 24
Finished Jun 30 04:23:48 PM PDT 24
Peak memory 194772 kb
Host smart-9527a9cb-d440-4028-a1d7-344dc9c92914
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3701504015 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_random_dout_din_no_pullu
p_pulldown.3701504015
Directory /workspace/26.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/26.gpio_random_long_reg_writes_reg_reads.2761363833
Short name T572
Test name
Test status
Simulation time 197495198 ps
CPU time 2.15 seconds
Started Jun 30 04:23:28 PM PDT 24
Finished Jun 30 04:23:36 PM PDT 24
Peak memory 198376 kb
Host smart-6a27f198-60d7-4b10-a234-b571341c8aa5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2761363833 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_ra
ndom_long_reg_writes_reg_reads.2761363833
Directory /workspace/26.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/26.gpio_smoke.1158363398
Short name T449
Test name
Test status
Simulation time 208732541 ps
CPU time 0.96 seconds
Started Jun 30 04:24:01 PM PDT 24
Finished Jun 30 04:24:05 PM PDT 24
Peak memory 196688 kb
Host smart-bb042fee-3fc4-44c6-a91b-ccdea7799467
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1158363398 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_smoke.1158363398
Directory /workspace/26.gpio_smoke/latest

Test location /workspace/coverage/default/26.gpio_smoke_no_pullup_pulldown.1560156529
Short name T586
Test name
Test status
Simulation time 199810908 ps
CPU time 1.35 seconds
Started Jun 30 04:24:14 PM PDT 24
Finished Jun 30 04:24:17 PM PDT 24
Peak memory 197088 kb
Host smart-4ee4eeca-8e80-43ca-8e08-f2ea6db7efea
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1560156529 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_smoke_no_pullup_pulldown.1560156529
Directory /workspace/26.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/26.gpio_stress_all.561104814
Short name T208
Test name
Test status
Simulation time 26990351645 ps
CPU time 187.52 seconds
Started Jun 30 04:24:00 PM PDT 24
Finished Jun 30 04:27:09 PM PDT 24
Peak memory 198476 kb
Host smart-3da5f4d3-6239-46c9-bd01-2770c7118188
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=561104814 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.g
pio_stress_all.561104814
Directory /workspace/26.gpio_stress_all/latest

Test location /workspace/coverage/default/26.gpio_stress_all_with_rand_reset.4094002816
Short name T694
Test name
Test status
Simulation time 152130392600 ps
CPU time 474.33 seconds
Started Jun 30 04:23:52 PM PDT 24
Finished Jun 30 04:31:48 PM PDT 24
Peak memory 198688 kb
Host smart-8e3f1cf5-c756-4a53-80c5-5bb5ff168840
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=4094002816 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_stress_all_with_rand_reset.4094002816
Directory /workspace/26.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.gpio_alert_test.3343034884
Short name T41
Test name
Test status
Simulation time 69361299 ps
CPU time 0.57 seconds
Started Jun 30 04:23:54 PM PDT 24
Finished Jun 30 04:23:56 PM PDT 24
Peak memory 194636 kb
Host smart-22dfe6c3-c031-4c51-a0fc-62f4bb574588
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3343034884 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_alert_test.3343034884
Directory /workspace/27.gpio_alert_test/latest

Test location /workspace/coverage/default/27.gpio_dout_din_regs_random_rw.3531762824
Short name T647
Test name
Test status
Simulation time 63814579 ps
CPU time 0.67 seconds
Started Jun 30 04:23:59 PM PDT 24
Finished Jun 30 04:24:02 PM PDT 24
Peak memory 194552 kb
Host smart-2dbb8aff-5fb1-4355-9013-afa9455e8f46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3531762824 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_dout_din_regs_random_rw.3531762824
Directory /workspace/27.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/27.gpio_filter_stress.613143794
Short name T287
Test name
Test status
Simulation time 9939470087 ps
CPU time 26.44 seconds
Started Jun 30 04:23:48 PM PDT 24
Finished Jun 30 04:24:16 PM PDT 24
Peak memory 197548 kb
Host smart-bb87ed54-4619-4936-a9ba-dc02efbbdc93
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=613143794 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_filter_stres
s.613143794
Directory /workspace/27.gpio_filter_stress/latest

Test location /workspace/coverage/default/27.gpio_full_random.196996987
Short name T236
Test name
Test status
Simulation time 89330257 ps
CPU time 0.98 seconds
Started Jun 30 04:23:50 PM PDT 24
Finished Jun 30 04:23:52 PM PDT 24
Peak memory 197496 kb
Host smart-fbecff49-dfc7-451b-9229-1f630d88e072
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=196996987 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_full_random.196996987
Directory /workspace/27.gpio_full_random/latest

Test location /workspace/coverage/default/27.gpio_intr_rand_pgm.1149505250
Short name T537
Test name
Test status
Simulation time 76096843 ps
CPU time 1.14 seconds
Started Jun 30 04:24:02 PM PDT 24
Finished Jun 30 04:24:06 PM PDT 24
Peak memory 196448 kb
Host smart-119c14a3-0e9f-48d2-b8bf-fc5fa95a71da
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1149505250 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_intr_rand_pgm.1149505250
Directory /workspace/27.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/27.gpio_intr_with_filter_rand_intr_event.3145691074
Short name T472
Test name
Test status
Simulation time 57176506 ps
CPU time 2.28 seconds
Started Jun 30 04:23:59 PM PDT 24
Finished Jun 30 04:24:03 PM PDT 24
Peak memory 198484 kb
Host smart-1a7b7558-87f7-4ea9-9f90-958eba54e4fc
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3145691074 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 27.gpio_intr_with_filter_rand_intr_event.3145691074
Directory /workspace/27.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/27.gpio_rand_intr_trigger.4256692516
Short name T117
Test name
Test status
Simulation time 69128052 ps
CPU time 1.9 seconds
Started Jun 30 04:23:54 PM PDT 24
Finished Jun 30 04:23:57 PM PDT 24
Peak memory 198516 kb
Host smart-3de2020e-4d8a-4ea4-b67c-50da060d0a84
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4256692516 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_rand_intr_trigger
.4256692516
Directory /workspace/27.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/27.gpio_random_dout_din.2500770853
Short name T550
Test name
Test status
Simulation time 154269677 ps
CPU time 0.93 seconds
Started Jun 30 04:23:53 PM PDT 24
Finished Jun 30 04:23:56 PM PDT 24
Peak memory 196412 kb
Host smart-63bc5891-112a-447a-be3e-e962faabba5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2500770853 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_random_dout_din.2500770853
Directory /workspace/27.gpio_random_dout_din/latest

Test location /workspace/coverage/default/27.gpio_random_dout_din_no_pullup_pulldown.1255595
Short name T609
Test name
Test status
Simulation time 287470628 ps
CPU time 1.2 seconds
Started Jun 30 04:24:14 PM PDT 24
Finished Jun 30 04:24:17 PM PDT 24
Peak memory 197392 kb
Host smart-04d9fd06-c68a-4578-9c8a-86a23ac008a4
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1255595 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_random_dout_din_no_pullup_p
ulldown.1255595
Directory /workspace/27.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/27.gpio_random_long_reg_writes_reg_reads.875397077
Short name T459
Test name
Test status
Simulation time 77394802 ps
CPU time 1.5 seconds
Started Jun 30 04:23:48 PM PDT 24
Finished Jun 30 04:23:51 PM PDT 24
Peak memory 198480 kb
Host smart-a12ffff2-1a64-49ae-897e-42a640191d65
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=875397077 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_ran
dom_long_reg_writes_reg_reads.875397077
Directory /workspace/27.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/27.gpio_smoke.871967113
Short name T13
Test name
Test status
Simulation time 353508270 ps
CPU time 1.05 seconds
Started Jun 30 04:23:37 PM PDT 24
Finished Jun 30 04:23:39 PM PDT 24
Peak memory 196112 kb
Host smart-ffee9168-859e-4bea-8a01-aaab02c04721
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=871967113 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_smoke.871967113
Directory /workspace/27.gpio_smoke/latest

Test location /workspace/coverage/default/27.gpio_smoke_no_pullup_pulldown.4267402654
Short name T505
Test name
Test status
Simulation time 48968750 ps
CPU time 1.25 seconds
Started Jun 30 04:23:41 PM PDT 24
Finished Jun 30 04:23:43 PM PDT 24
Peak memory 198476 kb
Host smart-c8ac766e-bea7-4fa5-98fa-54371fe180cc
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4267402654 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_smoke_no_pullup_pulldown.4267402654
Directory /workspace/27.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/27.gpio_stress_all.1725787260
Short name T399
Test name
Test status
Simulation time 40557410316 ps
CPU time 103.99 seconds
Started Jun 30 04:23:57 PM PDT 24
Finished Jun 30 04:25:42 PM PDT 24
Peak memory 198584 kb
Host smart-d0598891-f4eb-4418-8ebf-975a826cfdb8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1725787260 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.
gpio_stress_all.1725787260
Directory /workspace/27.gpio_stress_all/latest

Test location /workspace/coverage/default/28.gpio_alert_test.1280264236
Short name T229
Test name
Test status
Simulation time 24210249 ps
CPU time 0.65 seconds
Started Jun 30 04:23:53 PM PDT 24
Finished Jun 30 04:23:54 PM PDT 24
Peak memory 194444 kb
Host smart-5615ae6f-19da-4300-900b-27d17338179c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1280264236 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_alert_test.1280264236
Directory /workspace/28.gpio_alert_test/latest

Test location /workspace/coverage/default/28.gpio_dout_din_regs_random_rw.3093094112
Short name T494
Test name
Test status
Simulation time 17121561 ps
CPU time 0.75 seconds
Started Jun 30 04:23:56 PM PDT 24
Finished Jun 30 04:24:04 PM PDT 24
Peak memory 195328 kb
Host smart-1321701c-58cf-4f1c-aadd-804fa66ed8bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3093094112 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_dout_din_regs_random_rw.3093094112
Directory /workspace/28.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/28.gpio_filter_stress.1510181113
Short name T212
Test name
Test status
Simulation time 597697198 ps
CPU time 6.61 seconds
Started Jun 30 04:24:02 PM PDT 24
Finished Jun 30 04:24:12 PM PDT 24
Peak memory 197404 kb
Host smart-6d056b22-a47b-42b8-9297-6f070e48a25f
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1510181113 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_filter_stre
ss.1510181113
Directory /workspace/28.gpio_filter_stress/latest

Test location /workspace/coverage/default/28.gpio_full_random.102068513
Short name T564
Test name
Test status
Simulation time 105583751 ps
CPU time 0.83 seconds
Started Jun 30 04:23:56 PM PDT 24
Finished Jun 30 04:23:58 PM PDT 24
Peak memory 197444 kb
Host smart-3484e7c2-f146-4bdc-9635-6c2fc25c9d01
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=102068513 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_full_random.102068513
Directory /workspace/28.gpio_full_random/latest

Test location /workspace/coverage/default/28.gpio_intr_rand_pgm.2766360577
Short name T266
Test name
Test status
Simulation time 186322868 ps
CPU time 0.86 seconds
Started Jun 30 04:23:40 PM PDT 24
Finished Jun 30 04:23:41 PM PDT 24
Peak memory 196692 kb
Host smart-c3775562-6fa7-4dd5-8fd6-4df2f70f14de
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2766360577 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_intr_rand_pgm.2766360577
Directory /workspace/28.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/28.gpio_intr_with_filter_rand_intr_event.836121639
Short name T120
Test name
Test status
Simulation time 119916607 ps
CPU time 1.87 seconds
Started Jun 30 04:23:47 PM PDT 24
Finished Jun 30 04:23:50 PM PDT 24
Peak memory 198464 kb
Host smart-f4a005c3-669c-4616-8fb5-b412ed605abb
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=836121639 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 28.gpio_intr_with_filter_rand_intr_event.836121639
Directory /workspace/28.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/28.gpio_rand_intr_trigger.3485775892
Short name T501
Test name
Test status
Simulation time 196634396 ps
CPU time 2.95 seconds
Started Jun 30 04:23:51 PM PDT 24
Finished Jun 30 04:23:54 PM PDT 24
Peak memory 197692 kb
Host smart-d5e45b06-a06e-46c2-8ce6-70ca3a6f60e0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3485775892 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_rand_intr_trigger
.3485775892
Directory /workspace/28.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/28.gpio_random_dout_din.3493890391
Short name T221
Test name
Test status
Simulation time 128029367 ps
CPU time 0.64 seconds
Started Jun 30 04:23:52 PM PDT 24
Finished Jun 30 04:23:53 PM PDT 24
Peak memory 194688 kb
Host smart-3327e39f-3a99-4ba0-94e4-c6daf47e5a61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3493890391 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_random_dout_din.3493890391
Directory /workspace/28.gpio_random_dout_din/latest

Test location /workspace/coverage/default/28.gpio_random_dout_din_no_pullup_pulldown.835777438
Short name T404
Test name
Test status
Simulation time 137266729 ps
CPU time 0.69 seconds
Started Jun 30 04:23:55 PM PDT 24
Finished Jun 30 04:23:57 PM PDT 24
Peak memory 195760 kb
Host smart-1f0f1614-d47f-43e6-b2bd-eb7b6fcfa9f0
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=835777438 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_random_dout_din_no_pullup
_pulldown.835777438
Directory /workspace/28.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/28.gpio_random_long_reg_writes_reg_reads.515650867
Short name T532
Test name
Test status
Simulation time 93149749 ps
CPU time 3.82 seconds
Started Jun 30 04:23:45 PM PDT 24
Finished Jun 30 04:23:49 PM PDT 24
Peak memory 198436 kb
Host smart-1f28e020-595c-4a7a-8c54-997cb96d8c6b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=515650867 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_ran
dom_long_reg_writes_reg_reads.515650867
Directory /workspace/28.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/28.gpio_smoke.3934277331
Short name T243
Test name
Test status
Simulation time 274699286 ps
CPU time 1.14 seconds
Started Jun 30 04:23:32 PM PDT 24
Finished Jun 30 04:23:34 PM PDT 24
Peak memory 196044 kb
Host smart-0f572187-5116-4af0-b5cb-bc93bfe466fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3934277331 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_smoke.3934277331
Directory /workspace/28.gpio_smoke/latest

Test location /workspace/coverage/default/28.gpio_smoke_no_pullup_pulldown.2518967241
Short name T335
Test name
Test status
Simulation time 189583566 ps
CPU time 1.27 seconds
Started Jun 30 04:23:37 PM PDT 24
Finished Jun 30 04:23:39 PM PDT 24
Peak memory 196056 kb
Host smart-10a48788-8c4a-411c-965b-cb37ecf9971f
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2518967241 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_smoke_no_pullup_pulldown.2518967241
Directory /workspace/28.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/28.gpio_stress_all.1595553431
Short name T345
Test name
Test status
Simulation time 41575239871 ps
CPU time 178.53 seconds
Started Jun 30 04:24:04 PM PDT 24
Finished Jun 30 04:27:06 PM PDT 24
Peak memory 198548 kb
Host smart-8ed41ded-7c0a-43a1-8e29-9642cb06f2f6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1595553431 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.
gpio_stress_all.1595553431
Directory /workspace/28.gpio_stress_all/latest

Test location /workspace/coverage/default/29.gpio_alert_test.1583654081
Short name T26
Test name
Test status
Simulation time 20710390 ps
CPU time 0.55 seconds
Started Jun 30 04:23:49 PM PDT 24
Finished Jun 30 04:23:56 PM PDT 24
Peak memory 195144 kb
Host smart-3ec5904a-e267-49c3-bc53-f2708fd793ca
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1583654081 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_alert_test.1583654081
Directory /workspace/29.gpio_alert_test/latest

Test location /workspace/coverage/default/29.gpio_dout_din_regs_random_rw.1649341693
Short name T339
Test name
Test status
Simulation time 28150066 ps
CPU time 0.61 seconds
Started Jun 30 04:24:13 PM PDT 24
Finished Jun 30 04:24:15 PM PDT 24
Peak memory 194360 kb
Host smart-7e5af7bd-6115-4e80-947b-8bdb8bf930c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1649341693 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_dout_din_regs_random_rw.1649341693
Directory /workspace/29.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/29.gpio_filter_stress.1979843160
Short name T418
Test name
Test status
Simulation time 754579318 ps
CPU time 12.27 seconds
Started Jun 30 04:24:04 PM PDT 24
Finished Jun 30 04:24:20 PM PDT 24
Peak memory 197388 kb
Host smart-ea7cd4cc-a8cc-4a61-8c15-94278f05c246
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1979843160 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_filter_stre
ss.1979843160
Directory /workspace/29.gpio_filter_stress/latest

Test location /workspace/coverage/default/29.gpio_full_random.4169271302
Short name T372
Test name
Test status
Simulation time 303715556 ps
CPU time 0.97 seconds
Started Jun 30 04:23:59 PM PDT 24
Finished Jun 30 04:24:01 PM PDT 24
Peak memory 197176 kb
Host smart-ef02ba00-62f5-46ad-b697-13855f2b81a0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4169271302 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_full_random.4169271302
Directory /workspace/29.gpio_full_random/latest

Test location /workspace/coverage/default/29.gpio_intr_rand_pgm.2524958187
Short name T615
Test name
Test status
Simulation time 352112238 ps
CPU time 1.28 seconds
Started Jun 30 04:23:53 PM PDT 24
Finished Jun 30 04:23:55 PM PDT 24
Peak memory 198484 kb
Host smart-00f9661f-9ea0-4950-b00f-29f7a90b9cc4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2524958187 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_intr_rand_pgm.2524958187
Directory /workspace/29.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/29.gpio_intr_with_filter_rand_intr_event.2779529897
Short name T542
Test name
Test status
Simulation time 93816981 ps
CPU time 3.35 seconds
Started Jun 30 04:24:06 PM PDT 24
Finished Jun 30 04:24:13 PM PDT 24
Peak memory 198444 kb
Host smart-296589ab-51f6-4943-8d49-2128c2b291e8
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2779529897 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 29.gpio_intr_with_filter_rand_intr_event.2779529897
Directory /workspace/29.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/29.gpio_rand_intr_trigger.1840009920
Short name T688
Test name
Test status
Simulation time 655119665 ps
CPU time 1.93 seconds
Started Jun 30 04:23:48 PM PDT 24
Finished Jun 30 04:23:51 PM PDT 24
Peak memory 197660 kb
Host smart-344ec01d-7dfa-4b31-9f7b-b8e8393da4b2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1840009920 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_rand_intr_trigger
.1840009920
Directory /workspace/29.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/29.gpio_random_dout_din.2200238285
Short name T219
Test name
Test status
Simulation time 44558800 ps
CPU time 0.87 seconds
Started Jun 30 04:23:57 PM PDT 24
Finished Jun 30 04:23:59 PM PDT 24
Peak memory 196404 kb
Host smart-fa5651b9-5edb-40b2-9fe7-e7c06b054d2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2200238285 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_random_dout_din.2200238285
Directory /workspace/29.gpio_random_dout_din/latest

Test location /workspace/coverage/default/29.gpio_random_dout_din_no_pullup_pulldown.3340582986
Short name T188
Test name
Test status
Simulation time 112750012 ps
CPU time 1.06 seconds
Started Jun 30 04:24:03 PM PDT 24
Finished Jun 30 04:24:07 PM PDT 24
Peak memory 196320 kb
Host smart-d194bb74-a042-4219-ae08-3a5491ae44dc
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3340582986 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_random_dout_din_no_pullu
p_pulldown.3340582986
Directory /workspace/29.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/29.gpio_random_long_reg_writes_reg_reads.129434360
Short name T4
Test name
Test status
Simulation time 1341730598 ps
CPU time 2.74 seconds
Started Jun 30 04:24:09 PM PDT 24
Finished Jun 30 04:24:15 PM PDT 24
Peak memory 198416 kb
Host smart-33f0d9a4-42be-4405-81b1-bb4e69e62ddd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=129434360 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_ran
dom_long_reg_writes_reg_reads.129434360
Directory /workspace/29.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/29.gpio_smoke.3966002463
Short name T567
Test name
Test status
Simulation time 90307854 ps
CPU time 1.33 seconds
Started Jun 30 04:23:53 PM PDT 24
Finished Jun 30 04:23:56 PM PDT 24
Peak memory 197324 kb
Host smart-395ada9e-d1af-494f-ae11-9240727df684
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3966002463 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_smoke.3966002463
Directory /workspace/29.gpio_smoke/latest

Test location /workspace/coverage/default/29.gpio_smoke_no_pullup_pulldown.2329643620
Short name T651
Test name
Test status
Simulation time 35773925 ps
CPU time 1.14 seconds
Started Jun 30 04:23:58 PM PDT 24
Finished Jun 30 04:24:00 PM PDT 24
Peak memory 197348 kb
Host smart-e6a04774-5521-4107-ad39-429f5a3d32b7
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2329643620 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_smoke_no_pullup_pulldown.2329643620
Directory /workspace/29.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/29.gpio_stress_all.4186330420
Short name T495
Test name
Test status
Simulation time 32754873041 ps
CPU time 205.06 seconds
Started Jun 30 04:23:55 PM PDT 24
Finished Jun 30 04:27:22 PM PDT 24
Peak memory 198704 kb
Host smart-2b268671-91d8-44f0-957d-d8d26e5d4c96
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4186330420 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.
gpio_stress_all.4186330420
Directory /workspace/29.gpio_stress_all/latest

Test location /workspace/coverage/default/3.gpio_alert_test.1030098225
Short name T149
Test name
Test status
Simulation time 35393758 ps
CPU time 0.68 seconds
Started Jun 30 04:17:08 PM PDT 24
Finished Jun 30 04:17:09 PM PDT 24
Peak memory 193648 kb
Host smart-0bca0063-d490-44c1-b522-c6dbcd11ef45
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1030098225 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_alert_test.1030098225
Directory /workspace/3.gpio_alert_test/latest

Test location /workspace/coverage/default/3.gpio_dout_din_regs_random_rw.1788447978
Short name T181
Test name
Test status
Simulation time 226386529 ps
CPU time 0.73 seconds
Started Jun 30 04:20:46 PM PDT 24
Finished Jun 30 04:20:48 PM PDT 24
Peak memory 195732 kb
Host smart-71d2db48-aa9d-4504-83bf-a11e2479d247
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1788447978 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_dout_din_regs_random_rw.1788447978
Directory /workspace/3.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/3.gpio_filter_stress.101109701
Short name T397
Test name
Test status
Simulation time 2129338500 ps
CPU time 18.19 seconds
Started Jun 30 04:22:56 PM PDT 24
Finished Jun 30 04:23:17 PM PDT 24
Peak memory 197280 kb
Host smart-70cb12dc-7672-41c7-a8b7-f5374893b5a3
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=101109701 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_filter_stress
.101109701
Directory /workspace/3.gpio_filter_stress/latest

Test location /workspace/coverage/default/3.gpio_full_random.804439532
Short name T8
Test name
Test status
Simulation time 37675744 ps
CPU time 0.73 seconds
Started Jun 30 04:22:42 PM PDT 24
Finished Jun 30 04:22:46 PM PDT 24
Peak memory 194940 kb
Host smart-6a103cea-4601-472f-9e99-b619bb580b5d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=804439532 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_full_random.804439532
Directory /workspace/3.gpio_full_random/latest

Test location /workspace/coverage/default/3.gpio_intr_rand_pgm.3710031768
Short name T706
Test name
Test status
Simulation time 277915763 ps
CPU time 1.02 seconds
Started Jun 30 04:22:19 PM PDT 24
Finished Jun 30 04:22:21 PM PDT 24
Peak memory 196364 kb
Host smart-df73047e-7e33-4efd-82cf-37a42686571e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3710031768 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_intr_rand_pgm.3710031768
Directory /workspace/3.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/3.gpio_intr_with_filter_rand_intr_event.3490578412
Short name T263
Test name
Test status
Simulation time 72586658 ps
CPU time 0.9 seconds
Started Jun 30 04:22:06 PM PDT 24
Finished Jun 30 04:22:09 PM PDT 24
Peak memory 196656 kb
Host smart-5bee2733-14fa-4962-87df-21a55b2b0e58
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3490578412 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 3.gpio_intr_with_filter_rand_intr_event.3490578412
Directory /workspace/3.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/3.gpio_rand_intr_trigger.31728137
Short name T315
Test name
Test status
Simulation time 136649506 ps
CPU time 2.69 seconds
Started Jun 30 04:22:13 PM PDT 24
Finished Jun 30 04:22:16 PM PDT 24
Peak memory 196988 kb
Host smart-c6550cf7-7928-41ab-b467-8d8b1e805363
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31728137 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigger
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_rand_intr_trigger.31728137
Directory /workspace/3.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/3.gpio_random_dout_din.1604147858
Short name T119
Test name
Test status
Simulation time 50755531 ps
CPU time 0.66 seconds
Started Jun 30 04:22:13 PM PDT 24
Finished Jun 30 04:22:14 PM PDT 24
Peak memory 195760 kb
Host smart-fdd38587-2fe8-491f-b693-aa12ab2bf407
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1604147858 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_random_dout_din.1604147858
Directory /workspace/3.gpio_random_dout_din/latest

Test location /workspace/coverage/default/3.gpio_random_dout_din_no_pullup_pulldown.3145587935
Short name T384
Test name
Test status
Simulation time 22235778 ps
CPU time 0.7 seconds
Started Jun 30 04:22:18 PM PDT 24
Finished Jun 30 04:22:20 PM PDT 24
Peak memory 196272 kb
Host smart-f7e7be36-2100-42e5-aba9-426c4c85dff7
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3145587935 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_random_dout_din_no_pullup
_pulldown.3145587935
Directory /workspace/3.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/3.gpio_random_long_reg_writes_reg_reads.4241760839
Short name T116
Test name
Test status
Simulation time 109057693 ps
CPU time 4.76 seconds
Started Jun 30 04:22:50 PM PDT 24
Finished Jun 30 04:22:56 PM PDT 24
Peak memory 198544 kb
Host smart-f2715393-980c-495a-b59a-552c0b03e295
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4241760839 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_ran
dom_long_reg_writes_reg_reads.4241760839
Directory /workspace/3.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/3.gpio_sec_cm.315221548
Short name T50
Test name
Test status
Simulation time 857929778 ps
CPU time 0.87 seconds
Started Jun 30 04:22:49 PM PDT 24
Finished Jun 30 04:22:52 PM PDT 24
Peak memory 214068 kb
Host smart-c71beae1-1ce2-44ef-b52c-477ea24270bc
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=315221548 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_sec_cm.315221548
Directory /workspace/3.gpio_sec_cm/latest

Test location /workspace/coverage/default/3.gpio_smoke.2954747795
Short name T686
Test name
Test status
Simulation time 46202218 ps
CPU time 0.92 seconds
Started Jun 30 04:22:50 PM PDT 24
Finished Jun 30 04:22:52 PM PDT 24
Peak memory 196120 kb
Host smart-0b3b2cc2-35c0-45f0-a2aa-8794d5ba2e84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2954747795 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_smoke.2954747795
Directory /workspace/3.gpio_smoke/latest

Test location /workspace/coverage/default/3.gpio_smoke_no_pullup_pulldown.2914285291
Short name T128
Test name
Test status
Simulation time 67258925 ps
CPU time 1.25 seconds
Started Jun 30 04:22:41 PM PDT 24
Finished Jun 30 04:22:45 PM PDT 24
Peak memory 198440 kb
Host smart-360142a8-4eb1-4887-99a7-57b370c9dd04
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2914285291 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_smoke_no_pullup_pulldown.2914285291
Directory /workspace/3.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/3.gpio_stress_all.968565551
Short name T194
Test name
Test status
Simulation time 9217680056 ps
CPU time 124.54 seconds
Started Jun 30 04:21:54 PM PDT 24
Finished Jun 30 04:24:01 PM PDT 24
Peak memory 197500 kb
Host smart-f5734b5c-3866-4a3e-a09e-29f338332e3a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=968565551 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gp
io_stress_all.968565551
Directory /workspace/3.gpio_stress_all/latest

Test location /workspace/coverage/default/3.gpio_stress_all_with_rand_reset.3334128080
Short name T102
Test name
Test status
Simulation time 412097108055 ps
CPU time 1937.39 seconds
Started Jun 30 04:17:52 PM PDT 24
Finished Jun 30 04:50:10 PM PDT 24
Peak memory 198696 kb
Host smart-2c776095-c660-45bb-8b20-423dc046428c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3334128080 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_stress_all_with_rand_reset.3334128080
Directory /workspace/3.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.gpio_alert_test.2251828681
Short name T396
Test name
Test status
Simulation time 13850364 ps
CPU time 0.55 seconds
Started Jun 30 04:24:03 PM PDT 24
Finished Jun 30 04:24:07 PM PDT 24
Peak memory 194448 kb
Host smart-ba7c7807-a86b-4c88-9ffa-62726fc81a1b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2251828681 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_alert_test.2251828681
Directory /workspace/30.gpio_alert_test/latest

Test location /workspace/coverage/default/30.gpio_dout_din_regs_random_rw.3530721237
Short name T380
Test name
Test status
Simulation time 208348809 ps
CPU time 0.75 seconds
Started Jun 30 04:23:57 PM PDT 24
Finished Jun 30 04:23:59 PM PDT 24
Peak memory 195784 kb
Host smart-3b3a43fb-bb38-4d06-8c2e-eb35ca58dd0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3530721237 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_dout_din_regs_random_rw.3530721237
Directory /workspace/30.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/30.gpio_filter_stress.2003588998
Short name T394
Test name
Test status
Simulation time 509425314 ps
CPU time 5.54 seconds
Started Jun 30 04:23:52 PM PDT 24
Finished Jun 30 04:23:59 PM PDT 24
Peak memory 196020 kb
Host smart-cb6822fa-e8cf-45d0-afea-1a0c6148d9dd
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2003588998 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_filter_stre
ss.2003588998
Directory /workspace/30.gpio_filter_stress/latest

Test location /workspace/coverage/default/30.gpio_full_random.2418652322
Short name T7
Test name
Test status
Simulation time 401168273 ps
CPU time 1.01 seconds
Started Jun 30 04:23:53 PM PDT 24
Finished Jun 30 04:23:55 PM PDT 24
Peak memory 197088 kb
Host smart-9b3bae6a-fcae-432e-b2ef-684ec2c79b9d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2418652322 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_full_random.2418652322
Directory /workspace/30.gpio_full_random/latest

Test location /workspace/coverage/default/30.gpio_intr_rand_pgm.1597678823
Short name T206
Test name
Test status
Simulation time 49061716 ps
CPU time 1.24 seconds
Started Jun 30 04:23:59 PM PDT 24
Finished Jun 30 04:24:02 PM PDT 24
Peak memory 197680 kb
Host smart-e4fb96ec-8939-4292-8264-c6fa74a5ef25
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1597678823 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_intr_rand_pgm.1597678823
Directory /workspace/30.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/30.gpio_intr_with_filter_rand_intr_event.1090782234
Short name T234
Test name
Test status
Simulation time 35671206 ps
CPU time 1.38 seconds
Started Jun 30 04:23:50 PM PDT 24
Finished Jun 30 04:23:53 PM PDT 24
Peak memory 197040 kb
Host smart-08d6614a-70f3-4ced-b2a0-46e53c1d7125
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1090782234 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 30.gpio_intr_with_filter_rand_intr_event.1090782234
Directory /workspace/30.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/30.gpio_rand_intr_trigger.3525511340
Short name T493
Test name
Test status
Simulation time 157736693 ps
CPU time 1.36 seconds
Started Jun 30 04:24:00 PM PDT 24
Finished Jun 30 04:24:03 PM PDT 24
Peak memory 196744 kb
Host smart-9b6b717b-c07b-4219-b6b8-9ce76b009f96
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3525511340 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_rand_intr_trigger
.3525511340
Directory /workspace/30.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/30.gpio_random_dout_din.1510008348
Short name T554
Test name
Test status
Simulation time 140522924 ps
CPU time 1.23 seconds
Started Jun 30 04:24:00 PM PDT 24
Finished Jun 30 04:24:03 PM PDT 24
Peak memory 196300 kb
Host smart-b48f6098-ab93-49a9-939a-5e8b15792b7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1510008348 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_random_dout_din.1510008348
Directory /workspace/30.gpio_random_dout_din/latest

Test location /workspace/coverage/default/30.gpio_random_dout_din_no_pullup_pulldown.1259177554
Short name T163
Test name
Test status
Simulation time 18846898 ps
CPU time 0.72 seconds
Started Jun 30 04:23:58 PM PDT 24
Finished Jun 30 04:24:00 PM PDT 24
Peak memory 195844 kb
Host smart-301ca2fa-bc2c-451c-8a05-b2c9cc7f1a0e
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1259177554 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_random_dout_din_no_pullu
p_pulldown.1259177554
Directory /workspace/30.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/30.gpio_random_long_reg_writes_reg_reads.441028295
Short name T417
Test name
Test status
Simulation time 111713930 ps
CPU time 4.61 seconds
Started Jun 30 04:23:40 PM PDT 24
Finished Jun 30 04:23:45 PM PDT 24
Peak memory 198348 kb
Host smart-8cdc7d68-ef63-4411-b5d5-f13fbddfbffd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=441028295 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_ran
dom_long_reg_writes_reg_reads.441028295
Directory /workspace/30.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/30.gpio_smoke.2026095170
Short name T426
Test name
Test status
Simulation time 56687886 ps
CPU time 1.05 seconds
Started Jun 30 04:23:52 PM PDT 24
Finished Jun 30 04:23:54 PM PDT 24
Peak memory 196224 kb
Host smart-ac5059b9-d0f2-4dee-b865-68515e52a8a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2026095170 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_smoke.2026095170
Directory /workspace/30.gpio_smoke/latest

Test location /workspace/coverage/default/30.gpio_smoke_no_pullup_pulldown.3403295045
Short name T322
Test name
Test status
Simulation time 44089101 ps
CPU time 1.25 seconds
Started Jun 30 04:23:52 PM PDT 24
Finished Jun 30 04:23:54 PM PDT 24
Peak memory 196932 kb
Host smart-771c49f6-622b-4749-8119-9873aaee128d
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3403295045 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_smoke_no_pullup_pulldown.3403295045
Directory /workspace/30.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/30.gpio_stress_all.2810925440
Short name T604
Test name
Test status
Simulation time 9422042587 ps
CPU time 21.64 seconds
Started Jun 30 04:24:05 PM PDT 24
Finished Jun 30 04:24:30 PM PDT 24
Peak memory 198612 kb
Host smart-f97e5c59-3bc4-4f17-99ec-7d3f2b8c4689
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2810925440 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.
gpio_stress_all.2810925440
Directory /workspace/30.gpio_stress_all/latest

Test location /workspace/coverage/default/30.gpio_stress_all_with_rand_reset.1606965426
Short name T556
Test name
Test status
Simulation time 67180260972 ps
CPU time 1466.57 seconds
Started Jun 30 04:24:06 PM PDT 24
Finished Jun 30 04:48:40 PM PDT 24
Peak memory 198744 kb
Host smart-3f8ab442-55d4-489f-adce-4848a384cc8f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1606965426 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_stress_all_with_rand_reset.1606965426
Directory /workspace/30.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.gpio_alert_test.42180631
Short name T214
Test name
Test status
Simulation time 10907376 ps
CPU time 0.55 seconds
Started Jun 30 04:24:00 PM PDT 24
Finished Jun 30 04:24:02 PM PDT 24
Peak memory 194488 kb
Host smart-51caab83-b92c-4a68-b0a9-ea436007cf95
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42180631 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_alert_test.42180631
Directory /workspace/31.gpio_alert_test/latest

Test location /workspace/coverage/default/31.gpio_dout_din_regs_random_rw.2648276653
Short name T227
Test name
Test status
Simulation time 36288625 ps
CPU time 0.73 seconds
Started Jun 30 04:23:58 PM PDT 24
Finished Jun 30 04:24:00 PM PDT 24
Peak memory 195812 kb
Host smart-156218ad-ba66-47ab-ba34-394e0c5a714f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2648276653 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_dout_din_regs_random_rw.2648276653
Directory /workspace/31.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/31.gpio_filter_stress.2012278698
Short name T273
Test name
Test status
Simulation time 1738816908 ps
CPU time 23.77 seconds
Started Jun 30 04:24:08 PM PDT 24
Finished Jun 30 04:24:35 PM PDT 24
Peak memory 198396 kb
Host smart-de83b074-6b65-4abf-80de-aecd25d4abe8
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2012278698 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_filter_stre
ss.2012278698
Directory /workspace/31.gpio_filter_stress/latest

Test location /workspace/coverage/default/31.gpio_full_random.396454986
Short name T557
Test name
Test status
Simulation time 44705630 ps
CPU time 0.84 seconds
Started Jun 30 04:23:59 PM PDT 24
Finished Jun 30 04:24:02 PM PDT 24
Peak memory 197152 kb
Host smart-016dc901-d9c9-4b78-a776-4605ad438b32
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=396454986 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_full_random.396454986
Directory /workspace/31.gpio_full_random/latest

Test location /workspace/coverage/default/31.gpio_intr_rand_pgm.2721614362
Short name T112
Test name
Test status
Simulation time 77667831 ps
CPU time 0.99 seconds
Started Jun 30 04:23:57 PM PDT 24
Finished Jun 30 04:23:59 PM PDT 24
Peak memory 196608 kb
Host smart-a640c8ee-f2ed-4b44-b8ee-bf35cf059b87
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2721614362 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_intr_rand_pgm.2721614362
Directory /workspace/31.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/31.gpio_intr_with_filter_rand_intr_event.3833715053
Short name T365
Test name
Test status
Simulation time 20514742 ps
CPU time 0.89 seconds
Started Jun 30 04:24:01 PM PDT 24
Finished Jun 30 04:24:04 PM PDT 24
Peak memory 197328 kb
Host smart-acb8387e-a414-41cc-a777-a15329d2c4b3
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3833715053 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 31.gpio_intr_with_filter_rand_intr_event.3833715053
Directory /workspace/31.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/31.gpio_rand_intr_trigger.2307284038
Short name T168
Test name
Test status
Simulation time 148928513 ps
CPU time 0.98 seconds
Started Jun 30 04:23:59 PM PDT 24
Finished Jun 30 04:24:01 PM PDT 24
Peak memory 196556 kb
Host smart-19e55b99-968f-4a30-8c8d-9455ac18e710
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2307284038 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_rand_intr_trigger
.2307284038
Directory /workspace/31.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/31.gpio_random_dout_din.924937342
Short name T269
Test name
Test status
Simulation time 173258395 ps
CPU time 1.11 seconds
Started Jun 30 04:23:53 PM PDT 24
Finished Jun 30 04:23:55 PM PDT 24
Peak memory 197292 kb
Host smart-380ff82c-3ff3-4a28-b528-376189958ac2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=924937342 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_random_dout_din.924937342
Directory /workspace/31.gpio_random_dout_din/latest

Test location /workspace/coverage/default/31.gpio_random_dout_din_no_pullup_pulldown.3192074289
Short name T563
Test name
Test status
Simulation time 245968329 ps
CPU time 1.22 seconds
Started Jun 30 04:23:59 PM PDT 24
Finished Jun 30 04:24:01 PM PDT 24
Peak memory 197480 kb
Host smart-12f5f451-0ee8-41f4-95ef-86bb34a78a17
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3192074289 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_random_dout_din_no_pullu
p_pulldown.3192074289
Directory /workspace/31.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/31.gpio_random_long_reg_writes_reg_reads.4103756657
Short name T304
Test name
Test status
Simulation time 191494700 ps
CPU time 2.24 seconds
Started Jun 30 04:23:51 PM PDT 24
Finished Jun 30 04:23:55 PM PDT 24
Peak memory 198432 kb
Host smart-fdcac623-b657-40ad-8f50-9a154167c43c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4103756657 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_ra
ndom_long_reg_writes_reg_reads.4103756657
Directory /workspace/31.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/31.gpio_smoke.82293178
Short name T432
Test name
Test status
Simulation time 45829118 ps
CPU time 0.93 seconds
Started Jun 30 04:23:58 PM PDT 24
Finished Jun 30 04:24:00 PM PDT 24
Peak memory 196296 kb
Host smart-9d079e5e-b746-4b94-b6b6-4f86afd8d6f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=82293178 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_smoke.82293178
Directory /workspace/31.gpio_smoke/latest

Test location /workspace/coverage/default/31.gpio_smoke_no_pullup_pulldown.672178899
Short name T714
Test name
Test status
Simulation time 93394843 ps
CPU time 1.31 seconds
Started Jun 30 04:24:02 PM PDT 24
Finished Jun 30 04:24:06 PM PDT 24
Peak memory 196836 kb
Host smart-ef88d76b-d353-4eca-8b08-54315b64d64c
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=672178899 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_smoke_no_pullup_pulldown.672178899
Directory /workspace/31.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/31.gpio_stress_all.4270151375
Short name T246
Test name
Test status
Simulation time 16867270462 ps
CPU time 116.57 seconds
Started Jun 30 04:24:03 PM PDT 24
Finished Jun 30 04:26:03 PM PDT 24
Peak memory 198652 kb
Host smart-6cd8885f-4401-4045-8557-5c65f59f79f1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4270151375 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.
gpio_stress_all.4270151375
Directory /workspace/31.gpio_stress_all/latest

Test location /workspace/coverage/default/31.gpio_stress_all_with_rand_reset.2687096410
Short name T705
Test name
Test status
Simulation time 131077186841 ps
CPU time 716.45 seconds
Started Jun 30 04:24:00 PM PDT 24
Finished Jun 30 04:35:58 PM PDT 24
Peak memory 198700 kb
Host smart-2a2967a7-3085-443f-a115-e964d7b7b896
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2687096410 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_stress_all_with_rand_reset.2687096410
Directory /workspace/31.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.gpio_alert_test.2869583178
Short name T351
Test name
Test status
Simulation time 137777064 ps
CPU time 0.56 seconds
Started Jun 30 04:24:01 PM PDT 24
Finished Jun 30 04:24:05 PM PDT 24
Peak memory 194440 kb
Host smart-eb6e7c60-e1dd-404a-bfaa-5652ed5f2adb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2869583178 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_alert_test.2869583178
Directory /workspace/32.gpio_alert_test/latest

Test location /workspace/coverage/default/32.gpio_dout_din_regs_random_rw.285866553
Short name T526
Test name
Test status
Simulation time 25287271 ps
CPU time 0.83 seconds
Started Jun 30 04:23:55 PM PDT 24
Finished Jun 30 04:23:57 PM PDT 24
Peak memory 196976 kb
Host smart-7f5bdf23-42fb-4833-8892-57f25611b4c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=285866553 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_dout_din_regs_random_rw.285866553
Directory /workspace/32.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/32.gpio_filter_stress.3982065799
Short name T317
Test name
Test status
Simulation time 107074414 ps
CPU time 5.21 seconds
Started Jun 30 04:24:07 PM PDT 24
Finished Jun 30 04:24:16 PM PDT 24
Peak memory 198412 kb
Host smart-9f9070a7-7b89-494a-89c4-469ad9b95b72
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3982065799 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_filter_stre
ss.3982065799
Directory /workspace/32.gpio_filter_stress/latest

Test location /workspace/coverage/default/32.gpio_full_random.2275994213
Short name T416
Test name
Test status
Simulation time 301551787 ps
CPU time 1 seconds
Started Jun 30 04:24:04 PM PDT 24
Finished Jun 30 04:24:08 PM PDT 24
Peak memory 196992 kb
Host smart-5c7e87ec-3b9a-4134-91da-f4e4518b4067
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2275994213 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_full_random.2275994213
Directory /workspace/32.gpio_full_random/latest

Test location /workspace/coverage/default/32.gpio_intr_rand_pgm.2085652047
Short name T406
Test name
Test status
Simulation time 23462705 ps
CPU time 0.72 seconds
Started Jun 30 04:24:14 PM PDT 24
Finished Jun 30 04:24:17 PM PDT 24
Peak memory 195828 kb
Host smart-4c477dcb-98eb-4cf3-8b82-ad887723c2b4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2085652047 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_intr_rand_pgm.2085652047
Directory /workspace/32.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/32.gpio_intr_with_filter_rand_intr_event.1465630042
Short name T516
Test name
Test status
Simulation time 30150968 ps
CPU time 1.32 seconds
Started Jun 30 04:24:00 PM PDT 24
Finished Jun 30 04:24:03 PM PDT 24
Peak memory 198520 kb
Host smart-ead21c08-835e-4dcf-a5ba-53909b543061
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1465630042 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 32.gpio_intr_with_filter_rand_intr_event.1465630042
Directory /workspace/32.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/32.gpio_rand_intr_trigger.2993668513
Short name T388
Test name
Test status
Simulation time 613391958 ps
CPU time 3.23 seconds
Started Jun 30 04:24:00 PM PDT 24
Finished Jun 30 04:24:06 PM PDT 24
Peak memory 198664 kb
Host smart-88ce56c3-4cf7-4cba-85de-2d98c24a77f3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2993668513 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_rand_intr_trigger
.2993668513
Directory /workspace/32.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/32.gpio_random_dout_din.1414921716
Short name T187
Test name
Test status
Simulation time 74746886 ps
CPU time 0.82 seconds
Started Jun 30 04:23:47 PM PDT 24
Finished Jun 30 04:23:49 PM PDT 24
Peak memory 196508 kb
Host smart-a23ecbba-de23-4fc0-9f9d-60f579982ccb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1414921716 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_random_dout_din.1414921716
Directory /workspace/32.gpio_random_dout_din/latest

Test location /workspace/coverage/default/32.gpio_random_dout_din_no_pullup_pulldown.1175481799
Short name T699
Test name
Test status
Simulation time 73049447 ps
CPU time 0.88 seconds
Started Jun 30 04:24:08 PM PDT 24
Finished Jun 30 04:24:12 PM PDT 24
Peak memory 196464 kb
Host smart-6e117873-5b8e-4a53-81b7-037b909ca6b8
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1175481799 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_random_dout_din_no_pullu
p_pulldown.1175481799
Directory /workspace/32.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/32.gpio_random_long_reg_writes_reg_reads.1116989185
Short name T437
Test name
Test status
Simulation time 60105187 ps
CPU time 2.45 seconds
Started Jun 30 04:24:01 PM PDT 24
Finished Jun 30 04:24:06 PM PDT 24
Peak memory 198460 kb
Host smart-f3c69ea1-0f35-40b1-85ed-f7954d8b7ebb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1116989185 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_ra
ndom_long_reg_writes_reg_reads.1116989185
Directory /workspace/32.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/32.gpio_smoke.449660386
Short name T347
Test name
Test status
Simulation time 275330701 ps
CPU time 1.22 seconds
Started Jun 30 04:24:00 PM PDT 24
Finished Jun 30 04:24:04 PM PDT 24
Peak memory 196364 kb
Host smart-75d3d07b-7c24-4db8-ba69-e873b699916a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=449660386 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_smoke.449660386
Directory /workspace/32.gpio_smoke/latest

Test location /workspace/coverage/default/32.gpio_smoke_no_pullup_pulldown.1707808922
Short name T630
Test name
Test status
Simulation time 165242753 ps
CPU time 1.01 seconds
Started Jun 30 04:24:03 PM PDT 24
Finished Jun 30 04:24:07 PM PDT 24
Peak memory 197416 kb
Host smart-bc23ac19-af9f-4093-821a-83a858da6937
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1707808922 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_smoke_no_pullup_pulldown.1707808922
Directory /workspace/32.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/32.gpio_stress_all.726793354
Short name T470
Test name
Test status
Simulation time 2542656147 ps
CPU time 57.4 seconds
Started Jun 30 04:24:05 PM PDT 24
Finished Jun 30 04:25:05 PM PDT 24
Peak memory 198584 kb
Host smart-0fa25232-2491-44be-ad88-1fc280375308
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=726793354 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.g
pio_stress_all.726793354
Directory /workspace/32.gpio_stress_all/latest

Test location /workspace/coverage/default/33.gpio_alert_test.1096814445
Short name T258
Test name
Test status
Simulation time 58022876 ps
CPU time 0.56 seconds
Started Jun 30 04:24:04 PM PDT 24
Finished Jun 30 04:24:07 PM PDT 24
Peak memory 194624 kb
Host smart-7c581070-2805-4915-9e1f-31721f88d450
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1096814445 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_alert_test.1096814445
Directory /workspace/33.gpio_alert_test/latest

Test location /workspace/coverage/default/33.gpio_dout_din_regs_random_rw.4185738133
Short name T165
Test name
Test status
Simulation time 43485359 ps
CPU time 0.74 seconds
Started Jun 30 04:23:52 PM PDT 24
Finished Jun 30 04:23:54 PM PDT 24
Peak memory 196564 kb
Host smart-5ce4a93c-6d82-4141-ac5f-5c51acf8b3dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4185738133 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_dout_din_regs_random_rw.4185738133
Directory /workspace/33.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/33.gpio_filter_stress.354432466
Short name T538
Test name
Test status
Simulation time 368930100 ps
CPU time 9.11 seconds
Started Jun 30 04:23:59 PM PDT 24
Finished Jun 30 04:24:09 PM PDT 24
Peak memory 197292 kb
Host smart-b6b1cee2-c2b0-4592-b254-16aeeb768278
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=354432466 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_filter_stres
s.354432466
Directory /workspace/33.gpio_filter_stress/latest

Test location /workspace/coverage/default/33.gpio_full_random.2787979721
Short name T66
Test name
Test status
Simulation time 393932478 ps
CPU time 0.99 seconds
Started Jun 30 04:24:03 PM PDT 24
Finished Jun 30 04:24:07 PM PDT 24
Peak memory 196832 kb
Host smart-b955bbb8-de81-439f-ae97-796b1ff848cf
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2787979721 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_full_random.2787979721
Directory /workspace/33.gpio_full_random/latest

Test location /workspace/coverage/default/33.gpio_intr_rand_pgm.3046040556
Short name T100
Test name
Test status
Simulation time 83305818 ps
CPU time 0.88 seconds
Started Jun 30 04:24:08 PM PDT 24
Finished Jun 30 04:24:12 PM PDT 24
Peak memory 196324 kb
Host smart-4fbf8ef9-df21-40e8-b1d6-2f2982e2a3c3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3046040556 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_intr_rand_pgm.3046040556
Directory /workspace/33.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/33.gpio_intr_with_filter_rand_intr_event.3715946360
Short name T95
Test name
Test status
Simulation time 51006235 ps
CPU time 1.18 seconds
Started Jun 30 04:24:10 PM PDT 24
Finished Jun 30 04:24:14 PM PDT 24
Peak memory 197116 kb
Host smart-467d08d5-5019-4afe-b43d-4ff090e1fad8
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3715946360 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 33.gpio_intr_with_filter_rand_intr_event.3715946360
Directory /workspace/33.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/33.gpio_rand_intr_trigger.2699556586
Short name T296
Test name
Test status
Simulation time 278500594 ps
CPU time 2.94 seconds
Started Jun 30 04:24:03 PM PDT 24
Finished Jun 30 04:24:09 PM PDT 24
Peak memory 197444 kb
Host smart-c224bb15-8e5b-48ae-a8c2-994bb408b0b9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2699556586 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_rand_intr_trigger
.2699556586
Directory /workspace/33.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/33.gpio_random_dout_din.1384309243
Short name T683
Test name
Test status
Simulation time 23516064 ps
CPU time 0.94 seconds
Started Jun 30 04:24:07 PM PDT 24
Finished Jun 30 04:24:11 PM PDT 24
Peak memory 196320 kb
Host smart-a92306ed-e22d-4009-91ef-2de65267d5df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1384309243 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_random_dout_din.1384309243
Directory /workspace/33.gpio_random_dout_din/latest

Test location /workspace/coverage/default/33.gpio_random_dout_din_no_pullup_pulldown.1232230765
Short name T201
Test name
Test status
Simulation time 47664330 ps
CPU time 0.71 seconds
Started Jun 30 04:24:12 PM PDT 24
Finished Jun 30 04:24:15 PM PDT 24
Peak memory 196472 kb
Host smart-d7cb9070-49d4-48b1-98cb-ad4382a23316
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1232230765 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_random_dout_din_no_pullu
p_pulldown.1232230765
Directory /workspace/33.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/33.gpio_random_long_reg_writes_reg_reads.2371465390
Short name T447
Test name
Test status
Simulation time 1532985520 ps
CPU time 6.84 seconds
Started Jun 30 04:24:07 PM PDT 24
Finished Jun 30 04:24:17 PM PDT 24
Peak memory 198396 kb
Host smart-506f8a3a-e908-401d-99fe-562b39f8e572
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2371465390 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_ra
ndom_long_reg_writes_reg_reads.2371465390
Directory /workspace/33.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/33.gpio_smoke.946356163
Short name T174
Test name
Test status
Simulation time 26833462 ps
CPU time 0.75 seconds
Started Jun 30 04:23:53 PM PDT 24
Finished Jun 30 04:23:54 PM PDT 24
Peak memory 195652 kb
Host smart-bf92959a-fd55-4595-a135-b39955b2f0c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=946356163 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_smoke.946356163
Directory /workspace/33.gpio_smoke/latest

Test location /workspace/coverage/default/33.gpio_smoke_no_pullup_pulldown.275476164
Short name T634
Test name
Test status
Simulation time 45005814 ps
CPU time 1.3 seconds
Started Jun 30 04:23:58 PM PDT 24
Finished Jun 30 04:24:00 PM PDT 24
Peak memory 197172 kb
Host smart-5615f7ce-f025-40f0-b320-ddcc368fea04
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=275476164 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_smoke_no_pullup_pulldown.275476164
Directory /workspace/33.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/33.gpio_stress_all.880915158
Short name T642
Test name
Test status
Simulation time 70291574745 ps
CPU time 186.78 seconds
Started Jun 30 04:24:05 PM PDT 24
Finished Jun 30 04:27:16 PM PDT 24
Peak memory 198580 kb
Host smart-7e1a958e-6748-452c-a8d4-5f74dbeeed0c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=880915158 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.g
pio_stress_all.880915158
Directory /workspace/33.gpio_stress_all/latest

Test location /workspace/coverage/default/34.gpio_alert_test.2513165952
Short name T487
Test name
Test status
Simulation time 17037227 ps
CPU time 0.56 seconds
Started Jun 30 04:23:46 PM PDT 24
Finished Jun 30 04:23:48 PM PDT 24
Peak memory 195140 kb
Host smart-f7b51125-55c4-4ec0-bd04-e8bc2a3587f9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2513165952 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_alert_test.2513165952
Directory /workspace/34.gpio_alert_test/latest

Test location /workspace/coverage/default/34.gpio_dout_din_regs_random_rw.1215297922
Short name T590
Test name
Test status
Simulation time 19588438 ps
CPU time 0.65 seconds
Started Jun 30 04:24:06 PM PDT 24
Finished Jun 30 04:24:10 PM PDT 24
Peak memory 195216 kb
Host smart-e1e4ab72-8157-4d9f-8815-75b13dcbf0c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1215297922 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_dout_din_regs_random_rw.1215297922
Directory /workspace/34.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/34.gpio_filter_stress.2974541623
Short name T11
Test name
Test status
Simulation time 105798444 ps
CPU time 5.48 seconds
Started Jun 30 04:24:04 PM PDT 24
Finished Jun 30 04:24:13 PM PDT 24
Peak memory 197552 kb
Host smart-9eeb1095-b008-45b8-a1b9-68747c3a947f
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2974541623 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_filter_stre
ss.2974541623
Directory /workspace/34.gpio_filter_stress/latest

Test location /workspace/coverage/default/34.gpio_full_random.1716677123
Short name T247
Test name
Test status
Simulation time 490804941 ps
CPU time 0.75 seconds
Started Jun 30 04:23:52 PM PDT 24
Finished Jun 30 04:23:54 PM PDT 24
Peak memory 196400 kb
Host smart-1e101c85-0a2a-414b-a30c-72c204046e0a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1716677123 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_full_random.1716677123
Directory /workspace/34.gpio_full_random/latest

Test location /workspace/coverage/default/34.gpio_intr_rand_pgm.1963162399
Short name T321
Test name
Test status
Simulation time 43370129 ps
CPU time 1.08 seconds
Started Jun 30 04:23:54 PM PDT 24
Finished Jun 30 04:23:56 PM PDT 24
Peak memory 196256 kb
Host smart-b95a3ed7-e60a-4408-bd8d-d5757f26daa0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1963162399 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_intr_rand_pgm.1963162399
Directory /workspace/34.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/34.gpio_intr_with_filter_rand_intr_event.203649171
Short name T51
Test name
Test status
Simulation time 67981648 ps
CPU time 2.48 seconds
Started Jun 30 04:24:12 PM PDT 24
Finished Jun 30 04:24:17 PM PDT 24
Peak memory 198456 kb
Host smart-c993fac8-6ff8-465c-8ab1-21b3b661da77
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=203649171 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 34.gpio_intr_with_filter_rand_intr_event.203649171
Directory /workspace/34.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/34.gpio_rand_intr_trigger.575503329
Short name T316
Test name
Test status
Simulation time 37049062 ps
CPU time 1.18 seconds
Started Jun 30 04:24:00 PM PDT 24
Finished Jun 30 04:24:03 PM PDT 24
Peak memory 197104 kb
Host smart-6ed3f279-a6a0-4cc9-9050-38fd47e3b109
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=575503329 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_rand_intr_trigger.
575503329
Directory /workspace/34.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/34.gpio_random_dout_din.2778943166
Short name T445
Test name
Test status
Simulation time 59338065 ps
CPU time 0.74 seconds
Started Jun 30 04:23:56 PM PDT 24
Finished Jun 30 04:23:58 PM PDT 24
Peak memory 196592 kb
Host smart-9a213ef8-8b01-4b76-901b-16ffaafc1157
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2778943166 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_random_dout_din.2778943166
Directory /workspace/34.gpio_random_dout_din/latest

Test location /workspace/coverage/default/34.gpio_random_dout_din_no_pullup_pulldown.1041068102
Short name T471
Test name
Test status
Simulation time 117156611 ps
CPU time 1.07 seconds
Started Jun 30 04:23:47 PM PDT 24
Finished Jun 30 04:23:48 PM PDT 24
Peak memory 198496 kb
Host smart-168d19b2-556e-42d7-b3c1-34d082036422
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1041068102 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_random_dout_din_no_pullu
p_pulldown.1041068102
Directory /workspace/34.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/34.gpio_random_long_reg_writes_reg_reads.1075884921
Short name T213
Test name
Test status
Simulation time 172588671 ps
CPU time 2.97 seconds
Started Jun 30 04:24:08 PM PDT 24
Finished Jun 30 04:24:15 PM PDT 24
Peak memory 198412 kb
Host smart-c5a79dd7-82ac-4f5f-8f86-bab72444fddc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1075884921 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_ra
ndom_long_reg_writes_reg_reads.1075884921
Directory /workspace/34.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/34.gpio_smoke.4167148166
Short name T602
Test name
Test status
Simulation time 259759640 ps
CPU time 1.15 seconds
Started Jun 30 04:24:00 PM PDT 24
Finished Jun 30 04:24:03 PM PDT 24
Peak memory 196020 kb
Host smart-7cbe17ea-23d1-487c-b7b4-e56028e9e02c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4167148166 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_smoke.4167148166
Directory /workspace/34.gpio_smoke/latest

Test location /workspace/coverage/default/34.gpio_smoke_no_pullup_pulldown.3347302019
Short name T690
Test name
Test status
Simulation time 161775428 ps
CPU time 0.98 seconds
Started Jun 30 04:23:55 PM PDT 24
Finished Jun 30 04:23:57 PM PDT 24
Peak memory 195984 kb
Host smart-54814016-084a-4603-b969-d73d943aa911
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3347302019 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_smoke_no_pullup_pulldown.3347302019
Directory /workspace/34.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/34.gpio_stress_all.2145938734
Short name T144
Test name
Test status
Simulation time 23002801714 ps
CPU time 137.69 seconds
Started Jun 30 04:23:58 PM PDT 24
Finished Jun 30 04:26:17 PM PDT 24
Peak memory 198584 kb
Host smart-e5a04440-f175-457d-89d0-2944c0915a64
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2145938734 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.
gpio_stress_all.2145938734
Directory /workspace/34.gpio_stress_all/latest

Test location /workspace/coverage/default/35.gpio_alert_test.1386063668
Short name T701
Test name
Test status
Simulation time 23097842 ps
CPU time 0.58 seconds
Started Jun 30 04:23:56 PM PDT 24
Finished Jun 30 04:23:58 PM PDT 24
Peak memory 194452 kb
Host smart-4647a782-018a-40ba-99cb-5d04e3f45212
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1386063668 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_alert_test.1386063668
Directory /workspace/35.gpio_alert_test/latest

Test location /workspace/coverage/default/35.gpio_dout_din_regs_random_rw.1089430458
Short name T186
Test name
Test status
Simulation time 27285046 ps
CPU time 0.75 seconds
Started Jun 30 04:24:07 PM PDT 24
Finished Jun 30 04:24:11 PM PDT 24
Peak memory 195848 kb
Host smart-4b6572b0-6120-435e-ab6f-b7c7ba8d1c7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1089430458 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_dout_din_regs_random_rw.1089430458
Directory /workspace/35.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/35.gpio_filter_stress.584423056
Short name T215
Test name
Test status
Simulation time 391597156 ps
CPU time 10.67 seconds
Started Jun 30 04:23:52 PM PDT 24
Finished Jun 30 04:24:03 PM PDT 24
Peak memory 197368 kb
Host smart-43b72d96-b692-4453-86b3-3d0416d2aacd
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=584423056 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_filter_stres
s.584423056
Directory /workspace/35.gpio_filter_stress/latest

Test location /workspace/coverage/default/35.gpio_intr_rand_pgm.283584100
Short name T626
Test name
Test status
Simulation time 138252218 ps
CPU time 0.87 seconds
Started Jun 30 04:24:14 PM PDT 24
Finished Jun 30 04:24:17 PM PDT 24
Peak memory 197180 kb
Host smart-9a6a928d-7d3b-4e23-8dff-00a74586d17d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=283584100 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_intr_rand_pgm.283584100
Directory /workspace/35.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/35.gpio_intr_with_filter_rand_intr_event.1744874158
Short name T540
Test name
Test status
Simulation time 113283589 ps
CPU time 0.92 seconds
Started Jun 30 04:24:06 PM PDT 24
Finished Jun 30 04:24:11 PM PDT 24
Peak memory 197416 kb
Host smart-7a1a07bb-3a6c-43cd-8bec-0b42f981fb26
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1744874158 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 35.gpio_intr_with_filter_rand_intr_event.1744874158
Directory /workspace/35.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/35.gpio_rand_intr_trigger.3986189714
Short name T325
Test name
Test status
Simulation time 33681624 ps
CPU time 0.83 seconds
Started Jun 30 04:24:05 PM PDT 24
Finished Jun 30 04:24:10 PM PDT 24
Peak memory 194872 kb
Host smart-d75974c7-98d5-4aba-be45-07e85f65309e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3986189714 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_rand_intr_trigger
.3986189714
Directory /workspace/35.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/35.gpio_random_dout_din.2676176531
Short name T576
Test name
Test status
Simulation time 645609012 ps
CPU time 1.08 seconds
Started Jun 30 04:24:00 PM PDT 24
Finished Jun 30 04:24:04 PM PDT 24
Peak memory 196348 kb
Host smart-4f4fbb7e-d531-4d4d-9c5a-43362e41619a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2676176531 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_random_dout_din.2676176531
Directory /workspace/35.gpio_random_dout_din/latest

Test location /workspace/coverage/default/35.gpio_random_dout_din_no_pullup_pulldown.3052786720
Short name T320
Test name
Test status
Simulation time 23936462 ps
CPU time 0.73 seconds
Started Jun 30 04:24:00 PM PDT 24
Finished Jun 30 04:24:03 PM PDT 24
Peak memory 194628 kb
Host smart-b5d8701b-db40-4fda-aea7-4873a50216b6
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3052786720 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_random_dout_din_no_pullu
p_pulldown.3052786720
Directory /workspace/35.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/35.gpio_random_long_reg_writes_reg_reads.1082168315
Short name T1
Test name
Test status
Simulation time 218204144 ps
CPU time 2.08 seconds
Started Jun 30 04:24:00 PM PDT 24
Finished Jun 30 04:24:04 PM PDT 24
Peak memory 198336 kb
Host smart-11080809-b47b-466c-ac47-e5c3e437e371
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1082168315 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_ra
ndom_long_reg_writes_reg_reads.1082168315
Directory /workspace/35.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/35.gpio_smoke.2612316922
Short name T64
Test name
Test status
Simulation time 162093464 ps
CPU time 1.01 seconds
Started Jun 30 04:24:06 PM PDT 24
Finished Jun 30 04:24:11 PM PDT 24
Peak memory 196960 kb
Host smart-f7319dba-ca10-409b-984d-fd77ed432462
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2612316922 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_smoke.2612316922
Directory /workspace/35.gpio_smoke/latest

Test location /workspace/coverage/default/35.gpio_smoke_no_pullup_pulldown.363362099
Short name T681
Test name
Test status
Simulation time 341930361 ps
CPU time 0.85 seconds
Started Jun 30 04:23:56 PM PDT 24
Finished Jun 30 04:23:58 PM PDT 24
Peak memory 198096 kb
Host smart-2110a78f-6921-470a-8f77-ab4d23e5b19c
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=363362099 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_smoke_no_pullup_pulldown.363362099
Directory /workspace/35.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/35.gpio_stress_all.1161972516
Short name T367
Test name
Test status
Simulation time 3112194050 ps
CPU time 73.15 seconds
Started Jun 30 04:23:55 PM PDT 24
Finished Jun 30 04:25:10 PM PDT 24
Peak memory 198536 kb
Host smart-b4bf9d25-b23c-49ef-bab7-8e61c67217ef
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1161972516 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.
gpio_stress_all.1161972516
Directory /workspace/35.gpio_stress_all/latest

Test location /workspace/coverage/default/35.gpio_stress_all_with_rand_reset.1223921259
Short name T618
Test name
Test status
Simulation time 37033752521 ps
CPU time 993.01 seconds
Started Jun 30 04:24:05 PM PDT 24
Finished Jun 30 04:40:41 PM PDT 24
Peak memory 198692 kb
Host smart-340c3acb-2257-49da-aa61-05f5d914ed9e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1223921259 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_stress_all_with_rand_reset.1223921259
Directory /workspace/35.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.gpio_alert_test.3630497472
Short name T488
Test name
Test status
Simulation time 21016703 ps
CPU time 0.56 seconds
Started Jun 30 04:24:12 PM PDT 24
Finished Jun 30 04:24:19 PM PDT 24
Peak memory 194468 kb
Host smart-c63bc8ba-83c9-4d4d-8c20-7aaf2abc6b89
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3630497472 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_alert_test.3630497472
Directory /workspace/36.gpio_alert_test/latest

Test location /workspace/coverage/default/36.gpio_dout_din_regs_random_rw.2431520536
Short name T565
Test name
Test status
Simulation time 76091569 ps
CPU time 0.72 seconds
Started Jun 30 04:24:02 PM PDT 24
Finished Jun 30 04:24:06 PM PDT 24
Peak memory 196328 kb
Host smart-190ae0e3-0cb5-49eb-a6d2-1c1d3a1b9e6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2431520536 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_dout_din_regs_random_rw.2431520536
Directory /workspace/36.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/36.gpio_filter_stress.3717774376
Short name T378
Test name
Test status
Simulation time 289216770 ps
CPU time 4.74 seconds
Started Jun 30 04:24:01 PM PDT 24
Finished Jun 30 04:24:08 PM PDT 24
Peak memory 196928 kb
Host smart-5b1ae54c-5e44-453a-bfb1-1fe94fc692e3
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3717774376 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_filter_stre
ss.3717774376
Directory /workspace/36.gpio_filter_stress/latest

Test location /workspace/coverage/default/36.gpio_full_random.2981514375
Short name T138
Test name
Test status
Simulation time 138408555 ps
CPU time 0.97 seconds
Started Jun 30 04:24:03 PM PDT 24
Finished Jun 30 04:24:08 PM PDT 24
Peak memory 197064 kb
Host smart-b5207017-0a35-4eb9-990c-83fc5d87a067
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2981514375 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_full_random.2981514375
Directory /workspace/36.gpio_full_random/latest

Test location /workspace/coverage/default/36.gpio_intr_rand_pgm.1406855409
Short name T99
Test name
Test status
Simulation time 31672622 ps
CPU time 0.78 seconds
Started Jun 30 04:24:06 PM PDT 24
Finished Jun 30 04:24:10 PM PDT 24
Peak memory 197096 kb
Host smart-dbe2709d-4ea8-42ea-9634-3c1a4e391438
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1406855409 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_intr_rand_pgm.1406855409
Directory /workspace/36.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/36.gpio_intr_with_filter_rand_intr_event.3785727584
Short name T585
Test name
Test status
Simulation time 60826980 ps
CPU time 1.31 seconds
Started Jun 30 04:24:02 PM PDT 24
Finished Jun 30 04:24:06 PM PDT 24
Peak memory 198336 kb
Host smart-eab4fc27-17bf-47ee-b8b6-4d98e02374e3
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3785727584 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 36.gpio_intr_with_filter_rand_intr_event.3785727584
Directory /workspace/36.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/36.gpio_rand_intr_trigger.881995422
Short name T461
Test name
Test status
Simulation time 144460343 ps
CPU time 2.2 seconds
Started Jun 30 04:24:02 PM PDT 24
Finished Jun 30 04:24:07 PM PDT 24
Peak memory 197548 kb
Host smart-ca8684ba-bd9b-459f-8137-896e6701ac74
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=881995422 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_rand_intr_trigger.
881995422
Directory /workspace/36.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/36.gpio_random_dout_din.472610926
Short name T629
Test name
Test status
Simulation time 134811534 ps
CPU time 0.96 seconds
Started Jun 30 04:24:06 PM PDT 24
Finished Jun 30 04:24:11 PM PDT 24
Peak memory 197136 kb
Host smart-6d232cf7-b37b-46a3-8a59-95ecbd698f06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=472610926 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_random_dout_din.472610926
Directory /workspace/36.gpio_random_dout_din/latest

Test location /workspace/coverage/default/36.gpio_random_dout_din_no_pullup_pulldown.2079578996
Short name T211
Test name
Test status
Simulation time 112157828 ps
CPU time 0.97 seconds
Started Jun 30 04:24:01 PM PDT 24
Finished Jun 30 04:24:05 PM PDT 24
Peak memory 196500 kb
Host smart-5b4f9e54-4202-47c6-ae3d-4fc4c5ebf0e5
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2079578996 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_random_dout_din_no_pullu
p_pulldown.2079578996
Directory /workspace/36.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/36.gpio_random_long_reg_writes_reg_reads.2798784069
Short name T301
Test name
Test status
Simulation time 217042047 ps
CPU time 3 seconds
Started Jun 30 04:23:59 PM PDT 24
Finished Jun 30 04:24:03 PM PDT 24
Peak memory 198444 kb
Host smart-ad80cc6a-f745-4cfb-b75b-fd79c466e571
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2798784069 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_ra
ndom_long_reg_writes_reg_reads.2798784069
Directory /workspace/36.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/36.gpio_smoke.3877423719
Short name T510
Test name
Test status
Simulation time 273636705 ps
CPU time 0.72 seconds
Started Jun 30 04:24:01 PM PDT 24
Finished Jun 30 04:24:04 PM PDT 24
Peak memory 194564 kb
Host smart-af0ab42a-701c-4d89-99ae-ea439d7fd651
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3877423719 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_smoke.3877423719
Directory /workspace/36.gpio_smoke/latest

Test location /workspace/coverage/default/36.gpio_smoke_no_pullup_pulldown.1513632530
Short name T291
Test name
Test status
Simulation time 27571603 ps
CPU time 0.83 seconds
Started Jun 30 04:24:05 PM PDT 24
Finished Jun 30 04:24:09 PM PDT 24
Peak memory 195684 kb
Host smart-901acf29-2bed-4bd3-a3ea-7184f1f76c06
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1513632530 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_smoke_no_pullup_pulldown.1513632530
Directory /workspace/36.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/36.gpio_stress_all.14624848
Short name T97
Test name
Test status
Simulation time 7454677783 ps
CPU time 191.24 seconds
Started Jun 30 04:24:16 PM PDT 24
Finished Jun 30 04:27:28 PM PDT 24
Peak memory 198588 kb
Host smart-ca9d9951-3be8-43bd-b120-1680515d5d20
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14624848 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TE
ST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gp
io_stress_all.14624848
Directory /workspace/36.gpio_stress_all/latest

Test location /workspace/coverage/default/37.gpio_alert_test.1909300967
Short name T355
Test name
Test status
Simulation time 10471581 ps
CPU time 0.55 seconds
Started Jun 30 04:23:54 PM PDT 24
Finished Jun 30 04:23:56 PM PDT 24
Peak memory 195128 kb
Host smart-3a814a91-1d3b-47fb-9524-a8fff1fe6d78
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1909300967 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_alert_test.1909300967
Directory /workspace/37.gpio_alert_test/latest

Test location /workspace/coverage/default/37.gpio_dout_din_regs_random_rw.1787744751
Short name T469
Test name
Test status
Simulation time 35100349 ps
CPU time 0.69 seconds
Started Jun 30 04:23:58 PM PDT 24
Finished Jun 30 04:24:00 PM PDT 24
Peak memory 194620 kb
Host smart-d60957c4-1fc7-45ba-820a-874057b6c03c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1787744751 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_dout_din_regs_random_rw.1787744751
Directory /workspace/37.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/37.gpio_filter_stress.3272776549
Short name T433
Test name
Test status
Simulation time 1025398020 ps
CPU time 8.56 seconds
Started Jun 30 04:24:01 PM PDT 24
Finished Jun 30 04:24:13 PM PDT 24
Peak memory 197392 kb
Host smart-3578aa44-12f5-47ba-a185-7bcee4c9a01d
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3272776549 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_filter_stre
ss.3272776549
Directory /workspace/37.gpio_filter_stress/latest

Test location /workspace/coverage/default/37.gpio_full_random.3620963352
Short name T483
Test name
Test status
Simulation time 54866672 ps
CPU time 0.85 seconds
Started Jun 30 04:24:02 PM PDT 24
Finished Jun 30 04:24:06 PM PDT 24
Peak memory 197424 kb
Host smart-e50132fd-4c3f-4db1-8585-52933c83765d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3620963352 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_full_random.3620963352
Directory /workspace/37.gpio_full_random/latest

Test location /workspace/coverage/default/37.gpio_intr_rand_pgm.2566596535
Short name T297
Test name
Test status
Simulation time 291676695 ps
CPU time 1.18 seconds
Started Jun 30 04:23:57 PM PDT 24
Finished Jun 30 04:23:59 PM PDT 24
Peak memory 197128 kb
Host smart-5d74eee3-131b-4138-b8a2-007715b86f66
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2566596535 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_intr_rand_pgm.2566596535
Directory /workspace/37.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/37.gpio_rand_intr_trigger.3017913841
Short name T502
Test name
Test status
Simulation time 283775207 ps
CPU time 2.11 seconds
Started Jun 30 04:24:07 PM PDT 24
Finished Jun 30 04:24:13 PM PDT 24
Peak memory 197468 kb
Host smart-01361f76-5b1d-47c8-a472-4dcf7d766ad3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3017913841 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_rand_intr_trigger
.3017913841
Directory /workspace/37.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/37.gpio_random_dout_din.1576287282
Short name T674
Test name
Test status
Simulation time 145400920 ps
CPU time 0.95 seconds
Started Jun 30 04:24:09 PM PDT 24
Finished Jun 30 04:24:13 PM PDT 24
Peak memory 196860 kb
Host smart-d42c20d9-1494-4a11-89d7-26c4451ad7f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1576287282 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_random_dout_din.1576287282
Directory /workspace/37.gpio_random_dout_din/latest

Test location /workspace/coverage/default/37.gpio_random_dout_din_no_pullup_pulldown.3555108092
Short name T421
Test name
Test status
Simulation time 75911786 ps
CPU time 1.23 seconds
Started Jun 30 04:24:05 PM PDT 24
Finished Jun 30 04:24:09 PM PDT 24
Peak memory 197448 kb
Host smart-7888384b-d3f1-405c-a82c-1f9b8ff60475
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3555108092 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_random_dout_din_no_pullu
p_pulldown.3555108092
Directory /workspace/37.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/37.gpio_random_long_reg_writes_reg_reads.3319017384
Short name T410
Test name
Test status
Simulation time 217327479 ps
CPU time 3.38 seconds
Started Jun 30 04:24:08 PM PDT 24
Finished Jun 30 04:24:14 PM PDT 24
Peak memory 198484 kb
Host smart-1e77d339-a5d1-43db-8587-e0f4cac9912d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3319017384 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_ra
ndom_long_reg_writes_reg_reads.3319017384
Directory /workspace/37.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/37.gpio_smoke.36475234
Short name T284
Test name
Test status
Simulation time 112913366 ps
CPU time 1 seconds
Started Jun 30 04:23:57 PM PDT 24
Finished Jun 30 04:23:59 PM PDT 24
Peak memory 197500 kb
Host smart-c5a82393-5873-4772-95d1-1864b99b60e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=36475234 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_smoke.36475234
Directory /workspace/37.gpio_smoke/latest

Test location /workspace/coverage/default/37.gpio_smoke_no_pullup_pulldown.3938883936
Short name T415
Test name
Test status
Simulation time 88091523 ps
CPU time 0.66 seconds
Started Jun 30 04:24:05 PM PDT 24
Finished Jun 30 04:24:09 PM PDT 24
Peak memory 194504 kb
Host smart-5c9f0ce0-1b26-48a1-86e2-5818a21f821c
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3938883936 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_smoke_no_pullup_pulldown.3938883936
Directory /workspace/37.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/37.gpio_stress_all.1125073757
Short name T390
Test name
Test status
Simulation time 23711140282 ps
CPU time 138.8 seconds
Started Jun 30 04:24:04 PM PDT 24
Finished Jun 30 04:26:26 PM PDT 24
Peak memory 198588 kb
Host smart-ad34d0df-b7f7-4efd-9426-2547bdc7f6d4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1125073757 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.
gpio_stress_all.1125073757
Directory /workspace/37.gpio_stress_all/latest

Test location /workspace/coverage/default/37.gpio_stress_all_with_rand_reset.2177621127
Short name T59
Test name
Test status
Simulation time 225142884115 ps
CPU time 2290.71 seconds
Started Jun 30 04:24:06 PM PDT 24
Finished Jun 30 05:02:20 PM PDT 24
Peak memory 198660 kb
Host smart-43dbaa81-03f7-4162-b5a2-e8f1c74a3963
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2177621127 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_stress_all_with_rand_reset.2177621127
Directory /workspace/37.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.gpio_alert_test.105276140
Short name T382
Test name
Test status
Simulation time 19319121 ps
CPU time 0.62 seconds
Started Jun 30 04:24:00 PM PDT 24
Finished Jun 30 04:24:03 PM PDT 24
Peak memory 193664 kb
Host smart-67a776db-1f85-484d-a1eb-b80b2e2bfb79
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=105276140 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_alert_test.105276140
Directory /workspace/38.gpio_alert_test/latest

Test location /workspace/coverage/default/38.gpio_dout_din_regs_random_rw.3671714223
Short name T484
Test name
Test status
Simulation time 23126398 ps
CPU time 0.76 seconds
Started Jun 30 04:24:06 PM PDT 24
Finished Jun 30 04:24:11 PM PDT 24
Peak memory 196396 kb
Host smart-979736ed-eefc-48ac-98b4-4a80dd9a4de5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3671714223 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_dout_din_regs_random_rw.3671714223
Directory /workspace/38.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/38.gpio_filter_stress.2098190335
Short name T657
Test name
Test status
Simulation time 3616542752 ps
CPU time 23.32 seconds
Started Jun 30 04:24:12 PM PDT 24
Finished Jun 30 04:24:38 PM PDT 24
Peak memory 197128 kb
Host smart-98bfb0b0-8447-4859-8f37-9ef58b1035a2
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2098190335 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_filter_stre
ss.2098190335
Directory /workspace/38.gpio_filter_stress/latest

Test location /workspace/coverage/default/38.gpio_full_random.3775420078
Short name T508
Test name
Test status
Simulation time 387804006 ps
CPU time 0.77 seconds
Started Jun 30 04:24:01 PM PDT 24
Finished Jun 30 04:24:05 PM PDT 24
Peak memory 196360 kb
Host smart-a2aeaa29-7c63-458e-aa66-61908766f89c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3775420078 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_full_random.3775420078
Directory /workspace/38.gpio_full_random/latest

Test location /workspace/coverage/default/38.gpio_intr_rand_pgm.2665565199
Short name T525
Test name
Test status
Simulation time 209617910 ps
CPU time 0.99 seconds
Started Jun 30 04:24:17 PM PDT 24
Finished Jun 30 04:24:18 PM PDT 24
Peak memory 197292 kb
Host smart-ecfca8fb-d5a4-4d8e-a0b4-8edd5705b967
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2665565199 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_intr_rand_pgm.2665565199
Directory /workspace/38.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/38.gpio_intr_with_filter_rand_intr_event.2536650784
Short name T183
Test name
Test status
Simulation time 82137393 ps
CPU time 3.23 seconds
Started Jun 30 04:24:03 PM PDT 24
Finished Jun 30 04:24:09 PM PDT 24
Peak memory 198924 kb
Host smart-fe773f8a-7d86-426f-9bc3-9beac81d547e
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2536650784 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 38.gpio_intr_with_filter_rand_intr_event.2536650784
Directory /workspace/38.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/38.gpio_rand_intr_trigger.1407004330
Short name T535
Test name
Test status
Simulation time 53999583 ps
CPU time 0.94 seconds
Started Jun 30 04:24:07 PM PDT 24
Finished Jun 30 04:24:12 PM PDT 24
Peak memory 196036 kb
Host smart-8b39fe0d-269d-4c45-9f9b-4ebee76eecbf
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1407004330 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_rand_intr_trigger
.1407004330
Directory /workspace/38.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/38.gpio_random_dout_din.3818902741
Short name T607
Test name
Test status
Simulation time 38316733 ps
CPU time 0.84 seconds
Started Jun 30 04:24:02 PM PDT 24
Finished Jun 30 04:24:06 PM PDT 24
Peak memory 197056 kb
Host smart-4f973c01-f7f5-43b5-af7f-89413ea43131
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3818902741 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_random_dout_din.3818902741
Directory /workspace/38.gpio_random_dout_din/latest

Test location /workspace/coverage/default/38.gpio_random_dout_din_no_pullup_pulldown.1119840702
Short name T549
Test name
Test status
Simulation time 132817050 ps
CPU time 1.14 seconds
Started Jun 30 04:24:03 PM PDT 24
Finished Jun 30 04:24:07 PM PDT 24
Peak memory 197380 kb
Host smart-931b0591-6d70-4803-bc14-c9a221cfd0bd
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1119840702 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_random_dout_din_no_pullu
p_pulldown.1119840702
Directory /workspace/38.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/38.gpio_random_long_reg_writes_reg_reads.1444896536
Short name T338
Test name
Test status
Simulation time 155765415 ps
CPU time 2.4 seconds
Started Jun 30 04:23:59 PM PDT 24
Finished Jun 30 04:24:03 PM PDT 24
Peak memory 198364 kb
Host smart-c91c7aee-6723-493b-ac8d-9e20609377d8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1444896536 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_ra
ndom_long_reg_writes_reg_reads.1444896536
Directory /workspace/38.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/38.gpio_smoke.2635225998
Short name T176
Test name
Test status
Simulation time 480668035 ps
CPU time 1.27 seconds
Started Jun 30 04:24:06 PM PDT 24
Finished Jun 30 04:24:11 PM PDT 24
Peak memory 198444 kb
Host smart-d751e644-4bda-4073-b4a8-8f8f455bed8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2635225998 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_smoke.2635225998
Directory /workspace/38.gpio_smoke/latest

Test location /workspace/coverage/default/38.gpio_smoke_no_pullup_pulldown.4025944368
Short name T596
Test name
Test status
Simulation time 68749103 ps
CPU time 1.3 seconds
Started Jun 30 04:23:47 PM PDT 24
Finished Jun 30 04:23:49 PM PDT 24
Peak memory 198284 kb
Host smart-9359b356-f637-45f3-8c08-45dc0b68022e
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4025944368 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_smoke_no_pullup_pulldown.4025944368
Directory /workspace/38.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/38.gpio_stress_all.611273914
Short name T21
Test name
Test status
Simulation time 43886689206 ps
CPU time 99.4 seconds
Started Jun 30 04:24:15 PM PDT 24
Finished Jun 30 04:25:56 PM PDT 24
Peak memory 198628 kb
Host smart-db187baa-0d8f-45ec-b26f-e5140be85816
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=611273914 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.g
pio_stress_all.611273914
Directory /workspace/38.gpio_stress_all/latest

Test location /workspace/coverage/default/39.gpio_alert_test.2551462260
Short name T166
Test name
Test status
Simulation time 24010068 ps
CPU time 0.55 seconds
Started Jun 30 04:24:11 PM PDT 24
Finished Jun 30 04:24:14 PM PDT 24
Peak memory 194384 kb
Host smart-9d45e009-14e5-4f87-9df4-f5071f5831f0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2551462260 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_alert_test.2551462260
Directory /workspace/39.gpio_alert_test/latest

Test location /workspace/coverage/default/39.gpio_dout_din_regs_random_rw.1811653047
Short name T713
Test name
Test status
Simulation time 19378231 ps
CPU time 0.67 seconds
Started Jun 30 04:24:03 PM PDT 24
Finished Jun 30 04:24:06 PM PDT 24
Peak memory 195392 kb
Host smart-4c7c8f37-4834-479c-8295-b48cd97369ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1811653047 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_dout_din_regs_random_rw.1811653047
Directory /workspace/39.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/39.gpio_filter_stress.4250363477
Short name T352
Test name
Test status
Simulation time 509700559 ps
CPU time 12.25 seconds
Started Jun 30 04:24:12 PM PDT 24
Finished Jun 30 04:24:26 PM PDT 24
Peak memory 196976 kb
Host smart-11b13bcf-07ee-47d9-8a7f-263f8306eedf
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4250363477 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_filter_stre
ss.4250363477
Directory /workspace/39.gpio_filter_stress/latest

Test location /workspace/coverage/default/39.gpio_full_random.2440773462
Short name T709
Test name
Test status
Simulation time 128873389 ps
CPU time 0.7 seconds
Started Jun 30 04:24:03 PM PDT 24
Finished Jun 30 04:24:07 PM PDT 24
Peak memory 195164 kb
Host smart-4d48c209-e6e2-4e67-90e6-eafbf7cd7115
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2440773462 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_full_random.2440773462
Directory /workspace/39.gpio_full_random/latest

Test location /workspace/coverage/default/39.gpio_intr_rand_pgm.1702751210
Short name T450
Test name
Test status
Simulation time 53384748 ps
CPU time 0.71 seconds
Started Jun 30 04:24:18 PM PDT 24
Finished Jun 30 04:24:19 PM PDT 24
Peak memory 196540 kb
Host smart-b2bdedef-1401-4317-813d-71b4f7a6eed6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1702751210 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_intr_rand_pgm.1702751210
Directory /workspace/39.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/39.gpio_intr_with_filter_rand_intr_event.334700269
Short name T148
Test name
Test status
Simulation time 59525490 ps
CPU time 2.2 seconds
Started Jun 30 04:24:06 PM PDT 24
Finished Jun 30 04:24:11 PM PDT 24
Peak memory 198532 kb
Host smart-13ec71bb-fe04-40b3-b356-3dd89435c7c5
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=334700269 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 39.gpio_intr_with_filter_rand_intr_event.334700269
Directory /workspace/39.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/39.gpio_rand_intr_trigger.3673843312
Short name T486
Test name
Test status
Simulation time 50046532 ps
CPU time 0.87 seconds
Started Jun 30 04:24:05 PM PDT 24
Finished Jun 30 04:24:09 PM PDT 24
Peak memory 196708 kb
Host smart-798c5a21-d9ae-441a-809b-c984177a262b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3673843312 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_rand_intr_trigger
.3673843312
Directory /workspace/39.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/39.gpio_random_dout_din.2804816343
Short name T446
Test name
Test status
Simulation time 189436304 ps
CPU time 0.95 seconds
Started Jun 30 04:24:21 PM PDT 24
Finished Jun 30 04:24:22 PM PDT 24
Peak memory 196496 kb
Host smart-ce2d240d-dd2f-417f-b4e3-ff8ffeadf0e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2804816343 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_random_dout_din.2804816343
Directory /workspace/39.gpio_random_dout_din/latest

Test location /workspace/coverage/default/39.gpio_random_dout_din_no_pullup_pulldown.1293478979
Short name T568
Test name
Test status
Simulation time 67435917 ps
CPU time 1.24 seconds
Started Jun 30 04:24:12 PM PDT 24
Finished Jun 30 04:24:16 PM PDT 24
Peak memory 198496 kb
Host smart-ba60edf8-a563-410f-b04c-ea4483f83985
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1293478979 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_random_dout_din_no_pullu
p_pulldown.1293478979
Directory /workspace/39.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/39.gpio_random_long_reg_writes_reg_reads.1311076072
Short name T561
Test name
Test status
Simulation time 508275791 ps
CPU time 5.59 seconds
Started Jun 30 04:24:15 PM PDT 24
Finished Jun 30 04:24:22 PM PDT 24
Peak memory 198428 kb
Host smart-7942163b-64ca-4a70-b1a5-1bd7852674bf
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1311076072 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_ra
ndom_long_reg_writes_reg_reads.1311076072
Directory /workspace/39.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/39.gpio_smoke.3313491561
Short name T671
Test name
Test status
Simulation time 140697169 ps
CPU time 0.91 seconds
Started Jun 30 04:24:06 PM PDT 24
Finished Jun 30 04:24:11 PM PDT 24
Peak memory 197572 kb
Host smart-52ac1e43-37c2-4e47-aca1-e56672129337
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3313491561 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_smoke.3313491561
Directory /workspace/39.gpio_smoke/latest

Test location /workspace/coverage/default/39.gpio_smoke_no_pullup_pulldown.4229953977
Short name T235
Test name
Test status
Simulation time 139142467 ps
CPU time 1.16 seconds
Started Jun 30 04:24:09 PM PDT 24
Finished Jun 30 04:24:14 PM PDT 24
Peak memory 196784 kb
Host smart-16ffb8a9-144c-4bb9-9a0c-9472d195de70
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4229953977 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_smoke_no_pullup_pulldown.4229953977
Directory /workspace/39.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/39.gpio_stress_all.3883924205
Short name T265
Test name
Test status
Simulation time 27775697368 ps
CPU time 71.14 seconds
Started Jun 30 04:24:05 PM PDT 24
Finished Jun 30 04:25:19 PM PDT 24
Peak memory 198624 kb
Host smart-f7bc380e-f0dc-444a-a80c-f9a84a7cab02
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3883924205 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.
gpio_stress_all.3883924205
Directory /workspace/39.gpio_stress_all/latest

Test location /workspace/coverage/default/4.gpio_alert_test.3391160858
Short name T520
Test name
Test status
Simulation time 34035425 ps
CPU time 0.58 seconds
Started Jun 30 04:22:55 PM PDT 24
Finished Jun 30 04:22:58 PM PDT 24
Peak memory 194500 kb
Host smart-5f78e286-345d-40c3-bff5-2f6160912b6a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3391160858 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_alert_test.3391160858
Directory /workspace/4.gpio_alert_test/latest

Test location /workspace/coverage/default/4.gpio_dout_din_regs_random_rw.2787136603
Short name T141
Test name
Test status
Simulation time 201114951 ps
CPU time 0.81 seconds
Started Jun 30 04:22:57 PM PDT 24
Finished Jun 30 04:23:00 PM PDT 24
Peak memory 195668 kb
Host smart-705a545b-9138-4c03-a5f8-d783065e8430
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2787136603 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_dout_din_regs_random_rw.2787136603
Directory /workspace/4.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/4.gpio_filter_stress.3406332812
Short name T121
Test name
Test status
Simulation time 140122667 ps
CPU time 4.78 seconds
Started Jun 30 04:22:51 PM PDT 24
Finished Jun 30 04:22:57 PM PDT 24
Peak memory 196980 kb
Host smart-c68a170d-7a02-4cb4-b476-58971773f0dc
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3406332812 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_filter_stres
s.3406332812
Directory /workspace/4.gpio_filter_stress/latest

Test location /workspace/coverage/default/4.gpio_full_random.254779729
Short name T660
Test name
Test status
Simulation time 80347214 ps
CPU time 0.6 seconds
Started Jun 30 04:23:20 PM PDT 24
Finished Jun 30 04:23:21 PM PDT 24
Peak memory 195276 kb
Host smart-db5fb6a7-c580-4327-8253-fc4e5e55b0ac
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=254779729 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_full_random.254779729
Directory /workspace/4.gpio_full_random/latest

Test location /workspace/coverage/default/4.gpio_intr_rand_pgm.709781789
Short name T439
Test name
Test status
Simulation time 43055767 ps
CPU time 1.19 seconds
Started Jun 30 04:23:10 PM PDT 24
Finished Jun 30 04:23:11 PM PDT 24
Peak memory 197636 kb
Host smart-645af14a-24bc-4c06-9f73-41d4be99ddca
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=709781789 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_intr_rand_pgm.709781789
Directory /workspace/4.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/4.gpio_intr_with_filter_rand_intr_event.2590488013
Short name T456
Test name
Test status
Simulation time 941617054 ps
CPU time 2.36 seconds
Started Jun 30 04:23:16 PM PDT 24
Finished Jun 30 04:23:20 PM PDT 24
Peak memory 198540 kb
Host smart-474b7b83-d58a-49a2-a10b-5918ae4db93c
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2590488013 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 4.gpio_intr_with_filter_rand_intr_event.2590488013
Directory /workspace/4.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/4.gpio_rand_intr_trigger.2633935898
Short name T624
Test name
Test status
Simulation time 2037750385 ps
CPU time 2.35 seconds
Started Jun 30 04:23:18 PM PDT 24
Finished Jun 30 04:23:22 PM PDT 24
Peak memory 198512 kb
Host smart-ad0fdecf-e81a-46f0-b33c-278010b00a74
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2633935898 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_rand_intr_trigger.
2633935898
Directory /workspace/4.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/4.gpio_random_dout_din.3436524808
Short name T302
Test name
Test status
Simulation time 102432454 ps
CPU time 1 seconds
Started Jun 30 04:23:17 PM PDT 24
Finished Jun 30 04:23:20 PM PDT 24
Peak memory 196488 kb
Host smart-47f2ca37-b2a8-46b4-87b5-f6d59af29582
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3436524808 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_random_dout_din.3436524808
Directory /workspace/4.gpio_random_dout_din/latest

Test location /workspace/coverage/default/4.gpio_random_dout_din_no_pullup_pulldown.831485345
Short name T137
Test name
Test status
Simulation time 45534434 ps
CPU time 0.7 seconds
Started Jun 30 04:22:52 PM PDT 24
Finished Jun 30 04:22:55 PM PDT 24
Peak memory 195404 kb
Host smart-d680626a-a3b8-43d5-9058-6677a7c4ae70
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=831485345 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_random_dout_din_no_pullup_
pulldown.831485345
Directory /workspace/4.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/4.gpio_random_long_reg_writes_reg_reads.4027598976
Short name T232
Test name
Test status
Simulation time 765103903 ps
CPU time 2.41 seconds
Started Jun 30 04:22:55 PM PDT 24
Finished Jun 30 04:23:00 PM PDT 24
Peak memory 198484 kb
Host smart-93815dfc-fbf9-40c3-9df2-0799146a64d6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4027598976 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_ran
dom_long_reg_writes_reg_reads.4027598976
Directory /workspace/4.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/4.gpio_sec_cm.3102825449
Short name T39
Test name
Test status
Simulation time 1255761559 ps
CPU time 0.89 seconds
Started Jun 30 04:22:51 PM PDT 24
Finished Jun 30 04:22:54 PM PDT 24
Peak memory 215188 kb
Host smart-4c002f34-9336-4ce7-97bf-d1838598ee98
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3102825449 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_sec_cm.3102825449
Directory /workspace/4.gpio_sec_cm/latest

Test location /workspace/coverage/default/4.gpio_smoke.2029497653
Short name T478
Test name
Test status
Simulation time 430219490 ps
CPU time 1.71 seconds
Started Jun 30 04:22:51 PM PDT 24
Finished Jun 30 04:22:54 PM PDT 24
Peak memory 197328 kb
Host smart-5d5a97bb-77f9-46bb-829f-3d6d002b9e1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2029497653 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_smoke.2029497653
Directory /workspace/4.gpio_smoke/latest

Test location /workspace/coverage/default/4.gpio_smoke_no_pullup_pulldown.1734367607
Short name T658
Test name
Test status
Simulation time 29138710 ps
CPU time 0.85 seconds
Started Jun 30 04:22:56 PM PDT 24
Finished Jun 30 04:22:59 PM PDT 24
Peak memory 196916 kb
Host smart-e2d57968-21e1-4599-9e45-2df1cfcc42fa
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1734367607 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_smoke_no_pullup_pulldown.1734367607
Directory /workspace/4.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/4.gpio_stress_all.2913211277
Short name T283
Test name
Test status
Simulation time 4440255562 ps
CPU time 95.79 seconds
Started Jun 30 04:23:05 PM PDT 24
Finished Jun 30 04:24:42 PM PDT 24
Peak memory 198640 kb
Host smart-40c86e4a-5e2b-4d55-96dc-1fe28ef82a4b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2913211277 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.g
pio_stress_all.2913211277
Directory /workspace/4.gpio_stress_all/latest

Test location /workspace/coverage/default/40.gpio_alert_test.3761313527
Short name T200
Test name
Test status
Simulation time 18792855 ps
CPU time 0.55 seconds
Started Jun 30 04:24:16 PM PDT 24
Finished Jun 30 04:24:18 PM PDT 24
Peak memory 194484 kb
Host smart-e5e84588-c084-4be3-b532-683f6a57a4b6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3761313527 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_alert_test.3761313527
Directory /workspace/40.gpio_alert_test/latest

Test location /workspace/coverage/default/40.gpio_dout_din_regs_random_rw.940469654
Short name T170
Test name
Test status
Simulation time 16670119 ps
CPU time 0.62 seconds
Started Jun 30 04:24:06 PM PDT 24
Finished Jun 30 04:24:10 PM PDT 24
Peak memory 195144 kb
Host smart-fc83c04e-ab92-49fa-be39-6f591761e34b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=940469654 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_dout_din_regs_random_rw.940469654
Directory /workspace/40.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/40.gpio_filter_stress.2200186139
Short name T708
Test name
Test status
Simulation time 654597290 ps
CPU time 22.43 seconds
Started Jun 30 04:24:05 PM PDT 24
Finished Jun 30 04:24:31 PM PDT 24
Peak memory 197596 kb
Host smart-5478142d-ebc7-4406-b0b0-e04647a54bd6
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2200186139 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_filter_stre
ss.2200186139
Directory /workspace/40.gpio_filter_stress/latest

Test location /workspace/coverage/default/40.gpio_full_random.1076335514
Short name T154
Test name
Test status
Simulation time 96967266 ps
CPU time 0.79 seconds
Started Jun 30 04:24:15 PM PDT 24
Finished Jun 30 04:24:17 PM PDT 24
Peak memory 197072 kb
Host smart-6b14c43a-e2cb-4fd1-8a34-8577ffdd9d3c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1076335514 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_full_random.1076335514
Directory /workspace/40.gpio_full_random/latest

Test location /workspace/coverage/default/40.gpio_intr_rand_pgm.3000101172
Short name T413
Test name
Test status
Simulation time 28715827 ps
CPU time 0.7 seconds
Started Jun 30 04:23:55 PM PDT 24
Finished Jun 30 04:23:56 PM PDT 24
Peak memory 194844 kb
Host smart-18f20e9c-248b-4480-874e-7ba163beffb8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3000101172 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_intr_rand_pgm.3000101172
Directory /workspace/40.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/40.gpio_intr_with_filter_rand_intr_event.3401871883
Short name T560
Test name
Test status
Simulation time 200370947 ps
CPU time 1.93 seconds
Started Jun 30 04:24:06 PM PDT 24
Finished Jun 30 04:24:11 PM PDT 24
Peak memory 197372 kb
Host smart-0c894447-3a6a-432d-b88e-685c55205cf2
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3401871883 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 40.gpio_intr_with_filter_rand_intr_event.3401871883
Directory /workspace/40.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/40.gpio_rand_intr_trigger.1647258693
Short name T480
Test name
Test status
Simulation time 314986069 ps
CPU time 2.4 seconds
Started Jun 30 04:24:03 PM PDT 24
Finished Jun 30 04:24:09 PM PDT 24
Peak memory 197720 kb
Host smart-0ef78eab-ba5a-4503-bb41-fcde40974915
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1647258693 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_rand_intr_trigger
.1647258693
Directory /workspace/40.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/40.gpio_random_dout_din.2810323278
Short name T362
Test name
Test status
Simulation time 74715054 ps
CPU time 0.89 seconds
Started Jun 30 04:24:12 PM PDT 24
Finished Jun 30 04:24:15 PM PDT 24
Peak memory 197248 kb
Host smart-95a02ecb-bd36-483a-a787-6da0d2b07189
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2810323278 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_random_dout_din.2810323278
Directory /workspace/40.gpio_random_dout_din/latest

Test location /workspace/coverage/default/40.gpio_random_dout_din_no_pullup_pulldown.752035543
Short name T504
Test name
Test status
Simulation time 51584958 ps
CPU time 0.61 seconds
Started Jun 30 04:24:10 PM PDT 24
Finished Jun 30 04:24:14 PM PDT 24
Peak memory 194704 kb
Host smart-6065f39c-9ef3-4a06-8069-04c020ecc2d4
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=752035543 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_random_dout_din_no_pullup
_pulldown.752035543
Directory /workspace/40.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/40.gpio_random_long_reg_writes_reg_reads.1411358248
Short name T3
Test name
Test status
Simulation time 550789654 ps
CPU time 5.85 seconds
Started Jun 30 04:24:09 PM PDT 24
Finished Jun 30 04:24:18 PM PDT 24
Peak memory 198456 kb
Host smart-17505647-c86e-48f1-a35d-32e8546b4154
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1411358248 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_ra
ndom_long_reg_writes_reg_reads.1411358248
Directory /workspace/40.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/40.gpio_smoke.77549229
Short name T122
Test name
Test status
Simulation time 224883863 ps
CPU time 1.14 seconds
Started Jun 30 04:24:16 PM PDT 24
Finished Jun 30 04:24:18 PM PDT 24
Peak memory 196304 kb
Host smart-2ca8c2f2-6565-4cfd-a308-9702d4543b4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=77549229 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_smoke.77549229
Directory /workspace/40.gpio_smoke/latest

Test location /workspace/coverage/default/40.gpio_smoke_no_pullup_pulldown.3238606171
Short name T312
Test name
Test status
Simulation time 21828473 ps
CPU time 0.81 seconds
Started Jun 30 04:24:14 PM PDT 24
Finished Jun 30 04:24:17 PM PDT 24
Peak memory 196492 kb
Host smart-860599e3-03f1-44a5-b5e6-0c0a4731dde5
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3238606171 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_smoke_no_pullup_pulldown.3238606171
Directory /workspace/40.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/40.gpio_stress_all.4116866829
Short name T361
Test name
Test status
Simulation time 14751538101 ps
CPU time 186.32 seconds
Started Jun 30 04:24:16 PM PDT 24
Finished Jun 30 04:27:23 PM PDT 24
Peak memory 198624 kb
Host smart-a9b7bc78-33e3-460d-acf0-9213545263d7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4116866829 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.
gpio_stress_all.4116866829
Directory /workspace/40.gpio_stress_all/latest

Test location /workspace/coverage/default/41.gpio_alert_test.149731366
Short name T511
Test name
Test status
Simulation time 17410443 ps
CPU time 0.55 seconds
Started Jun 30 04:24:08 PM PDT 24
Finished Jun 30 04:24:13 PM PDT 24
Peak memory 194632 kb
Host smart-aacc9955-b535-4994-b0c0-f2fea32e0149
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=149731366 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_alert_test.149731366
Directory /workspace/41.gpio_alert_test/latest

Test location /workspace/coverage/default/41.gpio_dout_din_regs_random_rw.2358114382
Short name T592
Test name
Test status
Simulation time 89704771 ps
CPU time 0.76 seconds
Started Jun 30 04:24:20 PM PDT 24
Finished Jun 30 04:24:21 PM PDT 24
Peak memory 196596 kb
Host smart-a68bfdad-ea5e-4c2f-a720-f82a3269cefd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2358114382 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_dout_din_regs_random_rw.2358114382
Directory /workspace/41.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/41.gpio_filter_stress.3991099707
Short name T500
Test name
Test status
Simulation time 79747262 ps
CPU time 3.75 seconds
Started Jun 30 04:24:25 PM PDT 24
Finished Jun 30 04:24:29 PM PDT 24
Peak memory 197160 kb
Host smart-bcda7dd1-458c-4d17-8f89-b33e1940dd3c
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3991099707 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_filter_stre
ss.3991099707
Directory /workspace/41.gpio_filter_stress/latest

Test location /workspace/coverage/default/41.gpio_full_random.676252197
Short name T334
Test name
Test status
Simulation time 77369908 ps
CPU time 0.95 seconds
Started Jun 30 04:24:07 PM PDT 24
Finished Jun 30 04:24:11 PM PDT 24
Peak memory 197048 kb
Host smart-41dd46ee-92cc-47f5-97fc-0a10ad25dbcf
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=676252197 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_full_random.676252197
Directory /workspace/41.gpio_full_random/latest

Test location /workspace/coverage/default/41.gpio_intr_rand_pgm.1511533010
Short name T343
Test name
Test status
Simulation time 93383388 ps
CPU time 1.22 seconds
Started Jun 30 04:24:07 PM PDT 24
Finished Jun 30 04:24:11 PM PDT 24
Peak memory 196452 kb
Host smart-077d10e4-d5f5-467c-b26f-3527bea7c029
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1511533010 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_intr_rand_pgm.1511533010
Directory /workspace/41.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/41.gpio_intr_with_filter_rand_intr_event.3194966087
Short name T344
Test name
Test status
Simulation time 246338860 ps
CPU time 2.4 seconds
Started Jun 30 04:24:09 PM PDT 24
Finished Jun 30 04:24:15 PM PDT 24
Peak memory 198384 kb
Host smart-ec6a7158-a90b-4c79-97d3-529f822a4768
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3194966087 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 41.gpio_intr_with_filter_rand_intr_event.3194966087
Directory /workspace/41.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/41.gpio_rand_intr_trigger.299682971
Short name T226
Test name
Test status
Simulation time 118329296 ps
CPU time 1.92 seconds
Started Jun 30 04:24:06 PM PDT 24
Finished Jun 30 04:24:12 PM PDT 24
Peak memory 197228 kb
Host smart-766a045b-9a91-4bfa-9e65-63db7f0c100e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=299682971 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_rand_intr_trigger.
299682971
Directory /workspace/41.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/41.gpio_random_dout_din.1057707565
Short name T205
Test name
Test status
Simulation time 27263589 ps
CPU time 0.73 seconds
Started Jun 30 04:24:08 PM PDT 24
Finished Jun 30 04:24:12 PM PDT 24
Peak memory 196024 kb
Host smart-0ccb5799-f5a3-420e-9747-b718f6b2e213
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1057707565 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_random_dout_din.1057707565
Directory /workspace/41.gpio_random_dout_din/latest

Test location /workspace/coverage/default/41.gpio_random_dout_din_no_pullup_pulldown.3370543582
Short name T223
Test name
Test status
Simulation time 69160813 ps
CPU time 0.64 seconds
Started Jun 30 04:24:04 PM PDT 24
Finished Jun 30 04:24:08 PM PDT 24
Peak memory 194712 kb
Host smart-7a6d24a1-808a-4754-8780-3529fdd64878
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3370543582 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_random_dout_din_no_pullu
p_pulldown.3370543582
Directory /workspace/41.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/41.gpio_random_long_reg_writes_reg_reads.276090364
Short name T20
Test name
Test status
Simulation time 118860134 ps
CPU time 1.62 seconds
Started Jun 30 04:24:20 PM PDT 24
Finished Jun 30 04:24:22 PM PDT 24
Peak memory 198300 kb
Host smart-106226c5-6836-40cd-a1d3-cf5e96f9e0f9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=276090364 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_ran
dom_long_reg_writes_reg_reads.276090364
Directory /workspace/41.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/41.gpio_smoke.3374826523
Short name T169
Test name
Test status
Simulation time 194939450 ps
CPU time 1.13 seconds
Started Jun 30 04:24:07 PM PDT 24
Finished Jun 30 04:24:19 PM PDT 24
Peak memory 197240 kb
Host smart-a87f5039-18be-45f6-9661-f666af598710
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3374826523 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_smoke.3374826523
Directory /workspace/41.gpio_smoke/latest

Test location /workspace/coverage/default/41.gpio_smoke_no_pullup_pulldown.2709627001
Short name T543
Test name
Test status
Simulation time 195221409 ps
CPU time 1.01 seconds
Started Jun 30 04:24:09 PM PDT 24
Finished Jun 30 04:24:13 PM PDT 24
Peak memory 196716 kb
Host smart-49a6eb5b-31f5-4707-b070-e1e8d352bee4
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2709627001 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_smoke_no_pullup_pulldown.2709627001
Directory /workspace/41.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/41.gpio_stress_all.1934162791
Short name T123
Test name
Test status
Simulation time 3950573036 ps
CPU time 96.31 seconds
Started Jun 30 04:24:03 PM PDT 24
Finished Jun 30 04:25:43 PM PDT 24
Peak memory 198608 kb
Host smart-4b21b389-aead-44cc-b451-47e21e1265c3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1934162791 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.
gpio_stress_all.1934162791
Directory /workspace/41.gpio_stress_all/latest

Test location /workspace/coverage/default/42.gpio_alert_test.305465602
Short name T53
Test name
Test status
Simulation time 24444246 ps
CPU time 0.54 seconds
Started Jun 30 04:24:11 PM PDT 24
Finished Jun 30 04:24:14 PM PDT 24
Peak memory 194440 kb
Host smart-53ed7fa5-bb53-4548-af21-9dbb90905846
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=305465602 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_alert_test.305465602
Directory /workspace/42.gpio_alert_test/latest

Test location /workspace/coverage/default/42.gpio_dout_din_regs_random_rw.4042999440
Short name T431
Test name
Test status
Simulation time 69291474 ps
CPU time 0.64 seconds
Started Jun 30 04:24:05 PM PDT 24
Finished Jun 30 04:24:09 PM PDT 24
Peak memory 195200 kb
Host smart-1a38508b-bb86-46f2-90ab-b4c98f04af35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4042999440 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_dout_din_regs_random_rw.4042999440
Directory /workspace/42.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/42.gpio_filter_stress.3408309725
Short name T663
Test name
Test status
Simulation time 754019951 ps
CPU time 9.92 seconds
Started Jun 30 04:24:20 PM PDT 24
Finished Jun 30 04:24:30 PM PDT 24
Peak memory 197424 kb
Host smart-d6359074-6fbc-4ca3-b2f7-d93bbbac801c
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3408309725 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_filter_stre
ss.3408309725
Directory /workspace/42.gpio_filter_stress/latest

Test location /workspace/coverage/default/42.gpio_full_random.3863987442
Short name T19
Test name
Test status
Simulation time 320719508 ps
CPU time 0.99 seconds
Started Jun 30 04:24:23 PM PDT 24
Finished Jun 30 04:24:24 PM PDT 24
Peak memory 196984 kb
Host smart-a7ef1e93-12a0-4728-9376-af77840d9c22
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3863987442 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_full_random.3863987442
Directory /workspace/42.gpio_full_random/latest

Test location /workspace/coverage/default/42.gpio_intr_rand_pgm.1391361203
Short name T710
Test name
Test status
Simulation time 34640163 ps
CPU time 0.77 seconds
Started Jun 30 04:24:01 PM PDT 24
Finished Jun 30 04:24:05 PM PDT 24
Peak memory 195808 kb
Host smart-78e81478-87d3-4f16-8aa1-609d73f9d3ca
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1391361203 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_intr_rand_pgm.1391361203
Directory /workspace/42.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/42.gpio_intr_with_filter_rand_intr_event.3821149520
Short name T475
Test name
Test status
Simulation time 91778641 ps
CPU time 3.58 seconds
Started Jun 30 04:24:40 PM PDT 24
Finished Jun 30 04:24:44 PM PDT 24
Peak memory 198548 kb
Host smart-6cb5276b-0de7-4998-8691-345d4644e056
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3821149520 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 42.gpio_intr_with_filter_rand_intr_event.3821149520
Directory /workspace/42.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/42.gpio_rand_intr_trigger.3903800542
Short name T326
Test name
Test status
Simulation time 101706839 ps
CPU time 2.08 seconds
Started Jun 30 04:24:24 PM PDT 24
Finished Jun 30 04:24:26 PM PDT 24
Peak memory 197496 kb
Host smart-7e6e041d-9bca-4ddb-b020-f113936ffe9a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3903800542 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_rand_intr_trigger
.3903800542
Directory /workspace/42.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/42.gpio_random_dout_din.2427745627
Short name T485
Test name
Test status
Simulation time 52974456 ps
CPU time 0.81 seconds
Started Jun 30 04:24:03 PM PDT 24
Finished Jun 30 04:24:07 PM PDT 24
Peak memory 196004 kb
Host smart-a8056b8e-91e0-4a76-a8f8-d47c91215672
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2427745627 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_random_dout_din.2427745627
Directory /workspace/42.gpio_random_dout_din/latest

Test location /workspace/coverage/default/42.gpio_random_dout_din_no_pullup_pulldown.2054235792
Short name T270
Test name
Test status
Simulation time 66246672 ps
CPU time 1.24 seconds
Started Jun 30 04:24:10 PM PDT 24
Finished Jun 30 04:24:14 PM PDT 24
Peak memory 197436 kb
Host smart-eef81cc3-c276-4f87-8ffb-0fef119be7f0
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2054235792 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_random_dout_din_no_pullu
p_pulldown.2054235792
Directory /workspace/42.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/42.gpio_random_long_reg_writes_reg_reads.317633805
Short name T164
Test name
Test status
Simulation time 84398713 ps
CPU time 1.83 seconds
Started Jun 30 04:24:10 PM PDT 24
Finished Jun 30 04:24:23 PM PDT 24
Peak memory 198460 kb
Host smart-ae57456d-0c33-4e9a-9bb9-ebf2b15ddecf
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=317633805 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_ran
dom_long_reg_writes_reg_reads.317633805
Directory /workspace/42.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/42.gpio_smoke.4154939375
Short name T309
Test name
Test status
Simulation time 334937016 ps
CPU time 1.55 seconds
Started Jun 30 04:24:00 PM PDT 24
Finished Jun 30 04:24:03 PM PDT 24
Peak memory 198516 kb
Host smart-85c14965-6bc4-48b8-8c10-b8e64eb64349
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4154939375 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_smoke.4154939375
Directory /workspace/42.gpio_smoke/latest

Test location /workspace/coverage/default/42.gpio_smoke_no_pullup_pulldown.2957061546
Short name T189
Test name
Test status
Simulation time 120961194 ps
CPU time 0.75 seconds
Started Jun 30 04:24:09 PM PDT 24
Finished Jun 30 04:24:14 PM PDT 24
Peak memory 195672 kb
Host smart-ff77b471-3f84-46d0-970d-ad09d92a191d
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2957061546 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_smoke_no_pullup_pulldown.2957061546
Directory /workspace/42.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/42.gpio_stress_all.172184351
Short name T118
Test name
Test status
Simulation time 5703678101 ps
CPU time 73.84 seconds
Started Jun 30 04:24:11 PM PDT 24
Finished Jun 30 04:25:28 PM PDT 24
Peak memory 198588 kb
Host smart-6c118067-f1ab-4372-b39f-94c7d787a500
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=172184351 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.g
pio_stress_all.172184351
Directory /workspace/42.gpio_stress_all/latest

Test location /workspace/coverage/default/42.gpio_stress_all_with_rand_reset.3338101885
Short name T34
Test name
Test status
Simulation time 46284417891 ps
CPU time 1015.44 seconds
Started Jun 30 04:24:09 PM PDT 24
Finished Jun 30 04:41:08 PM PDT 24
Peak memory 198748 kb
Host smart-0a1c204c-71d7-4a56-9034-920982626801
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3338101885 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_stress_all_with_rand_reset.3338101885
Directory /workspace/42.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.gpio_alert_test.2465408392
Short name T28
Test name
Test status
Simulation time 25048536 ps
CPU time 0.56 seconds
Started Jun 30 04:24:11 PM PDT 24
Finished Jun 30 04:24:14 PM PDT 24
Peak memory 194444 kb
Host smart-15b8f578-cb77-45a3-ab2a-ca202e90891a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2465408392 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_alert_test.2465408392
Directory /workspace/43.gpio_alert_test/latest

Test location /workspace/coverage/default/43.gpio_dout_din_regs_random_rw.3221984053
Short name T584
Test name
Test status
Simulation time 145094088 ps
CPU time 0.82 seconds
Started Jun 30 04:24:08 PM PDT 24
Finished Jun 30 04:24:12 PM PDT 24
Peak memory 197016 kb
Host smart-b18dafe6-a639-4174-a0cd-2cdac16de6d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3221984053 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_dout_din_regs_random_rw.3221984053
Directory /workspace/43.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/43.gpio_filter_stress.2548282720
Short name T490
Test name
Test status
Simulation time 958782429 ps
CPU time 12.03 seconds
Started Jun 30 04:24:42 PM PDT 24
Finished Jun 30 04:24:54 PM PDT 24
Peak memory 197476 kb
Host smart-e8f9e93c-5ab7-4d6d-b518-7fbede1dc135
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2548282720 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_filter_stre
ss.2548282720
Directory /workspace/43.gpio_filter_stress/latest

Test location /workspace/coverage/default/43.gpio_full_random.676702456
Short name T182
Test name
Test status
Simulation time 27417255 ps
CPU time 0.68 seconds
Started Jun 30 04:24:38 PM PDT 24
Finished Jun 30 04:24:39 PM PDT 24
Peak memory 195132 kb
Host smart-6fda37c2-af3e-4178-a861-59d1dd13fb9a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=676702456 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_full_random.676702456
Directory /workspace/43.gpio_full_random/latest

Test location /workspace/coverage/default/43.gpio_intr_rand_pgm.2373189259
Short name T659
Test name
Test status
Simulation time 47748664 ps
CPU time 0.74 seconds
Started Jun 30 04:24:25 PM PDT 24
Finished Jun 30 04:24:26 PM PDT 24
Peak memory 196128 kb
Host smart-1a841b08-1180-4a2f-a4e8-1115cb123adb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2373189259 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_intr_rand_pgm.2373189259
Directory /workspace/43.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/43.gpio_intr_with_filter_rand_intr_event.1299619376
Short name T159
Test name
Test status
Simulation time 326027793 ps
CPU time 3.06 seconds
Started Jun 30 04:24:15 PM PDT 24
Finished Jun 30 04:24:19 PM PDT 24
Peak memory 198464 kb
Host smart-5dd3654e-813d-4bf1-9425-8399f35955a8
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1299619376 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 43.gpio_intr_with_filter_rand_intr_event.1299619376
Directory /workspace/43.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/43.gpio_rand_intr_trigger.393852014
Short name T451
Test name
Test status
Simulation time 282703765 ps
CPU time 1.63 seconds
Started Jun 30 04:24:11 PM PDT 24
Finished Jun 30 04:24:15 PM PDT 24
Peak memory 196520 kb
Host smart-b0dcbb3b-8288-46de-823a-96dca15b6d90
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=393852014 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_rand_intr_trigger.
393852014
Directory /workspace/43.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/43.gpio_random_dout_din.1862830991
Short name T614
Test name
Test status
Simulation time 109565237 ps
CPU time 0.76 seconds
Started Jun 30 04:24:07 PM PDT 24
Finished Jun 30 04:24:11 PM PDT 24
Peak memory 196652 kb
Host smart-176726f5-9d99-4e06-b1df-cdf9c7e187e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1862830991 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_random_dout_din.1862830991
Directory /workspace/43.gpio_random_dout_din/latest

Test location /workspace/coverage/default/43.gpio_random_dout_din_no_pullup_pulldown.2409687304
Short name T655
Test name
Test status
Simulation time 127785390 ps
CPU time 1.26 seconds
Started Jun 30 04:24:19 PM PDT 24
Finished Jun 30 04:24:21 PM PDT 24
Peak memory 196316 kb
Host smart-e0fcec95-3ee1-4daf-aec0-e384b9253ced
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2409687304 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_random_dout_din_no_pullu
p_pulldown.2409687304
Directory /workspace/43.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/43.gpio_random_long_reg_writes_reg_reads.4049146499
Short name T519
Test name
Test status
Simulation time 908578578 ps
CPU time 2.51 seconds
Started Jun 30 04:24:11 PM PDT 24
Finished Jun 30 04:24:16 PM PDT 24
Peak memory 198460 kb
Host smart-bc770329-fa5d-48ce-b7d6-77d0e9d0d716
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4049146499 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_ra
ndom_long_reg_writes_reg_reads.4049146499
Directory /workspace/43.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/43.gpio_smoke.2130625374
Short name T700
Test name
Test status
Simulation time 200142098 ps
CPU time 1.2 seconds
Started Jun 30 04:24:18 PM PDT 24
Finished Jun 30 04:24:20 PM PDT 24
Peak memory 197284 kb
Host smart-226d1327-895e-4fe3-a242-5dcfd3575bc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2130625374 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_smoke.2130625374
Directory /workspace/43.gpio_smoke/latest

Test location /workspace/coverage/default/43.gpio_smoke_no_pullup_pulldown.2163373392
Short name T25
Test name
Test status
Simulation time 43717637 ps
CPU time 0.83 seconds
Started Jun 30 04:24:08 PM PDT 24
Finished Jun 30 04:24:12 PM PDT 24
Peak memory 196524 kb
Host smart-5e0d9ad7-0117-4419-8077-436c273ab0cb
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2163373392 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_smoke_no_pullup_pulldown.2163373392
Directory /workspace/43.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/43.gpio_stress_all.384966390
Short name T230
Test name
Test status
Simulation time 7761788692 ps
CPU time 190.8 seconds
Started Jun 30 04:24:11 PM PDT 24
Finished Jun 30 04:27:24 PM PDT 24
Peak memory 198580 kb
Host smart-f0841176-93fa-4341-9f15-9af9c0681056
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=384966390 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.g
pio_stress_all.384966390
Directory /workspace/43.gpio_stress_all/latest

Test location /workspace/coverage/default/44.gpio_alert_test.2312416247
Short name T311
Test name
Test status
Simulation time 14971563 ps
CPU time 0.55 seconds
Started Jun 30 04:24:23 PM PDT 24
Finished Jun 30 04:24:24 PM PDT 24
Peak memory 194660 kb
Host smart-5de8a475-1a39-4984-859d-daaab44560a4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2312416247 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_alert_test.2312416247
Directory /workspace/44.gpio_alert_test/latest

Test location /workspace/coverage/default/44.gpio_dout_din_regs_random_rw.267414383
Short name T628
Test name
Test status
Simulation time 86879152 ps
CPU time 0.83 seconds
Started Jun 30 04:24:24 PM PDT 24
Finished Jun 30 04:24:25 PM PDT 24
Peak memory 196972 kb
Host smart-d3445b92-60ee-4f40-9ab1-33a11db8ef88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=267414383 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_dout_din_regs_random_rw.267414383
Directory /workspace/44.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/44.gpio_filter_stress.3585908713
Short name T492
Test name
Test status
Simulation time 1514183323 ps
CPU time 20.02 seconds
Started Jun 30 04:24:40 PM PDT 24
Finished Jun 30 04:25:01 PM PDT 24
Peak memory 198472 kb
Host smart-100514c4-8a89-4b07-a4e9-2574679aa6e5
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3585908713 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_filter_stre
ss.3585908713
Directory /workspace/44.gpio_filter_stress/latest

Test location /workspace/coverage/default/44.gpio_full_random.2988689833
Short name T573
Test name
Test status
Simulation time 49667525 ps
CPU time 0.82 seconds
Started Jun 30 04:24:47 PM PDT 24
Finished Jun 30 04:24:49 PM PDT 24
Peak memory 196440 kb
Host smart-543eee70-d0e1-49d1-8f49-a58e886a0f10
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2988689833 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_full_random.2988689833
Directory /workspace/44.gpio_full_random/latest

Test location /workspace/coverage/default/44.gpio_intr_rand_pgm.3728454773
Short name T425
Test name
Test status
Simulation time 304132134 ps
CPU time 1.33 seconds
Started Jun 30 04:24:27 PM PDT 24
Finished Jun 30 04:24:29 PM PDT 24
Peak memory 197492 kb
Host smart-41a15177-5480-47e4-840d-04ac651be24a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3728454773 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_intr_rand_pgm.3728454773
Directory /workspace/44.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/44.gpio_intr_with_filter_rand_intr_event.911897695
Short name T356
Test name
Test status
Simulation time 378670625 ps
CPU time 2.88 seconds
Started Jun 30 04:24:37 PM PDT 24
Finished Jun 30 04:24:41 PM PDT 24
Peak memory 198544 kb
Host smart-d17e2b14-f330-4a02-8697-062dd980af87
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=911897695 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 44.gpio_intr_with_filter_rand_intr_event.911897695
Directory /workspace/44.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/44.gpio_rand_intr_trigger.619508669
Short name T589
Test name
Test status
Simulation time 547251146 ps
CPU time 2.83 seconds
Started Jun 30 04:24:10 PM PDT 24
Finished Jun 30 04:24:16 PM PDT 24
Peak memory 197800 kb
Host smart-80d3e8b2-dff0-4c42-b218-76402926fbf1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=619508669 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_rand_intr_trigger.
619508669
Directory /workspace/44.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/44.gpio_random_dout_din.3564753363
Short name T513
Test name
Test status
Simulation time 136602190 ps
CPU time 1.14 seconds
Started Jun 30 04:24:11 PM PDT 24
Finished Jun 30 04:24:15 PM PDT 24
Peak memory 197412 kb
Host smart-c8149117-508b-432d-85e2-fa8e0c4e6f43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3564753363 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_random_dout_din.3564753363
Directory /workspace/44.gpio_random_dout_din/latest

Test location /workspace/coverage/default/44.gpio_random_dout_din_no_pullup_pulldown.2249230313
Short name T94
Test name
Test status
Simulation time 27001821 ps
CPU time 0.92 seconds
Started Jun 30 04:24:04 PM PDT 24
Finished Jun 30 04:24:08 PM PDT 24
Peak memory 197228 kb
Host smart-3b32022a-abfe-4a01-a435-425b50dfa54c
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2249230313 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_random_dout_din_no_pullu
p_pulldown.2249230313
Directory /workspace/44.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/44.gpio_random_long_reg_writes_reg_reads.453030319
Short name T693
Test name
Test status
Simulation time 361268351 ps
CPU time 6.01 seconds
Started Jun 30 04:24:15 PM PDT 24
Finished Jun 30 04:24:27 PM PDT 24
Peak memory 198904 kb
Host smart-683723f7-40f2-488a-aca2-0982efc534aa
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=453030319 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_ran
dom_long_reg_writes_reg_reads.453030319
Directory /workspace/44.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/44.gpio_smoke.807315109
Short name T420
Test name
Test status
Simulation time 48766984 ps
CPU time 1.21 seconds
Started Jun 30 04:24:27 PM PDT 24
Finished Jun 30 04:24:28 PM PDT 24
Peak memory 196900 kb
Host smart-7ed188f9-7bf0-4187-8a22-84f44fde2af7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=807315109 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_smoke.807315109
Directory /workspace/44.gpio_smoke/latest

Test location /workspace/coverage/default/44.gpio_smoke_no_pullup_pulldown.3913297949
Short name T238
Test name
Test status
Simulation time 23687691 ps
CPU time 0.76 seconds
Started Jun 30 04:24:11 PM PDT 24
Finished Jun 30 04:24:15 PM PDT 24
Peak memory 195524 kb
Host smart-a493b21e-1edc-4a52-bbfa-b02d42a1af11
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3913297949 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_smoke_no_pullup_pulldown.3913297949
Directory /workspace/44.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/44.gpio_stress_all.3521268904
Short name T403
Test name
Test status
Simulation time 16593817040 ps
CPU time 221.31 seconds
Started Jun 30 04:24:13 PM PDT 24
Finished Jun 30 04:27:56 PM PDT 24
Peak memory 198576 kb
Host smart-426708ef-44a1-4c90-96a9-e65cd3babe6d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3521268904 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.
gpio_stress_all.3521268904
Directory /workspace/44.gpio_stress_all/latest

Test location /workspace/coverage/default/44.gpio_stress_all_with_rand_reset.1837618522
Short name T92
Test name
Test status
Simulation time 67125064621 ps
CPU time 1042.52 seconds
Started Jun 30 04:24:30 PM PDT 24
Finished Jun 30 04:41:53 PM PDT 24
Peak memory 198660 kb
Host smart-8f9fbed0-6bd1-4deb-8b5d-ced33287a5ff
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1837618522 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_stress_all_with_rand_reset.1837618522
Directory /workspace/44.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.gpio_alert_test.1909340003
Short name T167
Test name
Test status
Simulation time 47617635 ps
CPU time 0.6 seconds
Started Jun 30 04:24:55 PM PDT 24
Finished Jun 30 04:24:56 PM PDT 24
Peak memory 195424 kb
Host smart-15526cc0-5b9c-43df-a3c1-a093c880259e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1909340003 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_alert_test.1909340003
Directory /workspace/45.gpio_alert_test/latest

Test location /workspace/coverage/default/45.gpio_dout_din_regs_random_rw.2885712374
Short name T548
Test name
Test status
Simulation time 32820836 ps
CPU time 0.73 seconds
Started Jun 30 04:24:25 PM PDT 24
Finished Jun 30 04:24:31 PM PDT 24
Peak memory 195664 kb
Host smart-52ce5849-76f2-421b-8cfa-bb50614b3c63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2885712374 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_dout_din_regs_random_rw.2885712374
Directory /workspace/45.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/45.gpio_filter_stress.5306701
Short name T379
Test name
Test status
Simulation time 1597330612 ps
CPU time 19.28 seconds
Started Jun 30 04:24:12 PM PDT 24
Finished Jun 30 04:24:33 PM PDT 24
Peak memory 197416 kb
Host smart-51defada-a3f0-46ba-a006-4f2524c304a9
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=5306701 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter_s
tress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_filter_stress.5306701
Directory /workspace/45.gpio_filter_stress/latest

Test location /workspace/coverage/default/45.gpio_full_random.208724466
Short name T250
Test name
Test status
Simulation time 308938351 ps
CPU time 0.85 seconds
Started Jun 30 04:24:26 PM PDT 24
Finished Jun 30 04:24:28 PM PDT 24
Peak memory 197584 kb
Host smart-19dc710c-f664-46e8-858a-679379a2ae1f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=208724466 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_full_random.208724466
Directory /workspace/45.gpio_full_random/latest

Test location /workspace/coverage/default/45.gpio_intr_rand_pgm.446062860
Short name T220
Test name
Test status
Simulation time 61606078 ps
CPU time 0.92 seconds
Started Jun 30 04:24:06 PM PDT 24
Finished Jun 30 04:24:11 PM PDT 24
Peak memory 196356 kb
Host smart-c95aa766-fc3e-4000-9b9c-f69785bcbd9a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=446062860 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_intr_rand_pgm.446062860
Directory /workspace/45.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/45.gpio_intr_with_filter_rand_intr_event.4246941007
Short name T578
Test name
Test status
Simulation time 69709641 ps
CPU time 2.68 seconds
Started Jun 30 04:24:38 PM PDT 24
Finished Jun 30 04:24:42 PM PDT 24
Peak memory 198568 kb
Host smart-7e783664-6254-4e73-92f7-811e01d41d40
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4246941007 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 45.gpio_intr_with_filter_rand_intr_event.4246941007
Directory /workspace/45.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/45.gpio_rand_intr_trigger.3464944281
Short name T190
Test name
Test status
Simulation time 216418073 ps
CPU time 2.84 seconds
Started Jun 30 04:24:18 PM PDT 24
Finished Jun 30 04:24:22 PM PDT 24
Peak memory 198488 kb
Host smart-059a196f-e721-4107-ae86-472f9ea7a3a3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3464944281 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_rand_intr_trigger
.3464944281
Directory /workspace/45.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/45.gpio_random_dout_din.2839799866
Short name T652
Test name
Test status
Simulation time 173512340 ps
CPU time 0.75 seconds
Started Jun 30 04:24:11 PM PDT 24
Finished Jun 30 04:24:15 PM PDT 24
Peak memory 195924 kb
Host smart-81557bd2-3699-4995-b407-7dff9177c817
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2839799866 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_random_dout_din.2839799866
Directory /workspace/45.gpio_random_dout_din/latest

Test location /workspace/coverage/default/45.gpio_random_dout_din_no_pullup_pulldown.2458542958
Short name T294
Test name
Test status
Simulation time 46287246 ps
CPU time 0.6 seconds
Started Jun 30 04:24:07 PM PDT 24
Finished Jun 30 04:24:11 PM PDT 24
Peak memory 194768 kb
Host smart-887c6080-1ef4-412b-95e4-f048f775dd6c
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2458542958 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_random_dout_din_no_pullu
p_pulldown.2458542958
Directory /workspace/45.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/45.gpio_random_long_reg_writes_reg_reads.749713638
Short name T305
Test name
Test status
Simulation time 1014146482 ps
CPU time 5.82 seconds
Started Jun 30 04:24:15 PM PDT 24
Finished Jun 30 04:24:22 PM PDT 24
Peak memory 198452 kb
Host smart-d2627afa-52e3-4614-ab9c-3c9629e92a4e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=749713638 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_ran
dom_long_reg_writes_reg_reads.749713638
Directory /workspace/45.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/45.gpio_smoke.3464153290
Short name T653
Test name
Test status
Simulation time 144059984 ps
CPU time 1.08 seconds
Started Jun 30 04:24:14 PM PDT 24
Finished Jun 30 04:24:17 PM PDT 24
Peak memory 196904 kb
Host smart-f9846fa4-782d-41f2-ad1a-324ccccff60e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3464153290 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_smoke.3464153290
Directory /workspace/45.gpio_smoke/latest

Test location /workspace/coverage/default/45.gpio_smoke_no_pullup_pulldown.214459827
Short name T391
Test name
Test status
Simulation time 82888406 ps
CPU time 0.67 seconds
Started Jun 30 04:24:08 PM PDT 24
Finished Jun 30 04:24:12 PM PDT 24
Peak memory 195700 kb
Host smart-0f1bf122-64ce-4f32-ad48-de5df8b9f4a0
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=214459827 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_smoke_no_pullup_pulldown.214459827
Directory /workspace/45.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/45.gpio_stress_all.293272639
Short name T553
Test name
Test status
Simulation time 22349631931 ps
CPU time 144.98 seconds
Started Jun 30 04:24:25 PM PDT 24
Finished Jun 30 04:26:50 PM PDT 24
Peak memory 198592 kb
Host smart-f439d521-ec47-4ac4-b87c-69e167cc8f04
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=293272639 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.g
pio_stress_all.293272639
Directory /workspace/45.gpio_stress_all/latest

Test location /workspace/coverage/default/45.gpio_stress_all_with_rand_reset.1696339850
Short name T56
Test name
Test status
Simulation time 43476360662 ps
CPU time 935.68 seconds
Started Jun 30 04:24:23 PM PDT 24
Finished Jun 30 04:39:59 PM PDT 24
Peak memory 198744 kb
Host smart-1a697c28-7e3c-4bd1-a953-f5940d07b722
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1696339850 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_stress_all_with_rand_reset.1696339850
Directory /workspace/45.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.gpio_alert_test.2611245371
Short name T354
Test name
Test status
Simulation time 37639492 ps
CPU time 0.55 seconds
Started Jun 30 04:24:16 PM PDT 24
Finished Jun 30 04:24:22 PM PDT 24
Peak memory 195140 kb
Host smart-f855ff52-c62f-4fca-98b2-8fdfef348a0a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2611245371 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_alert_test.2611245371
Directory /workspace/46.gpio_alert_test/latest

Test location /workspace/coverage/default/46.gpio_dout_din_regs_random_rw.4062255180
Short name T126
Test name
Test status
Simulation time 32080560 ps
CPU time 0.85 seconds
Started Jun 30 04:24:17 PM PDT 24
Finished Jun 30 04:24:19 PM PDT 24
Peak memory 196424 kb
Host smart-76a17617-7b7f-4250-9dac-67b746538215
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4062255180 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_dout_din_regs_random_rw.4062255180
Directory /workspace/46.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/46.gpio_filter_stress.3795822833
Short name T48
Test name
Test status
Simulation time 845548199 ps
CPU time 23.33 seconds
Started Jun 30 04:24:14 PM PDT 24
Finished Jun 30 04:24:39 PM PDT 24
Peak memory 197384 kb
Host smart-74085c5e-43c0-4803-8d48-a9ffe0a637e8
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3795822833 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_filter_stre
ss.3795822833
Directory /workspace/46.gpio_filter_stress/latest

Test location /workspace/coverage/default/46.gpio_full_random.3267623219
Short name T680
Test name
Test status
Simulation time 57475855 ps
CPU time 0.85 seconds
Started Jun 30 04:24:13 PM PDT 24
Finished Jun 30 04:24:16 PM PDT 24
Peak memory 196504 kb
Host smart-c4d06a4a-750f-41e3-b692-bfd28566bd86
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3267623219 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_full_random.3267623219
Directory /workspace/46.gpio_full_random/latest

Test location /workspace/coverage/default/46.gpio_intr_rand_pgm.4039998360
Short name T411
Test name
Test status
Simulation time 174259397 ps
CPU time 0.88 seconds
Started Jun 30 04:24:23 PM PDT 24
Finished Jun 30 04:24:24 PM PDT 24
Peak memory 196536 kb
Host smart-9543a55a-685b-4eca-9b9c-f7bee7fc18e6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4039998360 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_intr_rand_pgm.4039998360
Directory /workspace/46.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/46.gpio_intr_with_filter_rand_intr_event.3164172486
Short name T249
Test name
Test status
Simulation time 22736921 ps
CPU time 0.94 seconds
Started Jun 30 04:24:13 PM PDT 24
Finished Jun 30 04:24:16 PM PDT 24
Peak memory 196708 kb
Host smart-21f00c09-2c93-4894-8b0a-2936a454cf26
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3164172486 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 46.gpio_intr_with_filter_rand_intr_event.3164172486
Directory /workspace/46.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/46.gpio_rand_intr_trigger.1695953510
Short name T458
Test name
Test status
Simulation time 105805247 ps
CPU time 2.8 seconds
Started Jun 30 04:24:02 PM PDT 24
Finished Jun 30 04:24:07 PM PDT 24
Peak memory 196960 kb
Host smart-1ff6c55d-8684-440f-a35b-e4e89de3df53
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1695953510 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_rand_intr_trigger
.1695953510
Directory /workspace/46.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/46.gpio_random_dout_din.3763451848
Short name T703
Test name
Test status
Simulation time 31449886 ps
CPU time 0.64 seconds
Started Jun 30 04:24:14 PM PDT 24
Finished Jun 30 04:24:16 PM PDT 24
Peak memory 195592 kb
Host smart-93005a60-8981-4a13-9194-39bb8c8b8b91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3763451848 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_random_dout_din.3763451848
Directory /workspace/46.gpio_random_dout_din/latest

Test location /workspace/coverage/default/46.gpio_random_dout_din_no_pullup_pulldown.1353969014
Short name T125
Test name
Test status
Simulation time 45094528 ps
CPU time 0.71 seconds
Started Jun 30 04:24:07 PM PDT 24
Finished Jun 30 04:24:12 PM PDT 24
Peak memory 195900 kb
Host smart-194a0687-92a8-4fb3-a32f-c76b846a6cb2
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1353969014 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_random_dout_din_no_pullu
p_pulldown.1353969014
Directory /workspace/46.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/46.gpio_random_long_reg_writes_reg_reads.1386879207
Short name T704
Test name
Test status
Simulation time 163791190 ps
CPU time 2.66 seconds
Started Jun 30 04:24:06 PM PDT 24
Finished Jun 30 04:24:13 PM PDT 24
Peak memory 198376 kb
Host smart-b45ef05a-9b94-40aa-bb16-1fafc5a3075b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1386879207 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_ra
ndom_long_reg_writes_reg_reads.1386879207
Directory /workspace/46.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/46.gpio_smoke.1490299303
Short name T231
Test name
Test status
Simulation time 101122098 ps
CPU time 1.45 seconds
Started Jun 30 04:24:13 PM PDT 24
Finished Jun 30 04:24:16 PM PDT 24
Peak memory 198476 kb
Host smart-fc43b574-ac5a-4b11-838a-0cd8d10c59ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1490299303 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_smoke.1490299303
Directory /workspace/46.gpio_smoke/latest

Test location /workspace/coverage/default/46.gpio_smoke_no_pullup_pulldown.1424582988
Short name T280
Test name
Test status
Simulation time 109970480 ps
CPU time 0.79 seconds
Started Jun 30 04:24:12 PM PDT 24
Finished Jun 30 04:24:15 PM PDT 24
Peak memory 196328 kb
Host smart-dd510565-7b1b-4571-ac4a-314480579656
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1424582988 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_smoke_no_pullup_pulldown.1424582988
Directory /workspace/46.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/46.gpio_stress_all.1733356454
Short name T6
Test name
Test status
Simulation time 62002216903 ps
CPU time 154.89 seconds
Started Jun 30 04:24:11 PM PDT 24
Finished Jun 30 04:26:48 PM PDT 24
Peak memory 198596 kb
Host smart-bea291d6-75cc-4119-9956-409d351f213d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1733356454 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.
gpio_stress_all.1733356454
Directory /workspace/46.gpio_stress_all/latest

Test location /workspace/coverage/default/46.gpio_stress_all_with_rand_reset.3222673485
Short name T60
Test name
Test status
Simulation time 419398971941 ps
CPU time 2054.91 seconds
Started Jun 30 04:24:15 PM PDT 24
Finished Jun 30 04:58:32 PM PDT 24
Peak memory 198708 kb
Host smart-09504587-a848-41d3-880b-d688b3fa54b9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3222673485 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_stress_all_with_rand_reset.3222673485
Directory /workspace/46.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.gpio_alert_test.1863771642
Short name T514
Test name
Test status
Simulation time 24596288 ps
CPU time 0.56 seconds
Started Jun 30 04:24:18 PM PDT 24
Finished Jun 30 04:24:19 PM PDT 24
Peak memory 194440 kb
Host smart-891e221b-c8df-4a6e-9170-02932c20ad70
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1863771642 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_alert_test.1863771642
Directory /workspace/47.gpio_alert_test/latest

Test location /workspace/coverage/default/47.gpio_dout_din_regs_random_rw.2080274637
Short name T515
Test name
Test status
Simulation time 28523155 ps
CPU time 0.92 seconds
Started Jun 30 04:24:29 PM PDT 24
Finished Jun 30 04:24:36 PM PDT 24
Peak memory 197732 kb
Host smart-8f39ae13-0d22-4ad8-a387-cb8d0cd27907
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2080274637 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_dout_din_regs_random_rw.2080274637
Directory /workspace/47.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/47.gpio_filter_stress.944817207
Short name T702
Test name
Test status
Simulation time 612721899 ps
CPU time 16.49 seconds
Started Jun 30 04:24:14 PM PDT 24
Finished Jun 30 04:24:32 PM PDT 24
Peak memory 198396 kb
Host smart-6913b886-6c6e-40e4-9f57-36e0148628a5
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=944817207 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_filter_stres
s.944817207
Directory /workspace/47.gpio_filter_stress/latest

Test location /workspace/coverage/default/47.gpio_full_random.4068655513
Short name T695
Test name
Test status
Simulation time 59688506 ps
CPU time 0.83 seconds
Started Jun 30 04:24:45 PM PDT 24
Finished Jun 30 04:24:46 PM PDT 24
Peak memory 196444 kb
Host smart-cfecd376-7e5d-4713-b0b1-0df0984edc85
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4068655513 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_full_random.4068655513
Directory /workspace/47.gpio_full_random/latest

Test location /workspace/coverage/default/47.gpio_intr_rand_pgm.1134249769
Short name T453
Test name
Test status
Simulation time 106359858 ps
CPU time 0.98 seconds
Started Jun 30 04:24:15 PM PDT 24
Finished Jun 30 04:24:17 PM PDT 24
Peak memory 196624 kb
Host smart-32a29511-ddf1-4cd9-96b1-e9c0801542bb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1134249769 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_intr_rand_pgm.1134249769
Directory /workspace/47.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/47.gpio_intr_with_filter_rand_intr_event.2011689519
Short name T101
Test name
Test status
Simulation time 142352465 ps
CPU time 2.54 seconds
Started Jun 30 04:24:41 PM PDT 24
Finished Jun 30 04:24:44 PM PDT 24
Peak memory 198464 kb
Host smart-c06c547e-bff7-4a0d-97f1-d77e7f0f0827
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2011689519 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 47.gpio_intr_with_filter_rand_intr_event.2011689519
Directory /workspace/47.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/47.gpio_rand_intr_trigger.251418925
Short name T638
Test name
Test status
Simulation time 148962549 ps
CPU time 0.91 seconds
Started Jun 30 04:24:38 PM PDT 24
Finished Jun 30 04:24:39 PM PDT 24
Peak memory 196036 kb
Host smart-9811ef8f-3358-4080-bf9d-bef7277bebef
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=251418925 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_rand_intr_trigger.
251418925
Directory /workspace/47.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/47.gpio_random_dout_din.2007450370
Short name T679
Test name
Test status
Simulation time 66442649 ps
CPU time 1.15 seconds
Started Jun 30 04:24:19 PM PDT 24
Finished Jun 30 04:24:21 PM PDT 24
Peak memory 198536 kb
Host smart-fd8e2a8c-3146-45a0-906b-0fbac098e2e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2007450370 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_random_dout_din.2007450370
Directory /workspace/47.gpio_random_dout_din/latest

Test location /workspace/coverage/default/47.gpio_random_dout_din_no_pullup_pulldown.2240973820
Short name T12
Test name
Test status
Simulation time 882295002 ps
CPU time 1.15 seconds
Started Jun 30 04:24:15 PM PDT 24
Finished Jun 30 04:24:18 PM PDT 24
Peak memory 197488 kb
Host smart-6a7a6046-ffa1-4f4f-8ea9-c0f068cd17b5
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2240973820 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_random_dout_din_no_pullu
p_pulldown.2240973820
Directory /workspace/47.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/47.gpio_random_long_reg_writes_reg_reads.3518772508
Short name T298
Test name
Test status
Simulation time 3783226348 ps
CPU time 6.31 seconds
Started Jun 30 04:24:10 PM PDT 24
Finished Jun 30 04:24:19 PM PDT 24
Peak memory 198536 kb
Host smart-8ecc8f3c-293c-4750-856a-1cb92fba1381
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3518772508 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_ra
ndom_long_reg_writes_reg_reads.3518772508
Directory /workspace/47.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/47.gpio_smoke.1756436039
Short name T621
Test name
Test status
Simulation time 83433555 ps
CPU time 1.21 seconds
Started Jun 30 04:24:05 PM PDT 24
Finished Jun 30 04:24:10 PM PDT 24
Peak memory 197356 kb
Host smart-2c06376c-15a2-4454-b758-b1529ccfaee9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1756436039 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_smoke.1756436039
Directory /workspace/47.gpio_smoke/latest

Test location /workspace/coverage/default/47.gpio_smoke_no_pullup_pulldown.3609699451
Short name T527
Test name
Test status
Simulation time 49583722 ps
CPU time 0.9 seconds
Started Jun 30 04:24:02 PM PDT 24
Finished Jun 30 04:24:06 PM PDT 24
Peak memory 196732 kb
Host smart-f3e0c832-4f6c-4bb6-9003-7095f305d220
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3609699451 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_smoke_no_pullup_pulldown.3609699451
Directory /workspace/47.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/47.gpio_stress_all.1017005682
Short name T377
Test name
Test status
Simulation time 3388387385 ps
CPU time 79.46 seconds
Started Jun 30 04:24:10 PM PDT 24
Finished Jun 30 04:25:33 PM PDT 24
Peak memory 198560 kb
Host smart-04dc4bda-b141-4298-9f4a-648e1758be1c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1017005682 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.
gpio_stress_all.1017005682
Directory /workspace/47.gpio_stress_all/latest

Test location /workspace/coverage/default/47.gpio_stress_all_with_rand_reset.2042108660
Short name T58
Test name
Test status
Simulation time 76395806967 ps
CPU time 465.28 seconds
Started Jun 30 04:24:22 PM PDT 24
Finished Jun 30 04:32:07 PM PDT 24
Peak memory 198700 kb
Host smart-9dd53a6e-f923-413c-8d65-52d729fcce3e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2042108660 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_stress_all_with_rand_reset.2042108660
Directory /workspace/47.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.gpio_alert_test.3152951762
Short name T539
Test name
Test status
Simulation time 45744339 ps
CPU time 0.55 seconds
Started Jun 30 04:24:16 PM PDT 24
Finished Jun 30 04:24:22 PM PDT 24
Peak memory 194476 kb
Host smart-d07e3fbf-8e96-48c3-a606-b9ba248e840c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3152951762 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_alert_test.3152951762
Directory /workspace/48.gpio_alert_test/latest

Test location /workspace/coverage/default/48.gpio_dout_din_regs_random_rw.3091114436
Short name T385
Test name
Test status
Simulation time 44349976 ps
CPU time 0.73 seconds
Started Jun 30 04:24:19 PM PDT 24
Finished Jun 30 04:24:20 PM PDT 24
Peak memory 195724 kb
Host smart-45a7252a-0af5-4745-88fc-85c19342ee65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3091114436 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_dout_din_regs_random_rw.3091114436
Directory /workspace/48.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/48.gpio_filter_stress.1135809919
Short name T419
Test name
Test status
Simulation time 418528872 ps
CPU time 12.13 seconds
Started Jun 30 04:24:10 PM PDT 24
Finished Jun 30 04:24:25 PM PDT 24
Peak memory 197216 kb
Host smart-032e8939-34b0-4b28-91a3-eb161a5c11cb
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1135809919 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_filter_stre
ss.1135809919
Directory /workspace/48.gpio_filter_stress/latest

Test location /workspace/coverage/default/48.gpio_full_random.2621483637
Short name T580
Test name
Test status
Simulation time 122604130 ps
CPU time 0.61 seconds
Started Jun 30 04:24:32 PM PDT 24
Finished Jun 30 04:24:33 PM PDT 24
Peak memory 194960 kb
Host smart-1e9a67d6-6904-4bb7-9ef2-be2b05f24cc4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2621483637 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_full_random.2621483637
Directory /workspace/48.gpio_full_random/latest

Test location /workspace/coverage/default/48.gpio_intr_rand_pgm.1019420408
Short name T619
Test name
Test status
Simulation time 53523505 ps
CPU time 0.91 seconds
Started Jun 30 04:24:24 PM PDT 24
Finished Jun 30 04:24:25 PM PDT 24
Peak memory 197236 kb
Host smart-6f26222a-f34c-4f00-9ccc-e9270e0a0f9f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1019420408 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_intr_rand_pgm.1019420408
Directory /workspace/48.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/48.gpio_intr_with_filter_rand_intr_event.1096228200
Short name T145
Test name
Test status
Simulation time 21870195 ps
CPU time 0.92 seconds
Started Jun 30 04:24:20 PM PDT 24
Finished Jun 30 04:24:21 PM PDT 24
Peak memory 196608 kb
Host smart-6bbd05fa-dfd8-414e-851c-26cfb1c21e93
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1096228200 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 48.gpio_intr_with_filter_rand_intr_event.1096228200
Directory /workspace/48.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/48.gpio_rand_intr_trigger.3479223826
Short name T666
Test name
Test status
Simulation time 589804343 ps
CPU time 3.33 seconds
Started Jun 30 04:24:16 PM PDT 24
Finished Jun 30 04:24:20 PM PDT 24
Peak memory 198488 kb
Host smart-905cbd80-f9a4-4d04-867c-ec4dd16ec2fd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3479223826 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_rand_intr_trigger
.3479223826
Directory /workspace/48.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/48.gpio_random_dout_din.2332713669
Short name T260
Test name
Test status
Simulation time 74914808 ps
CPU time 1.22 seconds
Started Jun 30 04:24:47 PM PDT 24
Finished Jun 30 04:24:48 PM PDT 24
Peak memory 197488 kb
Host smart-7d0b7381-46f9-4ef8-8644-971609b50362
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2332713669 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_random_dout_din.2332713669
Directory /workspace/48.gpio_random_dout_din/latest

Test location /workspace/coverage/default/48.gpio_random_dout_din_no_pullup_pulldown.4250372756
Short name T400
Test name
Test status
Simulation time 34236366 ps
CPU time 0.78 seconds
Started Jun 30 04:24:35 PM PDT 24
Finished Jun 30 04:24:36 PM PDT 24
Peak memory 195800 kb
Host smart-894663a4-85d9-4d26-be8a-3bb15a668db2
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4250372756 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_random_dout_din_no_pullu
p_pulldown.4250372756
Directory /workspace/48.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/48.gpio_random_long_reg_writes_reg_reads.1226415000
Short name T533
Test name
Test status
Simulation time 199806164 ps
CPU time 4.25 seconds
Started Jun 30 04:24:09 PM PDT 24
Finished Jun 30 04:24:17 PM PDT 24
Peak memory 198384 kb
Host smart-728e6872-789b-45b9-abff-52d4753d3dfb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1226415000 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_ra
ndom_long_reg_writes_reg_reads.1226415000
Directory /workspace/48.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/48.gpio_smoke.1646098791
Short name T308
Test name
Test status
Simulation time 164797861 ps
CPU time 1.15 seconds
Started Jun 30 04:24:26 PM PDT 24
Finished Jun 30 04:24:28 PM PDT 24
Peak memory 195992 kb
Host smart-56c4ad2b-01b9-45c9-ac68-37fe93e3ff70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1646098791 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_smoke.1646098791
Directory /workspace/48.gpio_smoke/latest

Test location /workspace/coverage/default/48.gpio_smoke_no_pullup_pulldown.3654481166
Short name T24
Test name
Test status
Simulation time 62181175 ps
CPU time 1.18 seconds
Started Jun 30 04:24:22 PM PDT 24
Finished Jun 30 04:24:24 PM PDT 24
Peak memory 197332 kb
Host smart-3ae6692a-623d-484e-8fcd-e9ba001768a0
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3654481166 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_smoke_no_pullup_pulldown.3654481166
Directory /workspace/48.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/48.gpio_stress_all.3889377140
Short name T672
Test name
Test status
Simulation time 9468282247 ps
CPU time 129.74 seconds
Started Jun 30 04:24:15 PM PDT 24
Finished Jun 30 04:26:26 PM PDT 24
Peak memory 198624 kb
Host smart-ef1057c7-7177-42bb-b693-ec3577bc7b3b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3889377140 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.
gpio_stress_all.3889377140
Directory /workspace/48.gpio_stress_all/latest

Test location /workspace/coverage/default/48.gpio_stress_all_with_rand_reset.489131638
Short name T33
Test name
Test status
Simulation time 95919328727 ps
CPU time 2061.38 seconds
Started Jun 30 04:24:43 PM PDT 24
Finished Jun 30 04:59:05 PM PDT 24
Peak memory 198684 kb
Host smart-63214b37-1075-47ce-895f-5310a1f07c9d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=489131638 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_stress_all_with_rand_reset.489131638
Directory /workspace/48.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.gpio_alert_test.3532218250
Short name T625
Test name
Test status
Simulation time 11001841 ps
CPU time 0.58 seconds
Started Jun 30 04:24:44 PM PDT 24
Finished Jun 30 04:24:45 PM PDT 24
Peak memory 193692 kb
Host smart-2272cca2-7f65-41b3-9c1a-e71486e82792
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3532218250 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_alert_test.3532218250
Directory /workspace/49.gpio_alert_test/latest

Test location /workspace/coverage/default/49.gpio_dout_din_regs_random_rw.768082265
Short name T157
Test name
Test status
Simulation time 21615248 ps
CPU time 0.72 seconds
Started Jun 30 04:24:12 PM PDT 24
Finished Jun 30 04:24:15 PM PDT 24
Peak memory 195760 kb
Host smart-94d80b66-7990-4327-9f4a-d45c0d062d3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=768082265 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_dout_din_regs_random_rw.768082265
Directory /workspace/49.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/49.gpio_filter_stress.1696783693
Short name T197
Test name
Test status
Simulation time 825087655 ps
CPU time 19.75 seconds
Started Jun 30 04:24:25 PM PDT 24
Finished Jun 30 04:24:45 PM PDT 24
Peak memory 197440 kb
Host smart-2b6a9ef3-d0bf-442d-b56b-0cdc94077360
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1696783693 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_filter_stre
ss.1696783693
Directory /workspace/49.gpio_filter_stress/latest

Test location /workspace/coverage/default/49.gpio_full_random.2175208064
Short name T395
Test name
Test status
Simulation time 45398152 ps
CPU time 0.63 seconds
Started Jun 30 04:24:11 PM PDT 24
Finished Jun 30 04:24:15 PM PDT 24
Peak memory 194808 kb
Host smart-3d5ab5f4-5e7c-4daf-9f09-1f651225a2af
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2175208064 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_full_random.2175208064
Directory /workspace/49.gpio_full_random/latest

Test location /workspace/coverage/default/49.gpio_intr_rand_pgm.1834913199
Short name T350
Test name
Test status
Simulation time 189343689 ps
CPU time 1.01 seconds
Started Jun 30 04:24:20 PM PDT 24
Finished Jun 30 04:24:22 PM PDT 24
Peak memory 196492 kb
Host smart-e3289c6b-4ec2-4fee-9ced-9ef91e2fd689
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1834913199 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_intr_rand_pgm.1834913199
Directory /workspace/49.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/49.gpio_intr_with_filter_rand_intr_event.2463061781
Short name T279
Test name
Test status
Simulation time 42648977 ps
CPU time 1.04 seconds
Started Jun 30 04:24:29 PM PDT 24
Finished Jun 30 04:24:31 PM PDT 24
Peak memory 196488 kb
Host smart-295e39f3-1425-4c75-a2ac-e199b431682d
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2463061781 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 49.gpio_intr_with_filter_rand_intr_event.2463061781
Directory /workspace/49.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/49.gpio_rand_intr_trigger.3557693816
Short name T161
Test name
Test status
Simulation time 146885277 ps
CPU time 2.27 seconds
Started Jun 30 04:24:14 PM PDT 24
Finished Jun 30 04:24:18 PM PDT 24
Peak memory 198544 kb
Host smart-89b8b96d-7f60-4900-9f7b-aa6a5795421f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3557693816 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_rand_intr_trigger
.3557693816
Directory /workspace/49.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/49.gpio_random_dout_din.2937557430
Short name T661
Test name
Test status
Simulation time 60735651 ps
CPU time 0.76 seconds
Started Jun 30 04:24:23 PM PDT 24
Finished Jun 30 04:24:24 PM PDT 24
Peak memory 197588 kb
Host smart-9e20b821-56d8-494b-9ec4-336b0b81875a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2937557430 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_random_dout_din.2937557430
Directory /workspace/49.gpio_random_dout_din/latest

Test location /workspace/coverage/default/49.gpio_random_dout_din_no_pullup_pulldown.480141821
Short name T274
Test name
Test status
Simulation time 32802407 ps
CPU time 1.14 seconds
Started Jun 30 04:24:48 PM PDT 24
Finished Jun 30 04:24:50 PM PDT 24
Peak memory 196316 kb
Host smart-d0dca79c-0c6e-443c-8ac5-bdbff279d4f6
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=480141821 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_random_dout_din_no_pullup
_pulldown.480141821
Directory /workspace/49.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/49.gpio_random_long_reg_writes_reg_reads.1996437850
Short name T10
Test name
Test status
Simulation time 361604036 ps
CPU time 2.54 seconds
Started Jun 30 04:24:14 PM PDT 24
Finished Jun 30 04:24:18 PM PDT 24
Peak memory 198416 kb
Host smart-a6147662-1b78-4f58-8b02-01ff71aab941
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1996437850 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_ra
ndom_long_reg_writes_reg_reads.1996437850
Directory /workspace/49.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/49.gpio_smoke.3852868037
Short name T68
Test name
Test status
Simulation time 40031032 ps
CPU time 1.02 seconds
Started Jun 30 04:24:26 PM PDT 24
Finished Jun 30 04:24:27 PM PDT 24
Peak memory 196220 kb
Host smart-a3d4813d-898a-4f05-aed4-8d997a757246
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3852868037 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_smoke.3852868037
Directory /workspace/49.gpio_smoke/latest

Test location /workspace/coverage/default/49.gpio_smoke_no_pullup_pulldown.1584318272
Short name T198
Test name
Test status
Simulation time 166501448 ps
CPU time 1.13 seconds
Started Jun 30 04:24:31 PM PDT 24
Finished Jun 30 04:24:32 PM PDT 24
Peak memory 196928 kb
Host smart-f81fa414-9bef-4959-99ef-47516d86370e
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1584318272 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_smoke_no_pullup_pulldown.1584318272
Directory /workspace/49.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/49.gpio_stress_all.4122666594
Short name T468
Test name
Test status
Simulation time 14370404130 ps
CPU time 188.84 seconds
Started Jun 30 04:24:27 PM PDT 24
Finished Jun 30 04:27:36 PM PDT 24
Peak memory 198520 kb
Host smart-c7096d2d-3470-4910-857b-bc4d54519058
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4122666594 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.
gpio_stress_all.4122666594
Directory /workspace/49.gpio_stress_all/latest

Test location /workspace/coverage/default/5.gpio_alert_test.3173858270
Short name T353
Test name
Test status
Simulation time 15539504 ps
CPU time 0.57 seconds
Started Jun 30 04:22:55 PM PDT 24
Finished Jun 30 04:22:58 PM PDT 24
Peak memory 194544 kb
Host smart-8f174a14-8414-44b8-bcd4-ee9c397ba723
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3173858270 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_alert_test.3173858270
Directory /workspace/5.gpio_alert_test/latest

Test location /workspace/coverage/default/5.gpio_dout_din_regs_random_rw.836148451
Short name T261
Test name
Test status
Simulation time 152758957 ps
CPU time 0.89 seconds
Started Jun 30 04:22:51 PM PDT 24
Finished Jun 30 04:22:54 PM PDT 24
Peak memory 196920 kb
Host smart-90466fc9-d266-47ee-996c-3fdc390db394
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=836148451 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_dout_din_regs_random_rw.836148451
Directory /workspace/5.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/5.gpio_filter_stress.4014271563
Short name T531
Test name
Test status
Simulation time 814875390 ps
CPU time 20.01 seconds
Started Jun 30 04:22:55 PM PDT 24
Finished Jun 30 04:23:18 PM PDT 24
Peak memory 196748 kb
Host smart-af52ce78-cd32-414f-ac9d-a4c236c27c08
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4014271563 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_filter_stres
s.4014271563
Directory /workspace/5.gpio_filter_stress/latest

Test location /workspace/coverage/default/5.gpio_full_random.1055329100
Short name T482
Test name
Test status
Simulation time 139485593 ps
CPU time 0.74 seconds
Started Jun 30 04:22:51 PM PDT 24
Finished Jun 30 04:22:53 PM PDT 24
Peak memory 196948 kb
Host smart-7489f0f5-1505-4917-b868-56e274b82655
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1055329100 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_full_random.1055329100
Directory /workspace/5.gpio_full_random/latest

Test location /workspace/coverage/default/5.gpio_intr_rand_pgm.3360143633
Short name T133
Test name
Test status
Simulation time 99299039 ps
CPU time 1.25 seconds
Started Jun 30 04:23:12 PM PDT 24
Finished Jun 30 04:23:14 PM PDT 24
Peak memory 197516 kb
Host smart-7eba61d9-7beb-4e24-950a-6102bbf828ac
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3360143633 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_intr_rand_pgm.3360143633
Directory /workspace/5.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/5.gpio_intr_with_filter_rand_intr_event.3800514364
Short name T290
Test name
Test status
Simulation time 63501142 ps
CPU time 2.38 seconds
Started Jun 30 04:22:53 PM PDT 24
Finished Jun 30 04:22:59 PM PDT 24
Peak memory 196924 kb
Host smart-30316f56-e163-4b23-b180-ff0d8c27245d
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3800514364 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 5.gpio_intr_with_filter_rand_intr_event.3800514364
Directory /workspace/5.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/5.gpio_rand_intr_trigger.2422449308
Short name T348
Test name
Test status
Simulation time 131129440 ps
CPU time 2.56 seconds
Started Jun 30 04:23:11 PM PDT 24
Finished Jun 30 04:23:14 PM PDT 24
Peak memory 197012 kb
Host smart-c54f684e-4bdf-4598-a169-0c1a2b50d519
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2422449308 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_rand_intr_trigger.
2422449308
Directory /workspace/5.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/5.gpio_random_dout_din.208790532
Short name T132
Test name
Test status
Simulation time 68791260 ps
CPU time 1.17 seconds
Started Jun 30 04:23:08 PM PDT 24
Finished Jun 30 04:23:10 PM PDT 24
Peak memory 197432 kb
Host smart-c518eb65-888d-4791-961b-be79533358a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=208790532 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_random_dout_din.208790532
Directory /workspace/5.gpio_random_dout_din/latest

Test location /workspace/coverage/default/5.gpio_random_dout_din_no_pullup_pulldown.2788768959
Short name T392
Test name
Test status
Simulation time 304839080 ps
CPU time 0.64 seconds
Started Jun 30 04:22:52 PM PDT 24
Finished Jun 30 04:22:55 PM PDT 24
Peak memory 194740 kb
Host smart-7440570a-ad1d-47b4-baf3-782ba7f7a42f
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2788768959 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_random_dout_din_no_pullup
_pulldown.2788768959
Directory /workspace/5.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/5.gpio_random_long_reg_writes_reg_reads.211628817
Short name T692
Test name
Test status
Simulation time 29787375 ps
CPU time 1.3 seconds
Started Jun 30 04:23:14 PM PDT 24
Finished Jun 30 04:23:17 PM PDT 24
Peak memory 198432 kb
Host smart-d871d5e0-aafb-414f-a3c4-ab1879886792
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=211628817 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_rand
om_long_reg_writes_reg_reads.211628817
Directory /workspace/5.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/5.gpio_smoke.3445635619
Short name T455
Test name
Test status
Simulation time 32201474 ps
CPU time 0.78 seconds
Started Jun 30 04:22:53 PM PDT 24
Finished Jun 30 04:22:57 PM PDT 24
Peak memory 195812 kb
Host smart-634592b8-e683-4df0-b675-dd246a836750
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3445635619 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_smoke.3445635619
Directory /workspace/5.gpio_smoke/latest

Test location /workspace/coverage/default/5.gpio_smoke_no_pullup_pulldown.2309517835
Short name T613
Test name
Test status
Simulation time 29502047 ps
CPU time 0.84 seconds
Started Jun 30 04:22:52 PM PDT 24
Finished Jun 30 04:22:55 PM PDT 24
Peak memory 196580 kb
Host smart-39c2f046-e9f8-4724-bbf3-c09c67e8bc5b
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2309517835 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_smoke_no_pullup_pulldown.2309517835
Directory /workspace/5.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/5.gpio_stress_all.103247387
Short name T476
Test name
Test status
Simulation time 16754612295 ps
CPU time 173.04 seconds
Started Jun 30 04:23:08 PM PDT 24
Finished Jun 30 04:26:01 PM PDT 24
Peak memory 198624 kb
Host smart-702e27b3-6723-42bd-b200-de69a2ac65ec
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=103247387 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gp
io_stress_all.103247387
Directory /workspace/5.gpio_stress_all/latest

Test location /workspace/coverage/default/5.gpio_stress_all_with_rand_reset.1703406001
Short name T670
Test name
Test status
Simulation time 91189507937 ps
CPU time 750.16 seconds
Started Jun 30 04:23:15 PM PDT 24
Finished Jun 30 04:35:46 PM PDT 24
Peak memory 199136 kb
Host smart-03097c74-4693-4788-bd6c-27fc8b3e7915
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1703406001 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_stress_all_with_rand_reset.1703406001
Directory /workspace/5.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.gpio_alert_test.1216838299
Short name T162
Test name
Test status
Simulation time 21493204 ps
CPU time 0.56 seconds
Started Jun 30 04:22:51 PM PDT 24
Finished Jun 30 04:22:53 PM PDT 24
Peak memory 194420 kb
Host smart-fcb291b2-9d8f-4628-8f95-f3d9b8dff5c3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1216838299 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_alert_test.1216838299
Directory /workspace/6.gpio_alert_test/latest

Test location /workspace/coverage/default/6.gpio_dout_din_regs_random_rw.4107717255
Short name T340
Test name
Test status
Simulation time 477084388 ps
CPU time 0.87 seconds
Started Jun 30 04:23:14 PM PDT 24
Finished Jun 30 04:23:17 PM PDT 24
Peak memory 196392 kb
Host smart-62855077-0825-49fe-9dda-d3ed8817c45f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4107717255 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_dout_din_regs_random_rw.4107717255
Directory /workspace/6.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/6.gpio_filter_stress.1898119990
Short name T523
Test name
Test status
Simulation time 1235507492 ps
CPU time 7.23 seconds
Started Jun 30 04:23:14 PM PDT 24
Finished Jun 30 04:23:22 PM PDT 24
Peak memory 198420 kb
Host smart-37bab9b5-6abd-47d1-92b2-ebcd473938c1
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1898119990 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_filter_stres
s.1898119990
Directory /workspace/6.gpio_filter_stress/latest

Test location /workspace/coverage/default/6.gpio_full_random.2374168414
Short name T438
Test name
Test status
Simulation time 78050379 ps
CPU time 0.97 seconds
Started Jun 30 04:23:11 PM PDT 24
Finished Jun 30 04:23:12 PM PDT 24
Peak memory 196764 kb
Host smart-93f9f8e4-67ed-476e-99f2-3618d8092dbc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2374168414 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_full_random.2374168414
Directory /workspace/6.gpio_full_random/latest

Test location /workspace/coverage/default/6.gpio_intr_rand_pgm.2623640114
Short name T245
Test name
Test status
Simulation time 164633627 ps
CPU time 1.33 seconds
Started Jun 30 04:23:02 PM PDT 24
Finished Jun 30 04:23:04 PM PDT 24
Peak memory 197648 kb
Host smart-c862aea3-6897-4696-8cb3-5aa37316f445
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2623640114 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_intr_rand_pgm.2623640114
Directory /workspace/6.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/6.gpio_intr_with_filter_rand_intr_event.350037003
Short name T303
Test name
Test status
Simulation time 70330556 ps
CPU time 2.61 seconds
Started Jun 30 04:23:15 PM PDT 24
Finished Jun 30 04:23:19 PM PDT 24
Peak memory 198444 kb
Host smart-48543ea0-f2fd-4105-a41a-a9f6045a2bdd
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=350037003 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 6.gpio_intr_with_filter_rand_intr_event.350037003
Directory /workspace/6.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/6.gpio_rand_intr_trigger.1394874037
Short name T256
Test name
Test status
Simulation time 278293071 ps
CPU time 2.17 seconds
Started Jun 30 04:22:51 PM PDT 24
Finished Jun 30 04:22:54 PM PDT 24
Peak memory 197412 kb
Host smart-c0b207c7-ea66-429a-bc84-47291f97d0b9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1394874037 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_rand_intr_trigger.
1394874037
Directory /workspace/6.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/6.gpio_random_dout_din.1895347637
Short name T14
Test name
Test status
Simulation time 115264618 ps
CPU time 1.16 seconds
Started Jun 30 04:22:56 PM PDT 24
Finished Jun 30 04:22:59 PM PDT 24
Peak memory 197408 kb
Host smart-63f37238-3f57-4c18-a885-7d5d3493be9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1895347637 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_random_dout_din.1895347637
Directory /workspace/6.gpio_random_dout_din/latest

Test location /workspace/coverage/default/6.gpio_random_dout_din_no_pullup_pulldown.1868190374
Short name T422
Test name
Test status
Simulation time 36832810 ps
CPU time 0.82 seconds
Started Jun 30 04:23:12 PM PDT 24
Finished Jun 30 04:23:14 PM PDT 24
Peak memory 197748 kb
Host smart-d5a9ca45-416f-47ca-921e-4fd4f2926976
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1868190374 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_random_dout_din_no_pullup
_pulldown.1868190374
Directory /workspace/6.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/6.gpio_random_long_reg_writes_reg_reads.2373504549
Short name T341
Test name
Test status
Simulation time 100800744 ps
CPU time 2.34 seconds
Started Jun 30 04:22:57 PM PDT 24
Finished Jun 30 04:23:02 PM PDT 24
Peak memory 198196 kb
Host smart-02fe8928-1ded-4dab-957a-67ca59d4e1ca
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2373504549 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_ran
dom_long_reg_writes_reg_reads.2373504549
Directory /workspace/6.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/6.gpio_smoke.2725540950
Short name T507
Test name
Test status
Simulation time 240071452 ps
CPU time 1.13 seconds
Started Jun 30 04:23:04 PM PDT 24
Finished Jun 30 04:23:06 PM PDT 24
Peak memory 197284 kb
Host smart-e823c16b-9708-46bd-9aa4-71664ea306df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2725540950 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_smoke.2725540950
Directory /workspace/6.gpio_smoke/latest

Test location /workspace/coverage/default/6.gpio_smoke_no_pullup_pulldown.1348344044
Short name T664
Test name
Test status
Simulation time 120470551 ps
CPU time 0.77 seconds
Started Jun 30 04:23:00 PM PDT 24
Finished Jun 30 04:23:02 PM PDT 24
Peak memory 196512 kb
Host smart-2548f11e-07bb-467c-91d6-4a966e474408
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1348344044 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_smoke_no_pullup_pulldown.1348344044
Directory /workspace/6.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/6.gpio_stress_all.920491786
Short name T601
Test name
Test status
Simulation time 27438640393 ps
CPU time 63.71 seconds
Started Jun 30 04:23:19 PM PDT 24
Finished Jun 30 04:24:24 PM PDT 24
Peak memory 198532 kb
Host smart-6adb616c-a987-49e3-b604-2273b6b5e5e3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=920491786 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gp
io_stress_all.920491786
Directory /workspace/6.gpio_stress_all/latest

Test location /workspace/coverage/default/6.gpio_stress_all_with_rand_reset.3737089436
Short name T9
Test name
Test status
Simulation time 173117381468 ps
CPU time 612.55 seconds
Started Jun 30 04:23:07 PM PDT 24
Finished Jun 30 04:33:20 PM PDT 24
Peak memory 198704 kb
Host smart-6a136f96-6d83-4c32-9c9c-0bbfffc0336b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3737089436 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_stress_all_with_rand_reset.3737089436
Directory /workspace/6.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.gpio_alert_test.3488796187
Short name T600
Test name
Test status
Simulation time 19450674 ps
CPU time 0.54 seconds
Started Jun 30 04:23:12 PM PDT 24
Finished Jun 30 04:23:13 PM PDT 24
Peak memory 194436 kb
Host smart-7f75eb30-db8b-4778-84c7-4c899c5a42db
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3488796187 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_alert_test.3488796187
Directory /workspace/7.gpio_alert_test/latest

Test location /workspace/coverage/default/7.gpio_dout_din_regs_random_rw.3917676252
Short name T545
Test name
Test status
Simulation time 20958066 ps
CPU time 0.8 seconds
Started Jun 30 04:23:14 PM PDT 24
Finished Jun 30 04:23:16 PM PDT 24
Peak memory 195644 kb
Host smart-eacf3cf3-2ac9-4462-b38d-91b9d40ebf14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3917676252 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_dout_din_regs_random_rw.3917676252
Directory /workspace/7.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/7.gpio_filter_stress.3431220975
Short name T715
Test name
Test status
Simulation time 545279589 ps
CPU time 16.2 seconds
Started Jun 30 04:23:11 PM PDT 24
Finished Jun 30 04:23:27 PM PDT 24
Peak memory 198376 kb
Host smart-5da59a6f-fcc5-4a9e-a9e9-2984a003d4d1
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3431220975 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_filter_stres
s.3431220975
Directory /workspace/7.gpio_filter_stress/latest

Test location /workspace/coverage/default/7.gpio_full_random.2047016289
Short name T369
Test name
Test status
Simulation time 138670650 ps
CPU time 0.85 seconds
Started Jun 30 04:23:18 PM PDT 24
Finished Jun 30 04:23:21 PM PDT 24
Peak memory 196312 kb
Host smart-f8feb060-7606-4ff5-9937-fad518b1a80f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2047016289 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_full_random.2047016289
Directory /workspace/7.gpio_full_random/latest

Test location /workspace/coverage/default/7.gpio_intr_rand_pgm.4131120644
Short name T314
Test name
Test status
Simulation time 390772934 ps
CPU time 1.41 seconds
Started Jun 30 04:23:12 PM PDT 24
Finished Jun 30 04:23:14 PM PDT 24
Peak memory 198440 kb
Host smart-81b016be-ae22-4fb0-bdff-1a8cab313f65
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4131120644 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_intr_rand_pgm.4131120644
Directory /workspace/7.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/7.gpio_intr_with_filter_rand_intr_event.4114825854
Short name T277
Test name
Test status
Simulation time 1103705296 ps
CPU time 3.03 seconds
Started Jun 30 04:23:16 PM PDT 24
Finished Jun 30 04:23:20 PM PDT 24
Peak memory 198756 kb
Host smart-60524e71-9c1d-4892-96de-318215009d42
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4114825854 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 7.gpio_intr_with_filter_rand_intr_event.4114825854
Directory /workspace/7.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/7.gpio_rand_intr_trigger.843063098
Short name T146
Test name
Test status
Simulation time 64745284 ps
CPU time 1.76 seconds
Started Jun 30 04:23:17 PM PDT 24
Finished Jun 30 04:23:21 PM PDT 24
Peak memory 198516 kb
Host smart-abd9cf3a-6927-4456-a4cf-b3bed6949b3b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=843063098 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_rand_intr_trigger.843063098
Directory /workspace/7.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/7.gpio_random_dout_din.2217876581
Short name T171
Test name
Test status
Simulation time 124707593 ps
CPU time 1.16 seconds
Started Jun 30 04:23:18 PM PDT 24
Finished Jun 30 04:23:21 PM PDT 24
Peak memory 198564 kb
Host smart-08e3b106-4a48-4d68-92d1-b7dc5eead974
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2217876581 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_random_dout_din.2217876581
Directory /workspace/7.gpio_random_dout_din/latest

Test location /workspace/coverage/default/7.gpio_random_dout_din_no_pullup_pulldown.968048583
Short name T430
Test name
Test status
Simulation time 129225357 ps
CPU time 1 seconds
Started Jun 30 04:23:13 PM PDT 24
Finished Jun 30 04:23:15 PM PDT 24
Peak memory 196892 kb
Host smart-9ac241c7-1419-40bd-bf97-4948bc75d231
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=968048583 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_random_dout_din_no_pullup_
pulldown.968048583
Directory /workspace/7.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/7.gpio_random_long_reg_writes_reg_reads.405390322
Short name T285
Test name
Test status
Simulation time 98719099 ps
CPU time 2.23 seconds
Started Jun 30 04:23:16 PM PDT 24
Finished Jun 30 04:23:20 PM PDT 24
Peak memory 198452 kb
Host smart-64d6574a-1803-49e5-81bb-ea05e219aa1c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=405390322 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_rand
om_long_reg_writes_reg_reads.405390322
Directory /workspace/7.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/7.gpio_smoke.3350888304
Short name T555
Test name
Test status
Simulation time 216240357 ps
CPU time 1.13 seconds
Started Jun 30 04:22:57 PM PDT 24
Finished Jun 30 04:23:00 PM PDT 24
Peak memory 196492 kb
Host smart-c76e4730-904d-45a8-a686-0a25c40f6103
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3350888304 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_smoke.3350888304
Directory /workspace/7.gpio_smoke/latest

Test location /workspace/coverage/default/7.gpio_smoke_no_pullup_pulldown.2442852984
Short name T442
Test name
Test status
Simulation time 42561042 ps
CPU time 1.1 seconds
Started Jun 30 04:22:57 PM PDT 24
Finished Jun 30 04:23:00 PM PDT 24
Peak memory 196124 kb
Host smart-853c175f-197b-488a-8522-82a9390ea546
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2442852984 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_smoke_no_pullup_pulldown.2442852984
Directory /workspace/7.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/7.gpio_stress_all.1487535222
Short name T582
Test name
Test status
Simulation time 31706235497 ps
CPU time 119.57 seconds
Started Jun 30 04:23:18 PM PDT 24
Finished Jun 30 04:25:19 PM PDT 24
Peak memory 198544 kb
Host smart-a61fadf5-f386-4b8a-8710-b1e2744e3e3a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1487535222 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.g
pio_stress_all.1487535222
Directory /workspace/7.gpio_stress_all/latest

Test location /workspace/coverage/default/7.gpio_stress_all_with_rand_reset.3496098244
Short name T627
Test name
Test status
Simulation time 180724121680 ps
CPU time 1906.14 seconds
Started Jun 30 04:23:13 PM PDT 24
Finished Jun 30 04:55:01 PM PDT 24
Peak memory 198748 kb
Host smart-530dc29c-b123-493c-b8e6-e7dd1c0dcbb1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3496098244 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_stress_all_with_rand_reset.3496098244
Directory /workspace/7.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.gpio_alert_test.2921658971
Short name T617
Test name
Test status
Simulation time 83177391 ps
CPU time 0.6 seconds
Started Jun 30 04:23:20 PM PDT 24
Finished Jun 30 04:23:21 PM PDT 24
Peak memory 194624 kb
Host smart-7df4dc41-16ec-49ca-a0fd-da0ad487c054
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2921658971 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_alert_test.2921658971
Directory /workspace/8.gpio_alert_test/latest

Test location /workspace/coverage/default/8.gpio_dout_din_regs_random_rw.1024582557
Short name T616
Test name
Test status
Simulation time 40903283 ps
CPU time 0.89 seconds
Started Jun 30 04:23:15 PM PDT 24
Finished Jun 30 04:23:17 PM PDT 24
Peak memory 197688 kb
Host smart-59af2ec3-a098-4f34-8bf8-874725d5fc33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1024582557 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_dout_din_regs_random_rw.1024582557
Directory /workspace/8.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/8.gpio_filter_stress.4257976917
Short name T17
Test name
Test status
Simulation time 129901382 ps
CPU time 3.68 seconds
Started Jun 30 04:23:25 PM PDT 24
Finished Jun 30 04:23:29 PM PDT 24
Peak memory 197132 kb
Host smart-d736a464-5a90-4b6b-9cc2-d0694ca7746c
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4257976917 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_filter_stres
s.4257976917
Directory /workspace/8.gpio_filter_stress/latest

Test location /workspace/coverage/default/8.gpio_full_random.3945291892
Short name T32
Test name
Test status
Simulation time 187350796 ps
CPU time 0.81 seconds
Started Jun 30 04:23:16 PM PDT 24
Finished Jun 30 04:23:19 PM PDT 24
Peak memory 196308 kb
Host smart-049aa62e-39e6-4531-83d9-8fca2fe7dc56
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3945291892 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_full_random.3945291892
Directory /workspace/8.gpio_full_random/latest

Test location /workspace/coverage/default/8.gpio_intr_rand_pgm.494140547
Short name T239
Test name
Test status
Simulation time 36414635 ps
CPU time 1.01 seconds
Started Jun 30 04:23:14 PM PDT 24
Finished Jun 30 04:23:17 PM PDT 24
Peak memory 196224 kb
Host smart-be7dc53e-d7b3-48ea-beb1-ccc7d32d21f5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=494140547 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_intr_rand_pgm.494140547
Directory /workspace/8.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/8.gpio_intr_with_filter_rand_intr_event.134920665
Short name T184
Test name
Test status
Simulation time 65853394 ps
CPU time 2.58 seconds
Started Jun 30 04:23:14 PM PDT 24
Finished Jun 30 04:23:18 PM PDT 24
Peak memory 197372 kb
Host smart-066bec27-b584-4b2c-b20c-0208c276b772
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=134920665 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 8.gpio_intr_with_filter_rand_intr_event.134920665
Directory /workspace/8.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/8.gpio_rand_intr_trigger.540517503
Short name T342
Test name
Test status
Simulation time 56720961 ps
CPU time 1.19 seconds
Started Jun 30 04:23:18 PM PDT 24
Finished Jun 30 04:23:25 PM PDT 24
Peak memory 195996 kb
Host smart-9ff3db62-5ffa-474b-8479-f85d48ec0772
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=540517503 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_rand_intr_trigger.540517503
Directory /workspace/8.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/8.gpio_random_dout_din.3512932275
Short name T93
Test name
Test status
Simulation time 45075990 ps
CPU time 0.74 seconds
Started Jun 30 04:23:17 PM PDT 24
Finished Jun 30 04:23:19 PM PDT 24
Peak memory 195960 kb
Host smart-ca0a1aa2-56b9-46bc-b0c3-58f026151d0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3512932275 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_random_dout_din.3512932275
Directory /workspace/8.gpio_random_dout_din/latest

Test location /workspace/coverage/default/8.gpio_random_dout_din_no_pullup_pulldown.1272002902
Short name T111
Test name
Test status
Simulation time 79347136 ps
CPU time 0.95 seconds
Started Jun 30 04:23:17 PM PDT 24
Finished Jun 30 04:23:20 PM PDT 24
Peak memory 196460 kb
Host smart-c577db9a-ea41-4b78-b2ed-4e4c5bf0f220
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1272002902 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_random_dout_din_no_pullup
_pulldown.1272002902
Directory /workspace/8.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/8.gpio_random_long_reg_writes_reg_reads.1132710486
Short name T267
Test name
Test status
Simulation time 74827126 ps
CPU time 3.23 seconds
Started Jun 30 04:23:13 PM PDT 24
Finished Jun 30 04:23:17 PM PDT 24
Peak memory 198428 kb
Host smart-b85148c8-804f-4761-90d8-f2fdd5fb841d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1132710486 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_ran
dom_long_reg_writes_reg_reads.1132710486
Directory /workspace/8.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/8.gpio_smoke.2279653910
Short name T393
Test name
Test status
Simulation time 46550105 ps
CPU time 0.99 seconds
Started Jun 30 04:23:19 PM PDT 24
Finished Jun 30 04:23:21 PM PDT 24
Peak memory 196280 kb
Host smart-719ffdc6-a20f-4452-90c0-181b921068cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2279653910 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_smoke.2279653910
Directory /workspace/8.gpio_smoke/latest

Test location /workspace/coverage/default/8.gpio_smoke_no_pullup_pulldown.2497743608
Short name T360
Test name
Test status
Simulation time 456960089 ps
CPU time 0.92 seconds
Started Jun 30 04:23:16 PM PDT 24
Finished Jun 30 04:23:18 PM PDT 24
Peak memory 195792 kb
Host smart-10df2bb2-9f69-491c-9108-379563942c05
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2497743608 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_smoke_no_pullup_pulldown.2497743608
Directory /workspace/8.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/8.gpio_stress_all.1373088283
Short name T124
Test name
Test status
Simulation time 3665310139 ps
CPU time 77.51 seconds
Started Jun 30 04:23:25 PM PDT 24
Finished Jun 30 04:24:43 PM PDT 24
Peak memory 198560 kb
Host smart-99db7b69-a306-43c6-af5b-ec3950d1c3d3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1373088283 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.g
pio_stress_all.1373088283
Directory /workspace/8.gpio_stress_all/latest

Test location /workspace/coverage/default/8.gpio_stress_all_with_rand_reset.3653559991
Short name T518
Test name
Test status
Simulation time 239886314807 ps
CPU time 793.45 seconds
Started Jun 30 04:23:08 PM PDT 24
Finished Jun 30 04:36:22 PM PDT 24
Peak memory 198660 kb
Host smart-c739dca9-b322-4070-81e8-e52531fd44cd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3653559991 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_stress_all_with_rand_reset.3653559991
Directory /workspace/8.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.gpio_alert_test.3053650263
Short name T271
Test name
Test status
Simulation time 104349032 ps
CPU time 0.55 seconds
Started Jun 30 04:23:17 PM PDT 24
Finished Jun 30 04:23:19 PM PDT 24
Peak memory 195112 kb
Host smart-ca194865-1ea5-473b-ad39-db2cac28f97e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3053650263 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_alert_test.3053650263
Directory /workspace/9.gpio_alert_test/latest

Test location /workspace/coverage/default/9.gpio_dout_din_regs_random_rw.4159554921
Short name T158
Test name
Test status
Simulation time 81733634 ps
CPU time 0.6 seconds
Started Jun 30 04:23:19 PM PDT 24
Finished Jun 30 04:23:20 PM PDT 24
Peak memory 194012 kb
Host smart-80d6cfd6-32b5-43f2-8a7c-5f157164f897
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4159554921 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_dout_din_regs_random_rw.4159554921
Directory /workspace/9.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/9.gpio_filter_stress.3418862687
Short name T477
Test name
Test status
Simulation time 3029078945 ps
CPU time 21.98 seconds
Started Jun 30 04:23:13 PM PDT 24
Finished Jun 30 04:23:35 PM PDT 24
Peak memory 198520 kb
Host smart-7eef54d1-66ea-42d8-bc81-41977f148c08
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3418862687 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_filter_stres
s.3418862687
Directory /workspace/9.gpio_filter_stress/latest

Test location /workspace/coverage/default/9.gpio_full_random.1162287751
Short name T257
Test name
Test status
Simulation time 103105813 ps
CPU time 0.84 seconds
Started Jun 30 04:23:03 PM PDT 24
Finished Jun 30 04:23:05 PM PDT 24
Peak memory 196264 kb
Host smart-ff5b1e4a-537b-45a7-9c24-7451908b2f53
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1162287751 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_full_random.1162287751
Directory /workspace/9.gpio_full_random/latest

Test location /workspace/coverage/default/9.gpio_intr_rand_pgm.1762175116
Short name T195
Test name
Test status
Simulation time 68465971 ps
CPU time 1.02 seconds
Started Jun 30 04:23:12 PM PDT 24
Finished Jun 30 04:23:14 PM PDT 24
Peak memory 196420 kb
Host smart-983b50bf-8ec0-40b5-a20d-91f0571c1718
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1762175116 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_intr_rand_pgm.1762175116
Directory /workspace/9.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/9.gpio_intr_with_filter_rand_intr_event.4248878232
Short name T645
Test name
Test status
Simulation time 85143910 ps
CPU time 1.04 seconds
Started Jun 30 04:23:14 PM PDT 24
Finished Jun 30 04:23:16 PM PDT 24
Peak memory 197448 kb
Host smart-40c6bd17-d606-4151-913c-e7cb3676c2be
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4248878232 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 9.gpio_intr_with_filter_rand_intr_event.4248878232
Directory /workspace/9.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/9.gpio_rand_intr_trigger.2647942862
Short name T682
Test name
Test status
Simulation time 156170800 ps
CPU time 3.07 seconds
Started Jun 30 04:23:15 PM PDT 24
Finished Jun 30 04:23:19 PM PDT 24
Peak memory 198604 kb
Host smart-bc410a79-855a-435d-a62e-9a0774c3cc53
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2647942862 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_rand_intr_trigger.
2647942862
Directory /workspace/9.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/9.gpio_random_dout_din.2563396097
Short name T110
Test name
Test status
Simulation time 187183690 ps
CPU time 1.12 seconds
Started Jun 30 04:23:14 PM PDT 24
Finished Jun 30 04:23:16 PM PDT 24
Peak memory 197808 kb
Host smart-1a459911-3df4-4534-aa47-0b9d53cf131e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2563396097 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_random_dout_din.2563396097
Directory /workspace/9.gpio_random_dout_din/latest

Test location /workspace/coverage/default/9.gpio_random_dout_din_no_pullup_pulldown.1280015723
Short name T203
Test name
Test status
Simulation time 46312826 ps
CPU time 1 seconds
Started Jun 30 04:23:12 PM PDT 24
Finished Jun 30 04:23:14 PM PDT 24
Peak memory 196532 kb
Host smart-53145764-685b-4810-ae5e-1179ab9cf003
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1280015723 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_random_dout_din_no_pullup
_pulldown.1280015723
Directory /workspace/9.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/9.gpio_random_long_reg_writes_reg_reads.2481897084
Short name T153
Test name
Test status
Simulation time 1228186816 ps
CPU time 5.01 seconds
Started Jun 30 04:23:11 PM PDT 24
Finished Jun 30 04:23:17 PM PDT 24
Peak memory 198452 kb
Host smart-ebc5fbd2-c12e-4da8-9445-af79ed701209
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2481897084 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_ran
dom_long_reg_writes_reg_reads.2481897084
Directory /workspace/9.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/9.gpio_smoke.2682015266
Short name T460
Test name
Test status
Simulation time 169855017 ps
CPU time 0.93 seconds
Started Jun 30 04:23:20 PM PDT 24
Finished Jun 30 04:23:22 PM PDT 24
Peak memory 197676 kb
Host smart-bff4682b-cb08-4459-aa9e-334aef6367a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2682015266 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_smoke.2682015266
Directory /workspace/9.gpio_smoke/latest

Test location /workspace/coverage/default/9.gpio_smoke_no_pullup_pulldown.2168685757
Short name T330
Test name
Test status
Simulation time 91001235 ps
CPU time 0.78 seconds
Started Jun 30 04:23:14 PM PDT 24
Finished Jun 30 04:23:16 PM PDT 24
Peak memory 195612 kb
Host smart-be660c4b-f8aa-4c93-b440-901a5d470a1a
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2168685757 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_smoke_no_pullup_pulldown.2168685757
Directory /workspace/9.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/9.gpio_stress_all.960104811
Short name T136
Test name
Test status
Simulation time 14740952349 ps
CPU time 190.01 seconds
Started Jun 30 04:23:19 PM PDT 24
Finished Jun 30 04:26:30 PM PDT 24
Peak memory 198140 kb
Host smart-7c2444d2-0f3e-42e6-9236-7d7d6583fbfd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=960104811 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gp
io_stress_all.960104811
Directory /workspace/9.gpio_stress_all/latest

Test location /workspace/coverage/default/9.gpio_stress_all_with_rand_reset.3065656516
Short name T57
Test name
Test status
Simulation time 173612184028 ps
CPU time 2246.96 seconds
Started Jun 30 04:23:21 PM PDT 24
Finished Jun 30 05:00:49 PM PDT 24
Peak memory 198704 kb
Host smart-3c8fdb45-a60c-4ff7-97fc-d19ccef52943
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3065656516 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_stress_all_with_rand_reset.3065656516
Directory /workspace/9.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/en_cdc_prims/0.gpio_smoke_en_cdc_prim.855058604
Short name T891
Test name
Test status
Simulation time 102565125 ps
CPU time 1.45 seconds
Started Jun 30 04:17:52 PM PDT 24
Finished Jun 30 04:17:54 PM PDT 24
Peak memory 197036 kb
Host smart-b9f330f6-47ce-440f-a3ba-e3e2d3dd9c9f
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=855058604 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 0.gpio_smoke_en_cdc_prim.855058604
Directory /workspace/0.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/0.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1069643652
Short name T865
Test name
Test status
Simulation time 132889852 ps
CPU time 1.12 seconds
Started Jun 30 04:17:33 PM PDT 24
Finished Jun 30 04:17:35 PM PDT 24
Peak memory 196116 kb
Host smart-a02dd78a-5d8c-4a91-8bc6-d1feb9ec46c0
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1069643652 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 0.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.1069643652
Directory /workspace/0.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/1.gpio_smoke_en_cdc_prim.251511797
Short name T916
Test name
Test status
Simulation time 79825636 ps
CPU time 1.29 seconds
Started Jun 30 04:20:47 PM PDT 24
Finished Jun 30 04:20:48 PM PDT 24
Peak memory 196712 kb
Host smart-9451dc09-0aae-403c-8674-4cd38462c45e
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=251511797 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 1.gpio_smoke_en_cdc_prim.251511797
Directory /workspace/1.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/1.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3879106810
Short name T941
Test name
Test status
Simulation time 74167721 ps
CPU time 1.2 seconds
Started Jun 30 04:17:48 PM PDT 24
Finished Jun 30 04:17:49 PM PDT 24
Peak memory 196292 kb
Host smart-20bd0be6-15dd-47fc-bb4d-b2b271f34cae
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3879106810 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 1.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.3879106810
Directory /workspace/1.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/10.gpio_smoke_en_cdc_prim.3648628906
Short name T860
Test name
Test status
Simulation time 36868004 ps
CPU time 1.35 seconds
Started Jun 30 04:20:18 PM PDT 24
Finished Jun 30 04:20:20 PM PDT 24
Peak memory 196728 kb
Host smart-4be24274-2fd7-4811-a119-77b62d038f63
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3648628906 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 10.gpio_smoke_en_cdc_prim.3648628906
Directory /workspace/10.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/10.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2852233920
Short name T893
Test name
Test status
Simulation time 77415124 ps
CPU time 1.19 seconds
Started Jun 30 04:22:16 PM PDT 24
Finished Jun 30 04:22:18 PM PDT 24
Peak memory 198224 kb
Host smart-bda21c21-798a-402e-98ab-ddf947d53398
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2852233920 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 10.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2852233920
Directory /workspace/10.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/11.gpio_smoke_en_cdc_prim.759283829
Short name T882
Test name
Test status
Simulation time 104361142 ps
CPU time 1.1 seconds
Started Jun 30 04:21:50 PM PDT 24
Finished Jun 30 04:21:52 PM PDT 24
Peak memory 197356 kb
Host smart-3fea89a1-af2a-4a5e-9c61-cbe4283cc96a
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=759283829 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 11.gpio_smoke_en_cdc_prim.759283829
Directory /workspace/11.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/11.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3755991969
Short name T885
Test name
Test status
Simulation time 91542313 ps
CPU time 1.3 seconds
Started Jun 30 04:22:47 PM PDT 24
Finished Jun 30 04:22:51 PM PDT 24
Peak memory 195924 kb
Host smart-37880816-6f81-4c5f-bd86-eefe84079c02
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3755991969 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 11.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3755991969
Directory /workspace/11.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/12.gpio_smoke_en_cdc_prim.3922297999
Short name T912
Test name
Test status
Simulation time 298362927 ps
CPU time 1.2 seconds
Started Jun 30 04:22:47 PM PDT 24
Finished Jun 30 04:22:50 PM PDT 24
Peak memory 196804 kb
Host smart-ab58c45a-59f5-482d-8dbc-385a416e60fe
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3922297999 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 12.gpio_smoke_en_cdc_prim.3922297999
Directory /workspace/12.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/12.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2885320086
Short name T903
Test name
Test status
Simulation time 1065137409 ps
CPU time 1.19 seconds
Started Jun 30 04:19:25 PM PDT 24
Finished Jun 30 04:19:27 PM PDT 24
Peak memory 197004 kb
Host smart-d5c9ebf9-3040-4aa2-b3db-cc4ecf3089e6
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2885320086 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 12.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2885320086
Directory /workspace/12.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/13.gpio_smoke_en_cdc_prim.4263145252
Short name T872
Test name
Test status
Simulation time 38535793 ps
CPU time 0.86 seconds
Started Jun 30 04:22:53 PM PDT 24
Finished Jun 30 04:22:56 PM PDT 24
Peak memory 197480 kb
Host smart-390957d9-0da3-4772-b7e8-46d7c703a406
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=4263145252 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 13.gpio_smoke_en_cdc_prim.4263145252
Directory /workspace/13.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/13.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1022845849
Short name T866
Test name
Test status
Simulation time 199507339 ps
CPU time 0.93 seconds
Started Jun 30 04:22:06 PM PDT 24
Finished Jun 30 04:22:09 PM PDT 24
Peak memory 196228 kb
Host smart-d1d0071b-efe2-4e15-a594-06077d02a4de
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1022845849 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 13.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1022845849
Directory /workspace/13.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/14.gpio_smoke_en_cdc_prim.1034745129
Short name T844
Test name
Test status
Simulation time 30855082 ps
CPU time 1.02 seconds
Started Jun 30 04:22:00 PM PDT 24
Finished Jun 30 04:22:02 PM PDT 24
Peak memory 196076 kb
Host smart-4b0d6af5-b79e-4058-b647-e90b514ce03f
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1034745129 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 14.gpio_smoke_en_cdc_prim.1034745129
Directory /workspace/14.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/14.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3121563735
Short name T917
Test name
Test status
Simulation time 48692650 ps
CPU time 1.04 seconds
Started Jun 30 04:19:20 PM PDT 24
Finished Jun 30 04:19:22 PM PDT 24
Peak memory 197328 kb
Host smart-15bb2aef-4762-4ab6-922d-1875ea7c1375
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3121563735 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 14.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3121563735
Directory /workspace/14.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/15.gpio_smoke_en_cdc_prim.2879458930
Short name T856
Test name
Test status
Simulation time 93409982 ps
CPU time 0.72 seconds
Started Jun 30 04:22:09 PM PDT 24
Finished Jun 30 04:22:12 PM PDT 24
Peak memory 195656 kb
Host smart-c60dca68-556b-4504-8f7e-67ca945c7ccf
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2879458930 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 15.gpio_smoke_en_cdc_prim.2879458930
Directory /workspace/15.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/15.gpio_smoke_no_pullup_pulldown_en_cdc_prim.833227144
Short name T867
Test name
Test status
Simulation time 172668075 ps
CPU time 0.91 seconds
Started Jun 30 04:22:12 PM PDT 24
Finished Jun 30 04:22:14 PM PDT 24
Peak memory 195400 kb
Host smart-ee011ccf-c0a1-481f-a654-3d12a256b98f
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=833227144 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 15.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.833227144
Directory /workspace/15.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/16.gpio_smoke_en_cdc_prim.937779550
Short name T942
Test name
Test status
Simulation time 42561702 ps
CPU time 1.11 seconds
Started Jun 30 04:21:57 PM PDT 24
Finished Jun 30 04:21:59 PM PDT 24
Peak memory 195628 kb
Host smart-09a06362-d4ef-457a-a8cd-db2eaaf13825
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=937779550 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 16.gpio_smoke_en_cdc_prim.937779550
Directory /workspace/16.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/16.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2531144917
Short name T854
Test name
Test status
Simulation time 80633442 ps
CPU time 1.21 seconds
Started Jun 30 04:20:37 PM PDT 24
Finished Jun 30 04:20:39 PM PDT 24
Peak memory 196208 kb
Host smart-b66e960d-9464-48c0-a5ab-b15169f6d4f4
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2531144917 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 16.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2531144917
Directory /workspace/16.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/17.gpio_smoke_en_cdc_prim.1356828487
Short name T845
Test name
Test status
Simulation time 52865010 ps
CPU time 1.36 seconds
Started Jun 30 04:20:17 PM PDT 24
Finished Jun 30 04:20:18 PM PDT 24
Peak memory 197096 kb
Host smart-ae712c99-223d-4897-8d6a-22fe78fe748c
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1356828487 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 17.gpio_smoke_en_cdc_prim.1356828487
Directory /workspace/17.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/17.gpio_smoke_no_pullup_pulldown_en_cdc_prim.53469155
Short name T927
Test name
Test status
Simulation time 28287838 ps
CPU time 0.94 seconds
Started Jun 30 04:22:12 PM PDT 24
Finished Jun 30 04:22:14 PM PDT 24
Peak memory 196056 kb
Host smart-e02072ef-ec5f-4cdf-9472-235f530a4bd7
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53469155 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 17.gpio_smoke_no_pullup_pulldown_e
n_cdc_prim.53469155
Directory /workspace/17.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/18.gpio_smoke_en_cdc_prim.2493231678
Short name T898
Test name
Test status
Simulation time 219255538 ps
CPU time 1.12 seconds
Started Jun 30 04:20:15 PM PDT 24
Finished Jun 30 04:20:17 PM PDT 24
Peak memory 197196 kb
Host smart-32eaecde-29ee-40cb-b8f5-df0bf2339508
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2493231678 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 18.gpio_smoke_en_cdc_prim.2493231678
Directory /workspace/18.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/18.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3006183904
Short name T886
Test name
Test status
Simulation time 134475533 ps
CPU time 0.86 seconds
Started Jun 30 04:18:57 PM PDT 24
Finished Jun 30 04:18:58 PM PDT 24
Peak memory 198204 kb
Host smart-9a6d7e7a-fd6d-47ad-9a9d-6027c9f03e27
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3006183904 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 18.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3006183904
Directory /workspace/18.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/19.gpio_smoke_en_cdc_prim.197937118
Short name T897
Test name
Test status
Simulation time 108477848 ps
CPU time 1.43 seconds
Started Jun 30 04:22:13 PM PDT 24
Finished Jun 30 04:22:15 PM PDT 24
Peak memory 197016 kb
Host smart-87d17e57-9619-49f2-a6fe-a3c99d6f2966
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=197937118 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 19.gpio_smoke_en_cdc_prim.197937118
Directory /workspace/19.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/19.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1178044105
Short name T904
Test name
Test status
Simulation time 71293564 ps
CPU time 1.2 seconds
Started Jun 30 04:22:56 PM PDT 24
Finished Jun 30 04:22:59 PM PDT 24
Peak memory 191620 kb
Host smart-d2018c99-72e0-45de-99be-f030c611121a
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1178044105 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 19.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1178044105
Directory /workspace/19.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/2.gpio_smoke_en_cdc_prim.1259775910
Short name T864
Test name
Test status
Simulation time 154092041 ps
CPU time 1.35 seconds
Started Jun 30 04:17:05 PM PDT 24
Finished Jun 30 04:17:07 PM PDT 24
Peak memory 196056 kb
Host smart-b55543d9-5d27-497d-95ed-8d97e735a66a
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1259775910 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 2.gpio_smoke_en_cdc_prim.1259775910
Directory /workspace/2.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/2.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3809857565
Short name T930
Test name
Test status
Simulation time 30512427 ps
CPU time 0.78 seconds
Started Jun 30 04:20:06 PM PDT 24
Finished Jun 30 04:20:08 PM PDT 24
Peak memory 196520 kb
Host smart-0d70a947-099d-4780-9d2d-21d4be6748f9
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3809857565 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 2.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.3809857565
Directory /workspace/2.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/20.gpio_smoke_en_cdc_prim.868817643
Short name T925
Test name
Test status
Simulation time 73510009 ps
CPU time 1.07 seconds
Started Jun 30 04:22:57 PM PDT 24
Finished Jun 30 04:23:00 PM PDT 24
Peak memory 196612 kb
Host smart-91bb6139-f048-4d1a-866f-4029aacd0cf4
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=868817643 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 20.gpio_smoke_en_cdc_prim.868817643
Directory /workspace/20.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/20.gpio_smoke_no_pullup_pulldown_en_cdc_prim.195523641
Short name T859
Test name
Test status
Simulation time 343614462 ps
CPU time 1.05 seconds
Started Jun 30 04:18:49 PM PDT 24
Finished Jun 30 04:18:51 PM PDT 24
Peak memory 198392 kb
Host smart-d1fd2d21-84cc-4578-97cc-95b4ef59de56
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=195523641 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 20.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.195523641
Directory /workspace/20.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/21.gpio_smoke_en_cdc_prim.1673236069
Short name T858
Test name
Test status
Simulation time 201606293 ps
CPU time 0.97 seconds
Started Jun 30 04:22:52 PM PDT 24
Finished Jun 30 04:22:55 PM PDT 24
Peak memory 195972 kb
Host smart-f92f1453-de48-4433-bfab-cea52e37e20e
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1673236069 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 21.gpio_smoke_en_cdc_prim.1673236069
Directory /workspace/21.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/21.gpio_smoke_no_pullup_pulldown_en_cdc_prim.856051721
Short name T878
Test name
Test status
Simulation time 73300216 ps
CPU time 1.03 seconds
Started Jun 30 04:21:52 PM PDT 24
Finished Jun 30 04:21:54 PM PDT 24
Peak memory 196452 kb
Host smart-0abb011a-fa6b-4fbe-969e-2efd1aa19b35
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=856051721 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 21.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.856051721
Directory /workspace/21.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/22.gpio_smoke_en_cdc_prim.3600393809
Short name T905
Test name
Test status
Simulation time 77842756 ps
CPU time 0.79 seconds
Started Jun 30 04:23:10 PM PDT 24
Finished Jun 30 04:23:11 PM PDT 24
Peak memory 195628 kb
Host smart-91f0e3ae-fa6f-4c34-824b-f88c1553da4e
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3600393809 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 22.gpio_smoke_en_cdc_prim.3600393809
Directory /workspace/22.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/22.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2408265934
Short name T926
Test name
Test status
Simulation time 29068947 ps
CPU time 0.93 seconds
Started Jun 30 04:22:47 PM PDT 24
Finished Jun 30 04:22:50 PM PDT 24
Peak memory 197900 kb
Host smart-e9f17281-028c-446a-a92f-5bac8f789321
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2408265934 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 22.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2408265934
Directory /workspace/22.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/23.gpio_smoke_en_cdc_prim.3436535455
Short name T918
Test name
Test status
Simulation time 204235277 ps
CPU time 0.99 seconds
Started Jun 30 04:21:52 PM PDT 24
Finished Jun 30 04:21:54 PM PDT 24
Peak memory 195828 kb
Host smart-2b79fb87-0f7c-49d3-b6bd-f97c2ae8bd2f
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3436535455 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 23.gpio_smoke_en_cdc_prim.3436535455
Directory /workspace/23.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/23.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3952963022
Short name T896
Test name
Test status
Simulation time 63330535 ps
CPU time 1.45 seconds
Started Jun 30 04:21:52 PM PDT 24
Finished Jun 30 04:21:54 PM PDT 24
Peak memory 196264 kb
Host smart-abb0a71f-1d3a-44b1-bf81-ad575cfe6f23
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3952963022 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 23.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3952963022
Directory /workspace/23.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/24.gpio_smoke_en_cdc_prim.2850463682
Short name T922
Test name
Test status
Simulation time 41561526 ps
CPU time 0.84 seconds
Started Jun 30 04:19:11 PM PDT 24
Finished Jun 30 04:19:12 PM PDT 24
Peak memory 195592 kb
Host smart-eecaa241-fc7a-4c44-bcd1-dbd9a4dc91a5
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2850463682 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 24.gpio_smoke_en_cdc_prim.2850463682
Directory /workspace/24.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/24.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2152889118
Short name T935
Test name
Test status
Simulation time 60484936 ps
CPU time 1.41 seconds
Started Jun 30 04:22:49 PM PDT 24
Finished Jun 30 04:22:53 PM PDT 24
Peak memory 196588 kb
Host smart-faea5e46-756c-4ef0-b9db-a2cb30987fcb
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2152889118 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 24.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2152889118
Directory /workspace/24.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/25.gpio_smoke_en_cdc_prim.3923282534
Short name T884
Test name
Test status
Simulation time 258941790 ps
CPU time 1.21 seconds
Started Jun 30 04:18:29 PM PDT 24
Finished Jun 30 04:18:31 PM PDT 24
Peak memory 196896 kb
Host smart-e4754a1f-07ce-4e5b-9bab-800a5f94789c
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3923282534 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 25.gpio_smoke_en_cdc_prim.3923282534
Directory /workspace/25.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/25.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2326192310
Short name T857
Test name
Test status
Simulation time 51877253 ps
CPU time 1.03 seconds
Started Jun 30 04:19:21 PM PDT 24
Finished Jun 30 04:19:22 PM PDT 24
Peak memory 198668 kb
Host smart-dfe85b4e-403c-4a5b-a2a8-430affcc33c3
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2326192310 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 25.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2326192310
Directory /workspace/25.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/26.gpio_smoke_en_cdc_prim.4117752282
Short name T846
Test name
Test status
Simulation time 87453469 ps
CPU time 0.75 seconds
Started Jun 30 04:22:06 PM PDT 24
Finished Jun 30 04:22:09 PM PDT 24
Peak memory 194540 kb
Host smart-cf8d34d4-6e85-4cb9-8be7-ec734409577f
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=4117752282 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 26.gpio_smoke_en_cdc_prim.4117752282
Directory /workspace/26.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/26.gpio_smoke_no_pullup_pulldown_en_cdc_prim.137720659
Short name T938
Test name
Test status
Simulation time 89900208 ps
CPU time 0.95 seconds
Started Jun 30 04:22:06 PM PDT 24
Finished Jun 30 04:22:10 PM PDT 24
Peak memory 195664 kb
Host smart-db29c8fe-e8c8-4ad4-85ec-fff38f114c87
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=137720659 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 26.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.137720659
Directory /workspace/26.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/27.gpio_smoke_en_cdc_prim.2001527571
Short name T907
Test name
Test status
Simulation time 47997906 ps
CPU time 0.97 seconds
Started Jun 30 04:21:07 PM PDT 24
Finished Jun 30 04:21:08 PM PDT 24
Peak memory 196216 kb
Host smart-865327e8-02c9-4a34-b170-51c6acf629d7
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2001527571 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 27.gpio_smoke_en_cdc_prim.2001527571
Directory /workspace/27.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/27.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2563282677
Short name T868
Test name
Test status
Simulation time 135849461 ps
CPU time 1.29 seconds
Started Jun 30 04:22:06 PM PDT 24
Finished Jun 30 04:22:10 PM PDT 24
Peak memory 195496 kb
Host smart-cafacdba-0954-43d8-851b-bfd9646e2588
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2563282677 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 27.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2563282677
Directory /workspace/27.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/28.gpio_smoke_en_cdc_prim.2912681095
Short name T940
Test name
Test status
Simulation time 457996807 ps
CPU time 1.2 seconds
Started Jun 30 04:20:04 PM PDT 24
Finished Jun 30 04:20:06 PM PDT 24
Peak memory 196284 kb
Host smart-7340a4be-0e53-4857-89e9-b84d93fcb1f7
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2912681095 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 28.gpio_smoke_en_cdc_prim.2912681095
Directory /workspace/28.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/28.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1799942246
Short name T921
Test name
Test status
Simulation time 54154931 ps
CPU time 1.04 seconds
Started Jun 30 04:22:15 PM PDT 24
Finished Jun 30 04:22:17 PM PDT 24
Peak memory 196172 kb
Host smart-fc73b83f-7864-4674-a359-2d3ad11c876d
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1799942246 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 28.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1799942246
Directory /workspace/28.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/29.gpio_smoke_en_cdc_prim.1208842595
Short name T936
Test name
Test status
Simulation time 226097000 ps
CPU time 1.48 seconds
Started Jun 30 04:18:41 PM PDT 24
Finished Jun 30 04:18:43 PM PDT 24
Peak memory 197108 kb
Host smart-d2f0ce59-e258-4934-a9fa-2d3e93c4aa0a
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1208842595 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 29.gpio_smoke_en_cdc_prim.1208842595
Directory /workspace/29.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/29.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3735530722
Short name T906
Test name
Test status
Simulation time 87095482 ps
CPU time 1.42 seconds
Started Jun 30 04:22:15 PM PDT 24
Finished Jun 30 04:22:17 PM PDT 24
Peak memory 197136 kb
Host smart-b840b5ef-fe4e-4234-8a15-4c961259ceba
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3735530722 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 29.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3735530722
Directory /workspace/29.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/3.gpio_smoke_en_cdc_prim.2518662474
Short name T919
Test name
Test status
Simulation time 42220572 ps
CPU time 0.99 seconds
Started Jun 30 04:18:47 PM PDT 24
Finished Jun 30 04:18:49 PM PDT 24
Peak memory 196820 kb
Host smart-beeddf0c-01b1-4ddb-a5e3-608bdcdd697d
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2518662474 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 3.gpio_smoke_en_cdc_prim.2518662474
Directory /workspace/3.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/3.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3029269052
Short name T924
Test name
Test status
Simulation time 77075950 ps
CPU time 1.18 seconds
Started Jun 30 04:18:16 PM PDT 24
Finished Jun 30 04:18:18 PM PDT 24
Peak memory 196324 kb
Host smart-8bc34810-b3a2-4d46-90a3-229e96fb5f16
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3029269052 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 3.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.3029269052
Directory /workspace/3.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/30.gpio_smoke_en_cdc_prim.3838715977
Short name T894
Test name
Test status
Simulation time 20174658 ps
CPU time 0.71 seconds
Started Jun 30 04:22:00 PM PDT 24
Finished Jun 30 04:22:02 PM PDT 24
Peak memory 191436 kb
Host smart-8dc52e45-b76c-4c18-84f8-68d8fefe60fe
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3838715977 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 30.gpio_smoke_en_cdc_prim.3838715977
Directory /workspace/30.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/30.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1657113688
Short name T909
Test name
Test status
Simulation time 106813877 ps
CPU time 0.81 seconds
Started Jun 30 04:19:45 PM PDT 24
Finished Jun 30 04:19:46 PM PDT 24
Peak memory 195960 kb
Host smart-6047c6ea-165f-491a-95ae-b0abe317a8d6
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1657113688 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 30.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1657113688
Directory /workspace/30.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/31.gpio_smoke_en_cdc_prim.439045383
Short name T915
Test name
Test status
Simulation time 35619105 ps
CPU time 1 seconds
Started Jun 30 04:18:56 PM PDT 24
Finished Jun 30 04:18:58 PM PDT 24
Peak memory 198308 kb
Host smart-40598fed-7264-42f5-b38d-a754f55dc149
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=439045383 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 31.gpio_smoke_en_cdc_prim.439045383
Directory /workspace/31.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/31.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2544661167
Short name T923
Test name
Test status
Simulation time 168471369 ps
CPU time 1.2 seconds
Started Jun 30 04:20:49 PM PDT 24
Finished Jun 30 04:20:50 PM PDT 24
Peak memory 196744 kb
Host smart-6fd32f61-5ab6-41f0-8448-8ada1f4c2e51
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2544661167 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 31.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2544661167
Directory /workspace/31.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/32.gpio_smoke_en_cdc_prim.3587205588
Short name T887
Test name
Test status
Simulation time 82001777 ps
CPU time 1.18 seconds
Started Jun 30 04:22:01 PM PDT 24
Finished Jun 30 04:22:03 PM PDT 24
Peak memory 196280 kb
Host smart-ac020957-0f7f-43e9-b9f3-aca90aff9c89
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3587205588 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 32.gpio_smoke_en_cdc_prim.3587205588
Directory /workspace/32.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/32.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2468638602
Short name T873
Test name
Test status
Simulation time 73585501 ps
CPU time 1.23 seconds
Started Jun 30 04:22:15 PM PDT 24
Finished Jun 30 04:22:18 PM PDT 24
Peak memory 196724 kb
Host smart-265c96f9-b478-4b78-8929-23b562ea1978
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2468638602 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 32.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2468638602
Directory /workspace/32.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/33.gpio_smoke_en_cdc_prim.314263854
Short name T913
Test name
Test status
Simulation time 34048277 ps
CPU time 1.04 seconds
Started Jun 30 04:19:34 PM PDT 24
Finished Jun 30 04:19:35 PM PDT 24
Peak memory 195996 kb
Host smart-8b7c4da2-2edd-4fa0-9441-134059a0b340
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=314263854 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 33.gpio_smoke_en_cdc_prim.314263854
Directory /workspace/33.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/33.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1449189643
Short name T883
Test name
Test status
Simulation time 21746610 ps
CPU time 0.79 seconds
Started Jun 30 04:19:33 PM PDT 24
Finished Jun 30 04:19:34 PM PDT 24
Peak memory 196420 kb
Host smart-8e2d01af-0a99-40b5-af16-48bfbc5919c8
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1449189643 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 33.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1449189643
Directory /workspace/33.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/34.gpio_smoke_en_cdc_prim.190872353
Short name T855
Test name
Test status
Simulation time 210713644 ps
CPU time 0.93 seconds
Started Jun 30 04:20:07 PM PDT 24
Finished Jun 30 04:20:08 PM PDT 24
Peak memory 196888 kb
Host smart-3603e8c3-85db-4a19-8cc3-3ed5789828bb
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=190872353 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 34.gpio_smoke_en_cdc_prim.190872353
Directory /workspace/34.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/34.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1076558090
Short name T862
Test name
Test status
Simulation time 106039415 ps
CPU time 0.93 seconds
Started Jun 30 04:22:07 PM PDT 24
Finished Jun 30 04:22:09 PM PDT 24
Peak memory 198104 kb
Host smart-d14536a1-7a6b-435f-9e99-c3a9967ddd7b
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1076558090 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 34.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1076558090
Directory /workspace/34.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/35.gpio_smoke_en_cdc_prim.3486286388
Short name T911
Test name
Test status
Simulation time 29453234 ps
CPU time 0.83 seconds
Started Jun 30 04:22:05 PM PDT 24
Finished Jun 30 04:22:07 PM PDT 24
Peak memory 196664 kb
Host smart-0fa212c8-a7c3-4d5c-a0fb-19391e91d41f
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3486286388 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 35.gpio_smoke_en_cdc_prim.3486286388
Directory /workspace/35.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/35.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3227789154
Short name T932
Test name
Test status
Simulation time 55689981 ps
CPU time 1.34 seconds
Started Jun 30 04:22:50 PM PDT 24
Finished Jun 30 04:22:53 PM PDT 24
Peak memory 197044 kb
Host smart-67ddd543-877c-4b48-9c66-eb0e1ce7867b
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3227789154 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 35.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3227789154
Directory /workspace/35.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/36.gpio_smoke_en_cdc_prim.2600197349
Short name T870
Test name
Test status
Simulation time 180294445 ps
CPU time 1.32 seconds
Started Jun 30 04:22:06 PM PDT 24
Finished Jun 30 04:22:08 PM PDT 24
Peak memory 197164 kb
Host smart-1cf28ff8-546c-442a-974d-f589726003b8
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2600197349 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 36.gpio_smoke_en_cdc_prim.2600197349
Directory /workspace/36.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/36.gpio_smoke_no_pullup_pulldown_en_cdc_prim.232203841
Short name T933
Test name
Test status
Simulation time 79194368 ps
CPU time 1.03 seconds
Started Jun 30 04:22:35 PM PDT 24
Finished Jun 30 04:22:37 PM PDT 24
Peak memory 195324 kb
Host smart-95fa6efd-2ce8-4a6d-83b8-fd6c835afaec
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=232203841 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 36.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.232203841
Directory /workspace/36.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/37.gpio_smoke_en_cdc_prim.2637164660
Short name T914
Test name
Test status
Simulation time 21839226 ps
CPU time 0.75 seconds
Started Jun 30 04:19:51 PM PDT 24
Finished Jun 30 04:19:52 PM PDT 24
Peak memory 195660 kb
Host smart-dff1cc9b-7eb9-4294-bb75-34b403f7b1ba
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2637164660 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 37.gpio_smoke_en_cdc_prim.2637164660
Directory /workspace/37.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/37.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1018328091
Short name T874
Test name
Test status
Simulation time 302332951 ps
CPU time 1.29 seconds
Started Jun 30 04:22:39 PM PDT 24
Finished Jun 30 04:22:42 PM PDT 24
Peak memory 197392 kb
Host smart-bcd5294b-a004-4114-809a-86adb3fdb8d7
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1018328091 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 37.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1018328091
Directory /workspace/37.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/38.gpio_smoke_en_cdc_prim.3132332249
Short name T899
Test name
Test status
Simulation time 101565234 ps
CPU time 1.09 seconds
Started Jun 30 04:18:55 PM PDT 24
Finished Jun 30 04:18:56 PM PDT 24
Peak memory 196716 kb
Host smart-2e2be446-d811-4709-b353-399fcf9fbdd2
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3132332249 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 38.gpio_smoke_en_cdc_prim.3132332249
Directory /workspace/38.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/38.gpio_smoke_no_pullup_pulldown_en_cdc_prim.361497933
Short name T847
Test name
Test status
Simulation time 65467045 ps
CPU time 1.05 seconds
Started Jun 30 04:19:58 PM PDT 24
Finished Jun 30 04:19:59 PM PDT 24
Peak memory 196156 kb
Host smart-4099b357-3e02-41da-8bc9-be3c3fb722fa
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=361497933 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 38.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.361497933
Directory /workspace/38.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/39.gpio_smoke_en_cdc_prim.4168190745
Short name T931
Test name
Test status
Simulation time 116531382 ps
CPU time 1.1 seconds
Started Jun 30 04:22:53 PM PDT 24
Finished Jun 30 04:22:57 PM PDT 24
Peak memory 196836 kb
Host smart-b0940e02-81d7-405b-a7e2-4748445c0615
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=4168190745 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 39.gpio_smoke_en_cdc_prim.4168190745
Directory /workspace/39.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/39.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4247198605
Short name T939
Test name
Test status
Simulation time 208479356 ps
CPU time 1.07 seconds
Started Jun 30 04:21:56 PM PDT 24
Finished Jun 30 04:21:59 PM PDT 24
Peak memory 196348 kb
Host smart-e655f22d-94f6-442f-872c-2a87abf96185
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4247198605 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 39.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.4247198605
Directory /workspace/39.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/4.gpio_smoke_en_cdc_prim.2909541633
Short name T875
Test name
Test status
Simulation time 95508987 ps
CPU time 0.93 seconds
Started Jun 30 04:18:24 PM PDT 24
Finished Jun 30 04:18:25 PM PDT 24
Peak memory 196784 kb
Host smart-7b4df8cb-e519-48d3-a6cd-dbe7e13f8483
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2909541633 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 4.gpio_smoke_en_cdc_prim.2909541633
Directory /workspace/4.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/4.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1997726384
Short name T871
Test name
Test status
Simulation time 80090921 ps
CPU time 1.36 seconds
Started Jun 30 04:18:16 PM PDT 24
Finished Jun 30 04:18:18 PM PDT 24
Peak memory 196532 kb
Host smart-f9093527-2406-4646-8766-4599f2299495
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1997726384 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 4.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.1997726384
Directory /workspace/4.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/40.gpio_smoke_en_cdc_prim.161502148
Short name T881
Test name
Test status
Simulation time 106038499 ps
CPU time 1.55 seconds
Started Jun 30 04:21:56 PM PDT 24
Finished Jun 30 04:21:59 PM PDT 24
Peak memory 196164 kb
Host smart-03d2d57c-8c1d-4480-a984-8a4f70ddac98
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=161502148 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 40.gpio_smoke_en_cdc_prim.161502148
Directory /workspace/40.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/40.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3669231047
Short name T877
Test name
Test status
Simulation time 104297205 ps
CPU time 1.02 seconds
Started Jun 30 04:22:27 PM PDT 24
Finished Jun 30 04:22:29 PM PDT 24
Peak memory 196536 kb
Host smart-9654a93f-24c9-4946-a789-993ffdfd76ef
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3669231047 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 40.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3669231047
Directory /workspace/40.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/41.gpio_smoke_en_cdc_prim.242095037
Short name T869
Test name
Test status
Simulation time 255161762 ps
CPU time 1.25 seconds
Started Jun 30 04:22:12 PM PDT 24
Finished Jun 30 04:22:14 PM PDT 24
Peak memory 196700 kb
Host smart-d9795e66-fca6-47d5-b077-ca577636cbe1
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=242095037 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 41.gpio_smoke_en_cdc_prim.242095037
Directory /workspace/41.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/41.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2956799599
Short name T895
Test name
Test status
Simulation time 47235863 ps
CPU time 0.93 seconds
Started Jun 30 04:22:27 PM PDT 24
Finished Jun 30 04:22:28 PM PDT 24
Peak memory 197716 kb
Host smart-f3195cac-ac60-45b1-b83c-07806f6fa0b3
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2956799599 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 41.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2956799599
Directory /workspace/41.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/42.gpio_smoke_en_cdc_prim.1425137303
Short name T892
Test name
Test status
Simulation time 91293778 ps
CPU time 0.93 seconds
Started Jun 30 04:20:16 PM PDT 24
Finished Jun 30 04:20:18 PM PDT 24
Peak memory 197148 kb
Host smart-63d7d9e8-ac71-4522-928e-bfd3144fc4cd
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1425137303 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 42.gpio_smoke_en_cdc_prim.1425137303
Directory /workspace/42.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/42.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2256784556
Short name T848
Test name
Test status
Simulation time 304694093 ps
CPU time 0.81 seconds
Started Jun 30 04:22:42 PM PDT 24
Finished Jun 30 04:22:46 PM PDT 24
Peak memory 195732 kb
Host smart-fcd38266-7180-45e9-883e-c32923d00371
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2256784556 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 42.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2256784556
Directory /workspace/42.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/43.gpio_smoke_en_cdc_prim.2875942793
Short name T890
Test name
Test status
Simulation time 42396256 ps
CPU time 1.26 seconds
Started Jun 30 04:18:56 PM PDT 24
Finished Jun 30 04:18:58 PM PDT 24
Peak memory 198644 kb
Host smart-2824a470-88dc-4ad6-9cf5-69b926b0d82a
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2875942793 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 43.gpio_smoke_en_cdc_prim.2875942793
Directory /workspace/43.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/43.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2256197736
Short name T910
Test name
Test status
Simulation time 89881288 ps
CPU time 0.76 seconds
Started Jun 30 04:22:13 PM PDT 24
Finished Jun 30 04:22:15 PM PDT 24
Peak memory 196376 kb
Host smart-92ab8399-903d-4d3f-9c59-e2c738b3400b
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2256197736 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 43.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2256197736
Directory /workspace/43.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/44.gpio_smoke_en_cdc_prim.757481778
Short name T849
Test name
Test status
Simulation time 136757638 ps
CPU time 0.95 seconds
Started Jun 30 04:19:44 PM PDT 24
Finished Jun 30 04:19:45 PM PDT 24
Peak memory 196940 kb
Host smart-e69c1be0-4b10-4a56-8245-9e928622635c
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=757481778 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 44.gpio_smoke_en_cdc_prim.757481778
Directory /workspace/44.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/44.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3033542364
Short name T879
Test name
Test status
Simulation time 199535450 ps
CPU time 1.41 seconds
Started Jun 30 04:22:18 PM PDT 24
Finished Jun 30 04:22:20 PM PDT 24
Peak memory 195420 kb
Host smart-e7fe7c59-f41a-4100-b6b7-3931417df87c
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3033542364 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 44.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3033542364
Directory /workspace/44.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/45.gpio_smoke_en_cdc_prim.704240790
Short name T934
Test name
Test status
Simulation time 80732141 ps
CPU time 1.29 seconds
Started Jun 30 04:22:44 PM PDT 24
Finished Jun 30 04:22:49 PM PDT 24
Peak memory 198244 kb
Host smart-d710a349-decc-4a0c-9d7a-bf571278a905
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=704240790 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 45.gpio_smoke_en_cdc_prim.704240790
Directory /workspace/45.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/45.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3645766132
Short name T889
Test name
Test status
Simulation time 120933788 ps
CPU time 0.94 seconds
Started Jun 30 04:22:42 PM PDT 24
Finished Jun 30 04:22:47 PM PDT 24
Peak memory 196072 kb
Host smart-0989160e-8122-4871-a199-de66222fb06e
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3645766132 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 45.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3645766132
Directory /workspace/45.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/46.gpio_smoke_en_cdc_prim.3060270906
Short name T863
Test name
Test status
Simulation time 170889241 ps
CPU time 1.24 seconds
Started Jun 30 04:22:48 PM PDT 24
Finished Jun 30 04:22:51 PM PDT 24
Peak memory 196880 kb
Host smart-fe37584c-ef15-443a-aa1b-278d7e900e88
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3060270906 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 46.gpio_smoke_en_cdc_prim.3060270906
Directory /workspace/46.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/46.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1161655678
Short name T852
Test name
Test status
Simulation time 266238175 ps
CPU time 1.23 seconds
Started Jun 30 04:22:46 PM PDT 24
Finished Jun 30 04:22:49 PM PDT 24
Peak memory 196792 kb
Host smart-b223b79d-0681-4e8a-9cf6-a2b231cd6199
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1161655678 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 46.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1161655678
Directory /workspace/46.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/47.gpio_smoke_en_cdc_prim.4292385809
Short name T880
Test name
Test status
Simulation time 60210730 ps
CPU time 1.07 seconds
Started Jun 30 04:22:45 PM PDT 24
Finished Jun 30 04:22:49 PM PDT 24
Peak memory 196864 kb
Host smart-c2b4603d-9fe0-4838-b0e7-094142975b93
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=4292385809 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 47.gpio_smoke_en_cdc_prim.4292385809
Directory /workspace/47.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/47.gpio_smoke_no_pullup_pulldown_en_cdc_prim.92580453
Short name T937
Test name
Test status
Simulation time 165243195 ps
CPU time 1.09 seconds
Started Jun 30 04:22:51 PM PDT 24
Finished Jun 30 04:22:53 PM PDT 24
Peak memory 196892 kb
Host smart-83da9f04-c0e8-4ed7-ab1e-b5c31c4983ed
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92580453 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 47.gpio_smoke_no_pullup_pulldown_e
n_cdc_prim.92580453
Directory /workspace/47.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/48.gpio_smoke_en_cdc_prim.2829948219
Short name T861
Test name
Test status
Simulation time 47711706 ps
CPU time 1.17 seconds
Started Jun 30 04:22:56 PM PDT 24
Finished Jun 30 04:22:59 PM PDT 24
Peak memory 198244 kb
Host smart-81eca2f8-056e-4b3b-a461-0c8381778e49
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2829948219 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 48.gpio_smoke_en_cdc_prim.2829948219
Directory /workspace/48.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/48.gpio_smoke_no_pullup_pulldown_en_cdc_prim.70436908
Short name T888
Test name
Test status
Simulation time 75172179 ps
CPU time 1.1 seconds
Started Jun 30 04:22:48 PM PDT 24
Finished Jun 30 04:22:51 PM PDT 24
Peak memory 198348 kb
Host smart-29c925a7-262c-401f-9ea0-0e4021c9d611
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70436908 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 48.gpio_smoke_no_pullup_pulldown_e
n_cdc_prim.70436908
Directory /workspace/48.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/49.gpio_smoke_en_cdc_prim.1268656005
Short name T908
Test name
Test status
Simulation time 100524595 ps
CPU time 1.31 seconds
Started Jun 30 04:22:56 PM PDT 24
Finished Jun 30 04:23:00 PM PDT 24
Peak memory 196844 kb
Host smart-21f7b383-2b41-4b3b-ba53-8184ef1e6359
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1268656005 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 49.gpio_smoke_en_cdc_prim.1268656005
Directory /workspace/49.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/49.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3106697753
Short name T853
Test name
Test status
Simulation time 47734353 ps
CPU time 1.22 seconds
Started Jun 30 04:22:45 PM PDT 24
Finished Jun 30 04:22:49 PM PDT 24
Peak memory 197188 kb
Host smart-0929ce31-883f-4a78-a345-0cb2ac9d753f
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3106697753 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 49.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3106697753
Directory /workspace/49.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/5.gpio_smoke_en_cdc_prim.2760857381
Short name T876
Test name
Test status
Simulation time 108782019 ps
CPU time 0.87 seconds
Started Jun 30 04:17:40 PM PDT 24
Finished Jun 30 04:17:41 PM PDT 24
Peak memory 195760 kb
Host smart-39dd0a1c-0563-40fd-ae2d-3ae276d48b98
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2760857381 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 5.gpio_smoke_en_cdc_prim.2760857381
Directory /workspace/5.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/5.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3082573709
Short name T900
Test name
Test status
Simulation time 220133541 ps
CPU time 1.1 seconds
Started Jun 30 04:22:10 PM PDT 24
Finished Jun 30 04:22:13 PM PDT 24
Peak memory 196164 kb
Host smart-2261f9dd-b6cc-4410-8333-4abafea665d5
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3082573709 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 5.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.3082573709
Directory /workspace/5.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/6.gpio_smoke_en_cdc_prim.1700594167
Short name T901
Test name
Test status
Simulation time 242572533 ps
CPU time 1.21 seconds
Started Jun 30 04:19:45 PM PDT 24
Finished Jun 30 04:19:47 PM PDT 24
Peak memory 198308 kb
Host smart-a4e53dbf-b987-45a9-8599-61fd7943540f
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1700594167 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 6.gpio_smoke_en_cdc_prim.1700594167
Directory /workspace/6.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/6.gpio_smoke_no_pullup_pulldown_en_cdc_prim.280057913
Short name T928
Test name
Test status
Simulation time 111299173 ps
CPU time 0.97 seconds
Started Jun 30 04:22:40 PM PDT 24
Finished Jun 30 04:22:43 PM PDT 24
Peak memory 196428 kb
Host smart-540251ad-e572-45a2-8000-ebf58e807630
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=280057913 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 6.gpio_smoke_no_pullup_pulldown_e
n_cdc_prim.280057913
Directory /workspace/6.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/7.gpio_smoke_en_cdc_prim.1371344910
Short name T943
Test name
Test status
Simulation time 45441669 ps
CPU time 0.9 seconds
Started Jun 30 04:19:22 PM PDT 24
Finished Jun 30 04:19:23 PM PDT 24
Peak memory 195804 kb
Host smart-682d2112-e337-4fca-85e3-8f353696ad38
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1371344910 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 7.gpio_smoke_en_cdc_prim.1371344910
Directory /workspace/7.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/7.gpio_smoke_no_pullup_pulldown_en_cdc_prim.424168444
Short name T902
Test name
Test status
Simulation time 82368874 ps
CPU time 0.84 seconds
Started Jun 30 04:17:56 PM PDT 24
Finished Jun 30 04:17:57 PM PDT 24
Peak memory 196128 kb
Host smart-de979f4f-9df1-4026-b721-b6812e5e8f57
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=424168444 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 7.gpio_smoke_no_pullup_pulldown_e
n_cdc_prim.424168444
Directory /workspace/7.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/8.gpio_smoke_en_cdc_prim.1393602943
Short name T920
Test name
Test status
Simulation time 237985923 ps
CPU time 1.07 seconds
Started Jun 30 04:20:50 PM PDT 24
Finished Jun 30 04:20:52 PM PDT 24
Peak memory 196160 kb
Host smart-f02733cb-89d1-49e4-b9bf-bd00bf01d6d0
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1393602943 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 8.gpio_smoke_en_cdc_prim.1393602943
Directory /workspace/8.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/8.gpio_smoke_no_pullup_pulldown_en_cdc_prim.671155033
Short name T850
Test name
Test status
Simulation time 131272594 ps
CPU time 0.89 seconds
Started Jun 30 04:20:47 PM PDT 24
Finished Jun 30 04:20:48 PM PDT 24
Peak memory 191852 kb
Host smart-d050af6c-4aa8-4d37-b89b-37d0d2963e46
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=671155033 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 8.gpio_smoke_no_pullup_pulldown_e
n_cdc_prim.671155033
Directory /workspace/8.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/9.gpio_smoke_en_cdc_prim.2088233003
Short name T851
Test name
Test status
Simulation time 106674096 ps
CPU time 1.02 seconds
Started Jun 30 04:22:09 PM PDT 24
Finished Jun 30 04:22:12 PM PDT 24
Peak memory 198192 kb
Host smart-d5e484d2-5984-4f25-ae4c-daaf876c8541
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2088233003 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 9.gpio_smoke_en_cdc_prim.2088233003
Directory /workspace/9.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/9.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1813706211
Short name T929
Test name
Test status
Simulation time 40950770 ps
CPU time 1.15 seconds
Started Jun 30 04:22:50 PM PDT 24
Finished Jun 30 04:22:53 PM PDT 24
Peak memory 197908 kb
Host smart-5c8d2d29-c0ab-4bae-a02f-ef58a149cc43
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1813706211 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 9.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.1813706211
Directory /workspace/9.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest
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