Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	36	0	36	100.00
Crosses	128	0	128	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	32	0	32	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	128	0	128	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	32	0	32	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	3490328	1			T24	1		T25	1		T26	656
all_pins[1]	3490328	1			T24	1		T25	1		T26	656
all_pins[2]	3490328	1			T24	1		T25	1		T26	656
all_pins[3]	3490328	1			T24	1		T25	1		T26	656
all_pins[4]	3490328	1			T24	1		T25	1		T26	656
all_pins[5]	3490328	1			T24	1		T25	1		T26	656
all_pins[6]	3490328	1			T24	1		T25	1		T26	656
all_pins[7]	3490328	1			T24	1		T25	1		T26	656
all_pins[8]	3490328	1			T24	1		T25	1		T26	656
all_pins[9]	3490328	1			T24	1		T25	1		T26	656
all_pins[10]	3490328	1			T24	1		T25	1		T26	656
all_pins[11]	3490328	1			T24	1		T25	1		T26	656
all_pins[12]	3490328	1			T24	1		T25	1		T26	656
all_pins[13]	3490328	1			T24	1		T25	1		T26	656
all_pins[14]	3490328	1			T24	1		T25	1		T26	656
all_pins[15]	3490328	1			T24	1		T25	1		T26	656
all_pins[16]	3490328	1			T24	1		T25	1		T26	656
all_pins[17]	3490328	1			T24	1		T25	1		T26	656
all_pins[18]	3490328	1			T24	1		T25	1		T26	656
all_pins[19]	3490328	1			T24	1		T25	1		T26	656
all_pins[20]	3490328	1			T24	1		T25	1		T26	656
all_pins[21]	3490328	1			T24	1		T25	1		T26	656
all_pins[22]	3490328	1			T24	1		T25	1		T26	656
all_pins[23]	3490328	1			T24	1		T25	1		T26	656
all_pins[24]	3490328	1			T24	1		T25	1		T26	656
all_pins[25]	3490328	1			T24	1		T25	1		T26	656
all_pins[26]	3490328	1			T24	1		T25	1		T26	656
all_pins[27]	3490328	1			T24	1		T25	1		T26	656
all_pins[28]	3490328	1			T24	1		T25	1		T26	656
all_pins[29]	3490328	1			T24	1		T25	1		T26	656
all_pins[30]	3490328	1			T24	1		T25	1		T26	656
all_pins[31]	3490328	1			T24	1		T25	1		T26	656

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	69372798	1			T24	32		T25	32		T26	12905
values[0x1]	42317698	1			T26	8087		T1	6757		T11	2708
transitions[0x0=>0x1]	25358120	1			T26	4616		T1	4081		T11	1674
transitions[0x1=>0x0]	25357974	1			T26	4616		T1	4081		T11	1673

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	2164907	1			T24	1		T25	1		T26	411
all_pins[0]	values[0x1]	1325421	1			T26	245		T1	153		T11	71
all_pins[0]	transitions[0x0=>0x1]	822903	1			T26	172		T1	65		T11	54
all_pins[0]	transitions[0x1=>0x0]	815148	1			T26	137		T1	165		T11	50
all_pins[1]	values[0x0]	2169700	1			T24	1		T25	1		T26	384
all_pins[1]	values[0x1]	1320628	1			T26	272		T1	220		T11	94
all_pins[1]	transitions[0x0=>0x1]	788952	1			T26	149		T1	153		T11	53
all_pins[1]	transitions[0x1=>0x0]	793745	1			T26	122		T1	86		T11	30
all_pins[2]	values[0x0]	2166985	1			T24	1		T25	1		T26	401
all_pins[2]	values[0x1]	1323343	1			T26	255		T1	247		T11	84
all_pins[2]	transitions[0x0=>0x1]	792269	1			T26	131		T1	162		T11	51
all_pins[2]	transitions[0x1=>0x0]	789554	1			T26	148		T1	135		T11	61
all_pins[3]	values[0x0]	2169982	1			T24	1		T25	1		T26	425
all_pins[3]	values[0x1]	1320346	1			T26	231		T1	184		T11	80
all_pins[3]	transitions[0x0=>0x1]	788881	1			T26	157		T1	83		T11	47
all_pins[3]	transitions[0x1=>0x0]	791878	1			T26	181		T1	146		T11	51
all_pins[4]	values[0x0]	2169884	1			T24	1		T25	1		T26	499
all_pins[4]	values[0x1]	1320444	1			T26	157		T1	210		T11	83
all_pins[4]	transitions[0x0=>0x1]	789497	1			T26	81		T1	140		T11	60
all_pins[4]	transitions[0x1=>0x0]	789399	1			T26	155		T1	114		T11	57
all_pins[5]	values[0x0]	2164131	1			T24	1		T25	1		T26	334
all_pins[5]	values[0x1]	1326197	1			T26	322		T1	270		T11	100
all_pins[5]	transitions[0x0=>0x1]	794822	1			T26	236		T1	166		T11	50
all_pins[5]	transitions[0x1=>0x0]	789069	1			T26	71		T1	106		T11	33
all_pins[6]	values[0x0]	2169217	1			T24	1		T25	1		T26	410
all_pins[6]	values[0x1]	1321111	1			T26	246		T1	219		T11	65
all_pins[6]	transitions[0x0=>0x1]	787734	1			T26	116		T1	115		T11	36
all_pins[6]	transitions[0x1=>0x0]	792820	1			T26	192		T1	166		T11	71
all_pins[7]	values[0x0]	2168498	1			T24	1		T25	1		T26	383
all_pins[7]	values[0x1]	1321830	1			T26	273		T1	277		T11	98
all_pins[7]	transitions[0x0=>0x1]	790972	1			T26	169		T1	163		T11	66
all_pins[7]	transitions[0x1=>0x0]	790253	1			T26	142		T1	105		T11	33
all_pins[8]	values[0x0]	2166835	1			T24	1		T25	1		T26	416
all_pins[8]	values[0x1]	1323493	1			T26	240		T1	209		T11	115
all_pins[8]	transitions[0x0=>0x1]	791803	1			T26	151		T1	107		T11	61
all_pins[8]	transitions[0x1=>0x0]	790140	1			T26	184		T1	175		T11	44
all_pins[9]	values[0x0]	2167708	1			T24	1		T25	1		T26	372
all_pins[9]	values[0x1]	1322620	1			T26	284		T1	207		T11	53
all_pins[9]	transitions[0x0=>0x1]	788964	1			T26	164		T1	125		T11	29
all_pins[9]	transitions[0x1=>0x0]	789837	1			T26	120		T1	127		T11	91
all_pins[10]	values[0x0]	2172225	1			T24	1		T25	1		T26	371
all_pins[10]	values[0x1]	1318103	1			T26	285		T1	154		T11	122
all_pins[10]	transitions[0x0=>0x1]	789722	1			T26	163		T1	82		T11	95
all_pins[10]	transitions[0x1=>0x0]	794239	1			T26	162		T1	135		T11	26
all_pins[11]	values[0x0]	2169877	1			T24	1		T25	1		T26	467
all_pins[11]	values[0x1]	1320451	1			T26	189		T1	180		T11	89
all_pins[11]	transitions[0x0=>0x1]	792614	1			T26	87		T1	119		T11	43
all_pins[11]	transitions[0x1=>0x0]	790266	1			T26	183		T1	93		T11	76
all_pins[12]	values[0x0]	2164804	1			T24	1		T25	1		T26	418
all_pins[12]	values[0x1]	1325524	1			T26	238		T1	211		T11	80
all_pins[12]	transitions[0x0=>0x1]	795168	1			T26	165		T1	138		T11	45
all_pins[12]	transitions[0x1=>0x0]	790095	1			T26	116		T1	107		T11	54
all_pins[13]	values[0x0]	2165819	1			T24	1		T25	1		T26	428
all_pins[13]	values[0x1]	1324509	1			T26	228		T1	224		T11	101
all_pins[13]	transitions[0x0=>0x1]	790854	1			T26	129		T1	145		T11	64
all_pins[13]	transitions[0x1=>0x0]	791869	1			T26	139		T1	132		T11	43
all_pins[14]	values[0x0]	2166605	1			T24	1		T25	1		T26	415
all_pins[14]	values[0x1]	1323723	1			T26	241		T1	194		T11	61
all_pins[14]	transitions[0x0=>0x1]	790373	1			T26	130		T1	108		T11	32
all_pins[14]	transitions[0x1=>0x0]	791159	1			T26	117		T1	138		T11	72
all_pins[15]	values[0x0]	2172228	1			T24	1		T25	1		T26	402
all_pins[15]	values[0x1]	1318100	1			T26	254		T1	181		T11	70
all_pins[15]	transitions[0x0=>0x1]	788341	1			T26	151		T1	108		T11	41
all_pins[15]	transitions[0x1=>0x0]	793964	1			T26	138		T1	121		T11	32
all_pins[16]	values[0x0]	2167693	1			T24	1		T25	1		T26	471
all_pins[16]	values[0x1]	1322635	1			T26	185		T1	243		T11	92
all_pins[16]	transitions[0x0=>0x1]	794096	1			T26	102		T1	168		T11	52
all_pins[16]	transitions[0x1=>0x0]	789561	1			T26	171		T1	106		T11	30
all_pins[17]	values[0x0]	2166677	1			T24	1		T25	1		T26	421
all_pins[17]	values[0x1]	1323651	1			T26	235		T1	204		T11	90
all_pins[17]	transitions[0x0=>0x1]	791865	1			T26	141		T1	91		T11	55
all_pins[17]	transitions[0x1=>0x0]	790849	1			T26	91		T1	130		T11	57
all_pins[18]	values[0x0]	2170493	1			T24	1		T25	1		T26	482
all_pins[18]	values[0x1]	1319835	1			T26	174		T1	239		T11	49
all_pins[18]	transitions[0x0=>0x1]	790848	1			T26	99		T1	151		T11	21
all_pins[18]	transitions[0x1=>0x0]	794664	1			T26	160		T1	116		T11	62
all_pins[19]	values[0x0]	2164425	1			T24	1		T25	1		T26	383
all_pins[19]	values[0x1]	1325903	1			T26	273		T1	164		T11	118
all_pins[19]	transitions[0x0=>0x1]	794061	1			T26	197		T1	108		T11	97
all_pins[19]	transitions[0x1=>0x0]	787993	1			T26	98		T1	183		T11	28
all_pins[20]	values[0x0]	2166428	1			T24	1		T25	1		T26	330
all_pins[20]	values[0x1]	1323900	1			T26	326		T1	182		T11	76
all_pins[20]	transitions[0x0=>0x1]	791892	1			T26	165		T1	124		T11	36
all_pins[20]	transitions[0x1=>0x0]	793895	1			T26	112		T1	106		T11	78
all_pins[21]	values[0x0]	2165271	1			T24	1		T25	1		T26	372
all_pins[21]	values[0x1]	1325057	1			T26	284		T1	199		T11	96
all_pins[21]	transitions[0x0=>0x1]	791678	1			T26	118		T1	133		T11	71
all_pins[21]	transitions[0x1=>0x0]	790521	1			T26	160		T1	116		T11	51
all_pins[22]	values[0x0]	2165974	1			T24	1		T25	1		T26	276
all_pins[22]	values[0x1]	1324354	1			T26	380		T1	249		T11	68
all_pins[22]	transitions[0x0=>0x1]	793962	1			T26	216		T1	154		T11	34
all_pins[22]	transitions[0x1=>0x0]	794665	1			T26	120		T1	104		T11	62
all_pins[23]	values[0x0]	2161098	1			T24	1		T25	1		T26	416
all_pins[23]	values[0x1]	1329230	1			T26	240		T1	244		T11	123
all_pins[23]	transitions[0x0=>0x1]	794241	1			T26	79		T1	113		T11	78
all_pins[23]	transitions[0x1=>0x0]	789365	1			T26	219		T1	118		T11	23
all_pins[24]	values[0x0]	2163125	1			T24	1		T25	1		T26	352
all_pins[24]	values[0x1]	1327203	1			T26	304		T1	181		T11	78
all_pins[24]	transitions[0x0=>0x1]	794323	1			T26	189		T1	112		T11	29
all_pins[24]	transitions[0x1=>0x0]	796350	1			T26	125		T1	175		T11	74
all_pins[25]	values[0x0]	2168374	1			T24	1		T25	1		T26	393
all_pins[25]	values[0x1]	1321954	1			T26	263		T1	182		T11	76
all_pins[25]	transitions[0x0=>0x1]	790325	1			T26	148		T1	115		T11	50
all_pins[25]	transitions[0x1=>0x0]	795574	1			T26	189		T1	114		T11	52
all_pins[26]	values[0x0]	2173738	1			T24	1		T25	1		T26	404
all_pins[26]	values[0x1]	1316590	1			T26	252		T1	173		T11	61
all_pins[26]	transitions[0x0=>0x1]	790492	1			T26	121		T1	119		T11	40
all_pins[26]	transitions[0x1=>0x0]	795856	1			T26	132		T1	128		T11	55
all_pins[27]	values[0x0]	2172649	1			T24	1		T25	1		T26	402
all_pins[27]	values[0x1]	1317679	1			T26	254		T1	215		T11	94
all_pins[27]	transitions[0x0=>0x1]	790163	1			T26	136		T1	123		T11	73
all_pins[27]	transitions[0x1=>0x0]	789074	1			T26	134		T1	81		T11	40
all_pins[28]	values[0x0]	2163601	1			T24	1		T25	1		T26	415
all_pins[28]	values[0x1]	1326727	1			T26	241		T1	256		T11	94
all_pins[28]	transitions[0x0=>0x1]	795691	1			T26	135		T1	143		T11	53
all_pins[28]	transitions[0x1=>0x0]	786643	1			T26	148		T1	102		T11	53
all_pins[29]	values[0x0]	2171746	1			T24	1		T25	1		T26	383
all_pins[29]	values[0x1]	1318582	1			T26	273		T1	232		T11	90
all_pins[29]	transitions[0x0=>0x1]	788516	1			T26	159		T1	139		T11	65
all_pins[29]	transitions[0x1=>0x0]	796661	1			T26	127		T1	163		T11	69
all_pins[30]	values[0x0]	2169585	1			T24	1		T25	1		T26	423
all_pins[30]	values[0x1]	1320743	1			T26	233		T1	201		T11	69
all_pins[30]	transitions[0x0=>0x1]	793041	1			T26	120		T1	128		T11	43
all_pins[30]	transitions[0x1=>0x0]	790880	1			T26	160		T1	159		T11	64
all_pins[31]	values[0x0]	2172516	1			T24	1		T25	1		T26	446
all_pins[31]	values[0x1]	1317812	1			T26	210		T1	253		T11	68
all_pins[31]	transitions[0x0=>0x1]	789057	1			T26	140		T1	181		T11	50
all_pins[31]	transitions[0x1=>0x0]	791988	1			T26	163		T1	129		T11	51