Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=31}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=31}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=31}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	192	0	192	100.00

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=31}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	32	0	32	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=31}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	192	0	192	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	32	0	32	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	12015472	1			T24	212		T25	48		T26	1688
all_values[1]	12015472	1			T24	212		T25	48		T26	1688
all_values[2]	12015472	1			T24	212		T25	48		T26	1688
all_values[3]	12015472	1			T24	212		T25	48		T26	1688
all_values[4]	12015472	1			T24	212		T25	48		T26	1688
all_values[5]	12015472	1			T24	212		T25	48		T26	1688
all_values[6]	12015472	1			T24	212		T25	48		T26	1688
all_values[7]	12015472	1			T24	212		T25	48		T26	1688
all_values[8]	12015472	1			T24	212		T25	48		T26	1688
all_values[9]	12015472	1			T24	212		T25	48		T26	1688
all_values[10]	12015472	1			T24	212		T25	48		T26	1688
all_values[11]	12015472	1			T24	212		T25	48		T26	1688
all_values[12]	12015472	1			T24	212		T25	48		T26	1688
all_values[13]	12015472	1			T24	212		T25	48		T26	1688
all_values[14]	12015472	1			T24	212		T25	48		T26	1688
all_values[15]	12015472	1			T24	212		T25	48		T26	1688
all_values[16]	12015472	1			T24	212		T25	48		T26	1688
all_values[17]	12015472	1			T24	212		T25	48		T26	1688
all_values[18]	12015472	1			T24	212		T25	48		T26	1688
all_values[19]	12015472	1			T24	212		T25	48		T26	1688
all_values[20]	12015472	1			T24	212		T25	48		T26	1688
all_values[21]	12015472	1			T24	212		T25	48		T26	1688
all_values[22]	12015472	1			T24	212		T25	48		T26	1688
all_values[23]	12015472	1			T24	212		T25	48		T26	1688
all_values[24]	12015472	1			T24	212		T25	48		T26	1688
all_values[25]	12015472	1			T24	212		T25	48		T26	1688
all_values[26]	12015472	1			T24	212		T25	48		T26	1688
all_values[27]	12015472	1			T24	212		T25	48		T26	1688
all_values[28]	12015472	1			T24	212		T25	48		T26	1688
all_values[29]	12015472	1			T24	212		T25	48		T26	1688
all_values[30]	12015472	1			T24	212		T25	48		T26	1688
all_values[31]	12015472	1			T24	212		T25	48		T26	1688

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

226961665

1

T24

6784

T25

1536

T26

26075

auto[1]

157533439

1

T26

27941

T1

23958

T11

6257

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

99724912

1

T24

6784

T25

1536

T26

7028

auto[1]

284770192

1

T26

46988

T1

41387

T11

9988

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

380414313

1

T24

6784

T25

1536

T26

51954

auto[1]

4080791

1

T26

2062

T1

1604

T13

17

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	192	0	192	100.00
Automatically Generated Cross Bins	192	0	192	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	2639829	1			T24	212		T25	48		T26	148
all_values[0]	auto[0]	auto[0]	auto[1]	4361500	1			T26	665		T1	783		T11	151
all_values[0]	auto[0]	auto[1]	auto[0]	479422	1			T26	142		T1	73		T11	35
all_values[0]	auto[0]	auto[1]	auto[1]	4407092	1			T26	671		T1	447		T11	155
all_values[0]	auto[1]	auto[0]	auto[1]	64078	1			T26	26		T1	30		T13	1
all_values[0]	auto[1]	auto[1]	auto[1]	63551	1			T26	36		T1	14		T16	2
all_values[1]	auto[0]	auto[0]	auto[0]	2645148	1			T24	212		T25	48		T26	84
all_values[1]	auto[0]	auto[0]	auto[1]	4429683	1			T26	634		T1	498		T11	139
all_values[1]	auto[0]	auto[1]	auto[0]	479176	1			T26	133		T1	140		T11	18
all_values[1]	auto[0]	auto[1]	auto[1]	4333966	1			T26	775		T1	665		T11	182
all_values[1]	auto[1]	auto[0]	auto[1]	63864	1			T26	23		T1	26		T13	1
all_values[1]	auto[1]	auto[1]	auto[1]	63635	1			T26	39		T1	28		T16	2
all_values[2]	auto[0]	auto[0]	auto[0]	2636949	1			T24	212		T25	48		T26	129
all_values[2]	auto[0]	auto[0]	auto[1]	4371255	1			T26	731		T1	591		T11	141
all_values[2]	auto[0]	auto[1]	auto[0]	480934	1			T26	91		T1	67		T11	40
all_values[2]	auto[0]	auto[1]	auto[1]	4398902	1			T26	675		T1	720		T11	169
all_values[2]	auto[1]	auto[0]	auto[1]	63926	1			T26	29		T1	18		T16	5
all_values[2]	auto[1]	auto[1]	auto[1]	63506	1			T26	33		T1	26		T27	1323
all_values[3]	auto[0]	auto[0]	auto[0]	2643334	1			T24	212		T25	48		T26	144
all_values[3]	auto[0]	auto[0]	auto[1]	4412728	1			T26	646		T1	675		T11	198
all_values[3]	auto[0]	auto[1]	auto[0]	480010	1			T26	108		T1	86		T11	5
all_values[3]	auto[0]	auto[1]	auto[1]	4351972	1			T26	731		T1	544		T11	166
all_values[3]	auto[1]	auto[0]	auto[1]	64054	1			T26	30		T1	26		T13	1
all_values[3]	auto[1]	auto[1]	auto[1]	63374	1			T26	29		T1	23		T27	1247
all_values[4]	auto[0]	auto[0]	auto[0]	2633051	1			T24	212		T25	48		T26	167
all_values[4]	auto[0]	auto[0]	auto[1]	4405588	1			T26	969		T1	558		T11	163
all_values[4]	auto[0]	auto[1]	auto[0]	479170	1			T26	51		T1	114		T11	26
all_values[4]	auto[0]	auto[1]	auto[1]	4369989	1			T26	442		T1	684		T11	158
all_values[4]	auto[1]	auto[0]	auto[1]	64117	1			T26	41		T1	19		T13	1
all_values[4]	auto[1]	auto[1]	auto[1]	63557	1			T26	18		T1	32		T27	1315
all_values[5]	auto[0]	auto[0]	auto[0]	2632982	1			T24	212		T25	48		T26	76
all_values[5]	auto[0]	auto[0]	auto[1]	4359265	1			T26	579		T1	425		T11	159
all_values[5]	auto[0]	auto[1]	auto[0]	472913	1			T26	70		T1	109		T11	12
all_values[5]	auto[0]	auto[1]	auto[1]	4423080	1			T26	885		T1	856		T11	183
all_values[5]	auto[1]	auto[0]	auto[1]	63146	1			T26	28		T1	15		T16	2
all_values[5]	auto[1]	auto[1]	auto[1]	64086	1			T26	50		T1	29		T27	1377
all_values[6]	auto[0]	auto[0]	auto[0]	2636407	1			T24	212		T25	48		T26	92
all_values[6]	auto[0]	auto[0]	auto[1]	4407902	1			T26	737		T1	588		T11	159
all_values[6]	auto[0]	auto[1]	auto[0]	476070	1			T26	84		T1	95		T11	32
all_values[6]	auto[0]	auto[1]	auto[1]	4367401	1			T26	718		T1	616		T11	133
all_values[6]	auto[1]	auto[0]	auto[1]	64295	1			T26	35		T1	21		T13	1
all_values[6]	auto[1]	auto[1]	auto[1]	63397	1			T26	22		T1	25		T27	1320
all_values[7]	auto[0]	auto[0]	auto[0]	2650141	1			T24	212		T25	48		T26	88
all_values[7]	auto[0]	auto[0]	auto[1]	4384718	1			T26	573		T1	454		T11	93
all_values[7]	auto[0]	auto[1]	auto[0]	473453	1			T26	164		T1	97		T11	44
all_values[7]	auto[0]	auto[1]	auto[1]	4379678	1			T26	803		T1	822		T11	191
all_values[7]	auto[1]	auto[0]	auto[1]	64022	1			T26	20		T1	25		T16	5
all_values[7]	auto[1]	auto[1]	auto[1]	63460	1			T26	40		T1	31		T13	1
all_values[8]	auto[0]	auto[0]	auto[0]	2634369	1			T24	212		T25	48		T26	102
all_values[8]	auto[0]	auto[0]	auto[1]	4396975	1			T26	665		T1	657		T11	119
all_values[8]	auto[0]	auto[1]	auto[0]	477350	1			T26	136		T1	98		T11	35
all_values[8]	auto[0]	auto[1]	auto[1]	4378877	1			T26	716		T1	607		T11	206
all_values[8]	auto[1]	auto[0]	auto[1]	64199	1			T26	30		T1	29		T16	4
all_values[8]	auto[1]	auto[1]	auto[1]	63702	1			T26	39		T1	26		T16	2
all_values[9]	auto[0]	auto[0]	auto[0]	2634265	1			T24	212		T25	48		T26	98
all_values[9]	auto[0]	auto[0]	auto[1]	4412388	1			T26	591		T1	647		T11	210
all_values[9]	auto[0]	auto[1]	auto[0]	470268	1			T26	64		T1	69		T11	15
all_values[9]	auto[0]	auto[1]	auto[1]	4371173	1			T26	862		T1	603		T11	107
all_values[9]	auto[1]	auto[0]	auto[1]	64058	1			T26	34		T1	23		T16	2
all_values[9]	auto[1]	auto[1]	auto[1]	63320	1			T26	39		T1	25		T13	1
all_values[10]	auto[0]	auto[0]	auto[0]	2639804	1			T24	212		T25	48		T26	78
all_values[10]	auto[0]	auto[0]	auto[1]	4396503	1			T26	610		T1	689		T11	99
all_values[10]	auto[0]	auto[1]	auto[0]	469068	1			T26	122		T1	113		T11	34
all_values[10]	auto[0]	auto[1]	auto[1]	4382713	1			T26	808		T1	484		T11	233
all_values[10]	auto[1]	auto[0]	auto[1]	64414	1			T26	38		T1	35		T16	2
all_values[10]	auto[1]	auto[1]	auto[1]	62970	1			T26	32		T1	14		T16	1
all_values[11]	auto[0]	auto[0]	auto[0]	2642062	1			T24	212		T25	48		T26	110
all_values[11]	auto[0]	auto[0]	auto[1]	4383645	1			T26	774		T1	740		T11	115
all_values[11]	auto[0]	auto[1]	auto[0]	476700	1			T26	124		T1	91		T11	37
all_values[11]	auto[0]	auto[1]	auto[1]	4385319	1			T26	624		T1	483		T11	176
all_values[11]	auto[1]	auto[0]	auto[1]	64042	1			T26	33		T1	31		T16	4
all_values[11]	auto[1]	auto[1]	auto[1]	63704	1			T26	23		T1	20		T16	3
all_values[12]	auto[0]	auto[0]	auto[0]	2639231	1			T24	212		T25	48		T26	124
all_values[12]	auto[0]	auto[0]	auto[1]	4365728	1			T26	766		T1	620		T11	134
all_values[12]	auto[0]	auto[1]	auto[0]	481280	1			T26	91		T1	97		T11	52
all_values[12]	auto[0]	auto[1]	auto[1]	4401731	1			T26	639		T1	647		T11	175
all_values[12]	auto[1]	auto[0]	auto[1]	63938	1			T26	38		T1	20		T16	6
all_values[12]	auto[1]	auto[1]	auto[1]	63564	1			T26	30		T1	28		T27	1346
all_values[13]	auto[0]	auto[0]	auto[0]	2637101	1			T24	212		T25	48		T26	92
all_values[13]	auto[0]	auto[0]	auto[1]	4366026	1			T26	829		T1	511		T11	160
all_values[13]	auto[0]	auto[1]	auto[0]	472890	1			T26	59		T1	85		T11	26
all_values[13]	auto[0]	auto[1]	auto[1]	4411892	1			T26	643		T1	707		T11	180
all_values[13]	auto[1]	auto[0]	auto[1]	63989	1			T26	34		T1	18		T13	1
all_values[13]	auto[1]	auto[1]	auto[1]	63574	1			T26	31		T1	27		T27	1276
all_values[14]	auto[0]	auto[0]	auto[0]	2640763	1			T24	212		T25	48		T26	94
all_values[14]	auto[0]	auto[0]	auto[1]	4378534	1			T26	706		T1	564		T11	161
all_values[14]	auto[0]	auto[1]	auto[0]	477839	1			T26	117		T1	90		T11	40
all_values[14]	auto[0]	auto[1]	auto[1]	4390747	1			T26	711		T1	669		T11	111
all_values[14]	auto[1]	auto[0]	auto[1]	64189	1			T26	34		T1	16		T16	6
all_values[14]	auto[1]	auto[1]	auto[1]	63400	1			T26	26		T1	30		T27	1228
all_values[15]	auto[0]	auto[0]	auto[0]	2644001	1			T24	212		T25	48		T26	149
all_values[15]	auto[0]	auto[0]	auto[1]	4369310	1			T26	610		T1	609		T11	205
all_values[15]	auto[0]	auto[1]	auto[0]	483519	1			T26	135		T1	120		T11	7
all_values[15]	auto[0]	auto[1]	auto[1]	4391090	1			T26	731		T1	556		T11	134
all_values[15]	auto[1]	auto[0]	auto[1]	63944	1			T26	34		T1	30		T13	1
all_values[15]	auto[1]	auto[1]	auto[1]	63608	1			T26	29		T1	24		T16	1
all_values[16]	auto[0]	auto[0]	auto[0]	2650707	1			T24	212		T25	48		T26	170
all_values[16]	auto[0]	auto[0]	auto[1]	4384274	1			T26	766		T1	592		T11	147
all_values[16]	auto[0]	auto[1]	auto[0]	478117	1			T26	162		T1	50		T11	22
all_values[16]	auto[0]	auto[1]	auto[1]	4374957	1			T26	524		T1	700		T11	195
all_values[16]	auto[1]	auto[0]	auto[1]	63865	1			T26	44		T1	27		T16	3
all_values[16]	auto[1]	auto[1]	auto[1]	63552	1			T26	22		T1	20		T16	2
all_values[17]	auto[0]	auto[0]	auto[0]	2641312	1			T24	212		T25	48		T26	81
all_values[17]	auto[0]	auto[0]	auto[1]	4374659	1			T26	673		T1	627		T11	118
all_values[17]	auto[0]	auto[1]	auto[0]	475898	1			T26	90		T1	74		T11	67
all_values[17]	auto[0]	auto[1]	auto[1]	4396099	1			T26	780		T1	637		T11	166
all_values[17]	auto[1]	auto[0]	auto[1]	63712	1			T26	30		T1	23		T16	7
all_values[17]	auto[1]	auto[1]	auto[1]	63792	1			T26	34		T1	29		T27	1341
all_values[18]	auto[0]	auto[0]	auto[0]	2636405	1			T24	212		T25	48		T26	129
all_values[18]	auto[0]	auto[0]	auto[1]	4408422	1			T26	761		T1	563		T11	197
all_values[18]	auto[0]	auto[1]	auto[0]	472971	1			T26	174		T1	109		T11	38
all_values[18]	auto[0]	auto[1]	auto[1]	4370457	1			T26	558		T1	711		T11	93
all_values[18]	auto[1]	auto[0]	auto[1]	63697	1			T26	38		T1	22		T16	4
all_values[18]	auto[1]	auto[1]	auto[1]	63520	1			T26	28		T1	28		T13	1
all_values[19]	auto[0]	auto[0]	auto[0]	2634998	1			T24	212		T25	48		T26	131
all_values[19]	auto[0]	auto[0]	auto[1]	4400687	1			T26	648		T1	754		T11	108
all_values[19]	auto[0]	auto[1]	auto[0]	476321	1			T26	68		T1	72		T11	36
all_values[19]	auto[0]	auto[1]	auto[1]	4376213	1			T26	779		T1	479		T11	216
all_values[19]	auto[1]	auto[0]	auto[1]	64431	1			T26	26		T1	32		T16	5
all_values[19]	auto[1]	auto[1]	auto[1]	62822	1			T26	36		T1	23		T16	1
all_values[20]	auto[0]	auto[0]	auto[0]	2638437	1			T24	212		T25	48		T26	74
all_values[20]	auto[0]	auto[0]	auto[1]	4408882	1			T26	537		T1	731		T11	182
all_values[20]	auto[0]	auto[1]	auto[0]	473546	1			T26	103		T1	108		T11	18
all_values[20]	auto[0]	auto[1]	auto[1]	4366993	1			T26	913		T1	517		T11	135
all_values[20]	auto[1]	auto[0]	auto[1]	63700	1			T26	21		T1	27		T16	4
all_values[20]	auto[1]	auto[1]	auto[1]	63914	1			T26	40		T1	20		T16	2
all_values[21]	auto[0]	auto[0]	auto[0]	2632807	1			T24	212		T25	48		T26	114
all_values[21]	auto[0]	auto[0]	auto[1]	4383439	1			T26	628		T1	614		T11	120
all_values[21]	auto[0]	auto[1]	auto[0]	476051	1			T26	118		T1	151		T11	20
all_values[21]	auto[0]	auto[1]	auto[1]	4395751	1			T26	749		T1	581		T11	185
all_values[21]	auto[1]	auto[0]	auto[1]	63627	1			T26	35		T1	18		T16	5
all_values[21]	auto[1]	auto[1]	auto[1]	63797	1			T26	44		T1	33		T16	2
all_values[22]	auto[0]	auto[0]	auto[0]	2630941	1			T24	212		T25	48		T26	57
all_values[22]	auto[0]	auto[0]	auto[1]	4382253	1			T26	450		T1	520		T11	153
all_values[22]	auto[0]	auto[1]	auto[0]	476333	1			T26	84		T1	90		T11	50
all_values[22]	auto[0]	auto[1]	auto[1]	4398472	1			T26	1037		T1	736		T11	135
all_values[22]	auto[1]	auto[0]	auto[1]	64204	1			T26	20		T1	20		T13	1
all_values[22]	auto[1]	auto[1]	auto[1]	63269	1			T26	40		T1	32		T27	1341
all_values[23]	auto[0]	auto[0]	auto[0]	2634918	1			T24	212		T25	48		T26	129
all_values[23]	auto[0]	auto[0]	auto[1]	4366351	1			T26	647		T1	558		T11	93
all_values[23]	auto[0]	auto[1]	auto[0]	481055	1			T26	156		T1	94		T11	34
all_values[23]	auto[0]	auto[1]	auto[1]	4405675	1			T26	690		T1	708		T11	239
all_values[23]	auto[1]	auto[0]	auto[1]	63980	1			T26	37		T1	20		T13	1
all_values[23]	auto[1]	auto[1]	auto[1]	63493	1			T26	29		T1	31		T16	2
all_values[24]	auto[0]	auto[0]	auto[0]	2639553	1			T24	212		T25	48		T26	44
all_values[24]	auto[0]	auto[0]	auto[1]	4365142	1			T26	641		T1	784		T11	132
all_values[24]	auto[0]	auto[1]	auto[0]	483521	1			T26	75		T1	47		T11	54
all_values[24]	auto[0]	auto[1]	auto[1]	4399523	1			T26	873		T1	530		T11	153
all_values[24]	auto[1]	auto[0]	auto[1]	64028	1			T26	23		T1	29		T16	3
all_values[24]	auto[1]	auto[1]	auto[1]	63705	1			T26	32		T1	23		T16	1
all_values[25]	auto[0]	auto[0]	auto[0]	2639003	1			T24	212		T25	48		T26	63
all_values[25]	auto[0]	auto[0]	auto[1]	4399246	1			T26	732		T1	599		T11	197
all_values[25]	auto[0]	auto[1]	auto[0]	483277	1			T26	117		T1	133		T11	11
all_values[25]	auto[0]	auto[1]	auto[1]	4366153	1			T26	706		T1	579		T11	148
all_values[25]	auto[1]	auto[0]	auto[1]	64196	1			T26	44		T1	31		T16	2
all_values[25]	auto[1]	auto[1]	auto[1]	63597	1			T26	26		T1	32		T16	1
all_values[26]	auto[0]	auto[0]	auto[0]	2642546	1			T24	212		T25	48		T26	126
all_values[26]	auto[0]	auto[0]	auto[1]	4394842	1			T26	695		T1	736		T11	182
all_values[26]	auto[0]	auto[1]	auto[0]	479145	1			T26	131		T1	88		T11	42
all_values[26]	auto[0]	auto[1]	auto[1]	4371053	1			T26	663		T1	504		T11	119
all_values[26]	auto[1]	auto[0]	auto[1]	64224	1			T26	33		T1	27		T13	1
all_values[26]	auto[1]	auto[1]	auto[1]	63662	1			T26	40		T1	23		T27	1306
all_values[27]	auto[0]	auto[0]	auto[0]	2640921	1			T24	212		T25	48		T26	85
all_values[27]	auto[0]	auto[0]	auto[1]	4400132	1			T26	639		T1	624		T11	177
all_values[27]	auto[0]	auto[1]	auto[0]	472794	1			T26	148		T1	72		T11	17
all_values[27]	auto[0]	auto[1]	auto[1]	4373821	1			T26	741		T1	650		T11	170
all_values[27]	auto[1]	auto[0]	auto[1]	64178	1			T26	31		T1	26		T13	1
all_values[27]	auto[1]	auto[1]	auto[1]	63626	1			T26	44		T1	29		T27	1303
all_values[28]	auto[0]	auto[0]	auto[0]	2636969	1			T24	212		T25	48		T26	147
all_values[28]	auto[0]	auto[0]	auto[1]	4382908	1			T26	714		T1	602		T11	173
all_values[28]	auto[0]	auto[1]	auto[0]	474126	1			T26	115		T1	49		T11	12
all_values[28]	auto[0]	auto[1]	auto[1]	4394157	1			T26	651		T1	722		T11	180
all_values[28]	auto[1]	auto[0]	auto[1]	63578	1			T26	33		T1	22		T16	5
all_values[28]	auto[1]	auto[1]	auto[1]	63734	1			T26	28		T1	28		T27	1281
all_values[29]	auto[0]	auto[0]	auto[0]	2642504	1			T24	212		T25	48		T26	73
all_values[29]	auto[0]	auto[0]	auto[1]	4405456	1			T26	545		T1	638		T11	132
all_values[29]	auto[0]	auto[1]	auto[0]	483022	1			T26	167		T1	80		T11	38
all_values[29]	auto[0]	auto[1]	auto[1]	4357267	1			T26	843		T1	658		T11	158
all_values[29]	auto[1]	auto[0]	auto[1]	64358	1			T26	22		T1	20		T13	1
all_values[29]	auto[1]	auto[1]	auto[1]	62865	1			T26	38		T1	24		T27	1252
all_values[30]	auto[0]	auto[0]	auto[0]	2637804	1			T24	212		T25	48		T26	107
all_values[30]	auto[0]	auto[0]	auto[1]	4396411	1			T26	704		T1	535		T11	108
all_values[30]	auto[0]	auto[1]	auto[0]	478371	1			T26	107		T1	117		T11	64
all_values[30]	auto[0]	auto[1]	auto[1]	4375964	1			T26	713		T1	636		T11	139
all_values[30]	auto[1]	auto[0]	auto[1]	63554	1			T26	33		T1	23		T13	1
all_values[30]	auto[1]	auto[1]	auto[1]	63368	1			T26	24		T1	26		T16	2
all_values[31]	auto[0]	auto[0]	auto[0]	2638278	1			T24	212		T25	48		T26	102
all_values[31]	auto[0]	auto[0]	auto[1]	4410965	1			T26	795		T1	545		T11	138
all_values[31]	auto[0]	auto[1]	auto[0]	482762	1			T26	115		T1	89		T11	51
all_values[31]	auto[0]	auto[1]	auto[1]	4355407	1			T26	612		T1	694		T11	135
all_values[31]	auto[1]	auto[0]	auto[1]	64701	1			T26	31		T1	16		T13	1
all_values[31]	auto[1]	auto[1]	auto[1]	63359	1			T26	33		T1	36		T16	1

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal