Unified Coverage Report :: Group :: gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

Group : gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_gpio_env_0.1/gpio_env_cov.sv

---

Summary for Group gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	192	0	192	100.00

Variables for Group gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_pin	32	0	32	100.00	100	1	1	0
data_in	2	0	2	100.00	100	1	1	2
data_oe	2	0	2	100.00	100	1	1	2
data_out	2	0	2	100.00	100	1	1	2

Crosses for Group gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_cross_all	192	0	192	100.00	100	1	1	0

Summary for Variable cp_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	32	0	32	100.00

User Defined Bins for cp_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bins_for_gpio_bits[0]	11811147	1			T24	420		T25	92		T26	1616
bins_for_gpio_bits[1]	11811147	1			T24	420		T25	92		T26	1616
bins_for_gpio_bits[2]	11811147	1			T24	420		T25	92		T26	1616
bins_for_gpio_bits[3]	11811147	1			T24	420		T25	92		T26	1616
bins_for_gpio_bits[4]	11811147	1			T24	420		T25	92		T26	1616
bins_for_gpio_bits[5]	11811147	1			T24	420		T25	92		T26	1616
bins_for_gpio_bits[6]	11811147	1			T24	420		T25	92		T26	1616
bins_for_gpio_bits[7]	11811147	1			T24	420		T25	92		T26	1616
bins_for_gpio_bits[8]	11811147	1			T24	420		T25	92		T26	1616
bins_for_gpio_bits[9]	11811147	1			T24	420		T25	92		T26	1616
bins_for_gpio_bits[10]	11811147	1			T24	420		T25	92		T26	1616
bins_for_gpio_bits[11]	11811147	1			T24	420		T25	92		T26	1616
bins_for_gpio_bits[12]	11811147	1			T24	420		T25	92		T26	1616
bins_for_gpio_bits[13]	11811147	1			T24	420		T25	92		T26	1616
bins_for_gpio_bits[14]	11811147	1			T24	420		T25	92		T26	1616
bins_for_gpio_bits[15]	11811147	1			T24	420		T25	92		T26	1616
bins_for_gpio_bits[16]	11811147	1			T24	420		T25	92		T26	1616
bins_for_gpio_bits[17]	11811147	1			T24	420		T25	92		T26	1616
bins_for_gpio_bits[18]	11811147	1			T24	420		T25	92		T26	1616
bins_for_gpio_bits[19]	11811147	1			T24	420		T25	92		T26	1616
bins_for_gpio_bits[20]	11811147	1			T24	420		T25	92		T26	1616
bins_for_gpio_bits[21]	11811147	1			T24	420		T25	92		T26	1616
bins_for_gpio_bits[22]	11811147	1			T24	420		T25	92		T26	1616
bins_for_gpio_bits[23]	11811147	1			T24	420		T25	92		T26	1616
bins_for_gpio_bits[24]	11811147	1			T24	420		T25	92		T26	1616
bins_for_gpio_bits[25]	11811147	1			T24	420		T25	92		T26	1616
bins_for_gpio_bits[26]	11811147	1			T24	420		T25	92		T26	1616
bins_for_gpio_bits[27]	11811147	1			T24	420		T25	92		T26	1616
bins_for_gpio_bits[28]	11811147	1			T24	420		T25	92		T26	1616
bins_for_gpio_bits[29]	11811147	1			T24	420		T25	92		T26	1616
bins_for_gpio_bits[30]	11811147	1			T24	420		T25	92		T26	1616
bins_for_gpio_bits[31]	11811147	1			T24	420		T25	92		T26	1616

---

Summary for Variable data_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for data_in

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

220514980

1

T24

10634

T25

2359

T26

39716

auto[1]

157441724

1

T24

2806

T25

585

T26

11996

---

Summary for Variable data_oe

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for data_oe

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

305621341

1

T24

9974

T25

2732

T26

29589

auto[1]

72335363

1

T24

3466

T25

212

T26

22123

---

Summary for Variable data_out

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for data_out

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

284597078

1

T24

6918

T25

2026

T26

26249

auto[1]

93359626

1

T24

6522

T25

918

T26

25463

---

Summary for Cross cp_cross_all

Samples crossed: cp_pin data_out data_oe data_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	192	0	192	100.00
Automatically Generated Cross Bins	192	0	192	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cp_cross_all

Bins

cp_pin	data_out	data_oe	data_in	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bins_for_gpio_bits[0]	auto[0]	auto[0]	auto[0]	4379447	1			T24	125		T25	45		T26	420
bins_for_gpio_bits[0]	auto[0]	auto[0]	auto[1]	3381733	1			T24	10		T25	12		T26	15
bins_for_gpio_bits[0]	auto[0]	auto[1]	auto[0]	1137333	1			T24	50		T25	10		T26	391
bins_for_gpio_bits[0]	auto[1]	auto[0]	auto[0]	1371388	1			T24	164		T25	17		T26	392
bins_for_gpio_bits[0]	auto[1]	auto[0]	auto[1]	411795	1			T24	22		T25	8		T26	14
bins_for_gpio_bits[0]	auto[1]	auto[1]	auto[1]	1129451	1			T24	49		T26	384		T1	356
bins_for_gpio_bits[1]	auto[0]	auto[0]	auto[0]	4379800	1			T24	129		T25	48		T26	485
bins_for_gpio_bits[1]	auto[0]	auto[0]	auto[1]	3376452	1			T24	17		T25	18		T26	11
bins_for_gpio_bits[1]	auto[0]	auto[1]	auto[0]	1141028	1			T24	48		T25	3		T26	353
bins_for_gpio_bits[1]	auto[1]	auto[0]	auto[0]	1374277	1			T24	128		T25	13		T26	403
bins_for_gpio_bits[1]	auto[1]	auto[0]	auto[1]	413103	1			T24	16		T25	3		T26	14
bins_for_gpio_bits[1]	auto[1]	auto[1]	auto[1]	1126487	1			T24	82		T25	7		T26	350
bins_for_gpio_bits[2]	auto[0]	auto[0]	auto[0]	4372712	1			T24	174		T25	46		T26	477
bins_for_gpio_bits[2]	auto[0]	auto[0]	auto[1]	3386753	1			T24	22		T25	18		T26	14
bins_for_gpio_bits[2]	auto[0]	auto[1]	auto[0]	1134160	1			T24	61		T25	9		T26	388
bins_for_gpio_bits[2]	auto[1]	auto[0]	auto[0]	1377961	1			T24	118		T25	18		T26	426
bins_for_gpio_bits[2]	auto[1]	auto[0]	auto[1]	414142	1			T24	9		T25	1		T26	21
bins_for_gpio_bits[2]	auto[1]	auto[1]	auto[1]	1125419	1			T24	36		T26	290		T1	404
bins_for_gpio_bits[3]	auto[0]	auto[0]	auto[0]	4366653	1			T24	116		T25	52		T26	399
bins_for_gpio_bits[3]	auto[0]	auto[0]	auto[1]	3389668	1			T24	16		T25	16		T26	18
bins_for_gpio_bits[3]	auto[0]	auto[1]	auto[0]	1141374	1			T24	73		T25	15		T26	330
bins_for_gpio_bits[3]	auto[1]	auto[0]	auto[0]	1380851	1			T24	149		T25	5		T26	442
bins_for_gpio_bits[3]	auto[1]	auto[0]	auto[1]	410310	1			T24	16		T26	18		T1	335
bins_for_gpio_bits[3]	auto[1]	auto[1]	auto[1]	1122291	1			T24	50		T25	4		T26	409
bins_for_gpio_bits[4]	auto[0]	auto[0]	auto[0]	4379810	1			T24	137		T25	56		T26	513
bins_for_gpio_bits[4]	auto[0]	auto[0]	auto[1]	3385394	1			T24	16		T25	7		T26	13
bins_for_gpio_bits[4]	auto[0]	auto[1]	auto[0]	1133074	1			T24	45		T25	1		T26	311
bins_for_gpio_bits[4]	auto[1]	auto[0]	auto[0]	1373672	1			T24	139		T25	23		T26	398
bins_for_gpio_bits[4]	auto[1]	auto[0]	auto[1]	412419	1			T24	17		T25	3		T26	21
bins_for_gpio_bits[4]	auto[1]	auto[1]	auto[1]	1126778	1			T24	66		T25	2		T26	360
bins_for_gpio_bits[5]	auto[0]	auto[0]	auto[0]	4376290	1			T24	149		T25	67		T26	532
bins_for_gpio_bits[5]	auto[0]	auto[0]	auto[1]	3384164	1			T24	28		T25	13		T26	19
bins_for_gpio_bits[5]	auto[0]	auto[1]	auto[0]	1134885	1			T24	66		T25	2		T26	316
bins_for_gpio_bits[5]	auto[1]	auto[0]	auto[0]	1374175	1			T24	119		T25	10		T26	426
bins_for_gpio_bits[5]	auto[1]	auto[0]	auto[1]	413013	1			T24	11		T26	13		T1	349
bins_for_gpio_bits[5]	auto[1]	auto[1]	auto[1]	1128620	1			T24	47		T26	310		T1	316
bins_for_gpio_bits[6]	auto[0]	auto[0]	auto[0]	4367802	1			T24	128		T25	38		T26	447
bins_for_gpio_bits[6]	auto[0]	auto[0]	auto[1]	3388418	1			T24	8		T25	8		T26	11
bins_for_gpio_bits[6]	auto[0]	auto[1]	auto[0]	1140153	1			T24	52		T25	5		T26	380
bins_for_gpio_bits[6]	auto[1]	auto[0]	auto[0]	1369951	1			T24	148		T25	20		T26	467
bins_for_gpio_bits[6]	auto[1]	auto[0]	auto[1]	411526	1			T24	22		T25	11		T26	13
bins_for_gpio_bits[6]	auto[1]	auto[1]	auto[1]	1133297	1			T24	62		T25	10		T26	298
bins_for_gpio_bits[7]	auto[0]	auto[0]	auto[0]	4367296	1			T24	145		T25	52		T26	539
bins_for_gpio_bits[7]	auto[0]	auto[0]	auto[1]	3386960	1			T24	12		T25	9		T26	26
bins_for_gpio_bits[7]	auto[0]	auto[1]	auto[0]	1136196	1			T24	56		T25	2		T26	351
bins_for_gpio_bits[7]	auto[1]	auto[0]	auto[0]	1379644	1			T24	111		T25	21		T26	427
bins_for_gpio_bits[7]	auto[1]	auto[0]	auto[1]	410991	1			T24	22		T25	4		T26	10
bins_for_gpio_bits[7]	auto[1]	auto[1]	auto[1]	1130060	1			T24	74		T25	4		T26	263
bins_for_gpio_bits[8]	auto[0]	auto[0]	auto[0]	4380492	1			T24	172		T25	52		T26	411
bins_for_gpio_bits[8]	auto[0]	auto[0]	auto[1]	3377540	1			T24	15		T25	16		T26	20
bins_for_gpio_bits[8]	auto[0]	auto[1]	auto[0]	1134608	1			T24	50		T25	1		T26	401
bins_for_gpio_bits[8]	auto[1]	auto[0]	auto[0]	1378614	1			T24	140		T25	13		T26	467
bins_for_gpio_bits[8]	auto[1]	auto[0]	auto[1]	410525	1			T24	16		T25	4		T26	18
bins_for_gpio_bits[8]	auto[1]	auto[1]	auto[1]	1129368	1			T24	27		T25	6		T26	299
bins_for_gpio_bits[9]	auto[0]	auto[0]	auto[0]	4372447	1			T24	149		T25	42		T26	341
bins_for_gpio_bits[9]	auto[0]	auto[0]	auto[1]	3380967	1			T24	16		T25	13		T26	9
bins_for_gpio_bits[9]	auto[0]	auto[1]	auto[0]	1133625	1			T24	62		T25	8		T26	208
bins_for_gpio_bits[9]	auto[1]	auto[0]	auto[0]	1383444	1			T24	147		T25	24		T26	603
bins_for_gpio_bits[9]	auto[1]	auto[0]	auto[1]	414009	1			T24	22		T25	5		T26	23
bins_for_gpio_bits[9]	auto[1]	auto[1]	auto[1]	1126655	1			T24	24		T26	432		T1	223
bins_for_gpio_bits[10]	auto[0]	auto[0]	auto[0]	4373708	1			T24	196		T25	30		T26	547
bins_for_gpio_bits[10]	auto[0]	auto[0]	auto[1]	3383639	1			T24	31		T25	8		T26	24
bins_for_gpio_bits[10]	auto[0]	auto[1]	auto[0]	1137206	1			T24	58		T25	2		T26	380
bins_for_gpio_bits[10]	auto[1]	auto[0]	auto[0]	1377156	1			T24	82		T25	33		T26	393
bins_for_gpio_bits[10]	auto[1]	auto[0]	auto[1]	412334	1			T24	9		T25	10		T26	10
bins_for_gpio_bits[10]	auto[1]	auto[1]	auto[1]	1127104	1			T24	44		T25	9		T26	262
bins_for_gpio_bits[11]	auto[0]	auto[0]	auto[0]	4369829	1			T24	143		T25	53		T26	548
bins_for_gpio_bits[11]	auto[0]	auto[0]	auto[1]	3384016	1			T24	26		T25	11		T26	23
bins_for_gpio_bits[11]	auto[0]	auto[1]	auto[0]	1137699	1			T24	62		T25	4		T26	364
bins_for_gpio_bits[11]	auto[1]	auto[0]	auto[0]	1377193	1			T24	125		T25	14		T26	373
bins_for_gpio_bits[11]	auto[1]	auto[0]	auto[1]	412546	1			T24	13		T25	4		T26	12
bins_for_gpio_bits[11]	auto[1]	auto[1]	auto[1]	1129864	1			T24	51		T25	6		T26	296
bins_for_gpio_bits[12]	auto[0]	auto[0]	auto[0]	4379647	1			T24	101		T25	48		T26	420
bins_for_gpio_bits[12]	auto[0]	auto[0]	auto[1]	3374674	1			T24	9		T25	15		T26	12
bins_for_gpio_bits[12]	auto[0]	auto[1]	auto[0]	1135005	1			T24	37		T25	15		T26	419
bins_for_gpio_bits[12]	auto[1]	auto[0]	auto[0]	1378118	1			T24	183		T25	10		T26	419
bins_for_gpio_bits[12]	auto[1]	auto[0]	auto[1]	414015	1			T24	20		T25	2		T26	9
bins_for_gpio_bits[12]	auto[1]	auto[1]	auto[1]	1129688	1			T24	70		T25	2		T26	337
bins_for_gpio_bits[13]	auto[0]	auto[0]	auto[0]	4385412	1			T24	100		T25	32		T26	507
bins_for_gpio_bits[13]	auto[0]	auto[0]	auto[1]	3377837	1			T24	22		T25	12		T26	23
bins_for_gpio_bits[13]	auto[0]	auto[1]	auto[0]	1135644	1			T24	56		T26	448		T1	294
bins_for_gpio_bits[13]	auto[1]	auto[0]	auto[0]	1376904	1			T24	171		T25	40		T26	339
bins_for_gpio_bits[13]	auto[1]	auto[0]	auto[1]	412001	1			T24	15		T25	4		T26	17
bins_for_gpio_bits[13]	auto[1]	auto[1]	auto[1]	1123349	1			T24	56		T25	4		T26	282
bins_for_gpio_bits[14]	auto[0]	auto[0]	auto[0]	4373518	1			T24	172		T25	47		T26	536
bins_for_gpio_bits[14]	auto[0]	auto[0]	auto[1]	3383924	1			T24	17		T25	20		T26	8
bins_for_gpio_bits[14]	auto[0]	auto[1]	auto[0]	1135358	1			T24	44		T25	10		T26	206
bins_for_gpio_bits[14]	auto[1]	auto[0]	auto[0]	1377349	1			T24	113		T25	11		T26	520
bins_for_gpio_bits[14]	auto[1]	auto[0]	auto[1]	412297	1			T24	25		T25	2		T26	30
bins_for_gpio_bits[14]	auto[1]	auto[1]	auto[1]	1128701	1			T24	49		T25	2		T26	316
bins_for_gpio_bits[15]	auto[0]	auto[0]	auto[0]	4371116	1			T24	145		T25	37		T26	413
bins_for_gpio_bits[15]	auto[0]	auto[0]	auto[1]	3378536	1			T24	9		T25	7		T26	11
bins_for_gpio_bits[15]	auto[0]	auto[1]	auto[0]	1138393	1			T24	63		T25	5		T26	346
bins_for_gpio_bits[15]	auto[1]	auto[0]	auto[0]	1376978	1			T24	133		T25	38		T26	469
bins_for_gpio_bits[15]	auto[1]	auto[0]	auto[1]	415457	1			T24	17		T25	5		T26	22
bins_for_gpio_bits[15]	auto[1]	auto[1]	auto[1]	1130667	1			T24	53		T26	355		T1	261
bins_for_gpio_bits[16]	auto[0]	auto[0]	auto[0]	4378785	1			T24	170		T25	77		T26	473
bins_for_gpio_bits[16]	auto[0]	auto[0]	auto[1]	3387691	1			T24	15		T25	12		T26	11
bins_for_gpio_bits[16]	auto[0]	auto[1]	auto[0]	1132414	1			T24	43		T25	3		T26	357
bins_for_gpio_bits[16]	auto[1]	auto[0]	auto[0]	1378197	1			T24	127		T26	402		T1	15
bins_for_gpio_bits[16]	auto[1]	auto[0]	auto[1]	411000	1			T24	12		T26	29		T1	382
bins_for_gpio_bits[16]	auto[1]	auto[1]	auto[1]	1123060	1			T24	53		T26	344		T1	373
bins_for_gpio_bits[17]	auto[0]	auto[0]	auto[0]	4385421	1			T24	165		T25	56		T26	426
bins_for_gpio_bits[17]	auto[0]	auto[0]	auto[1]	3374231	1			T24	12		T25	11		T26	23
bins_for_gpio_bits[17]	auto[0]	auto[1]	auto[0]	1134559	1			T24	47		T25	1		T26	409
bins_for_gpio_bits[17]	auto[1]	auto[0]	auto[0]	1381927	1			T24	130		T25	17		T26	352
bins_for_gpio_bits[17]	auto[1]	auto[0]	auto[1]	411928	1			T24	21		T25	6		T26	20
bins_for_gpio_bits[17]	auto[1]	auto[1]	auto[1]	1123081	1			T24	45		T25	1		T26	386
bins_for_gpio_bits[18]	auto[0]	auto[0]	auto[0]	4377833	1			T24	137		T25	38		T26	441
bins_for_gpio_bits[18]	auto[0]	auto[0]	auto[1]	3381154	1			T24	21		T25	15		T26	9
bins_for_gpio_bits[18]	auto[0]	auto[1]	auto[0]	1134554	1			T24	89		T25	5		T26	311
bins_for_gpio_bits[18]	auto[1]	auto[0]	auto[0]	1379748	1			T24	110		T25	30		T26	477
bins_for_gpio_bits[18]	auto[1]	auto[0]	auto[1]	413077	1			T24	15		T25	2		T26	24
bins_for_gpio_bits[18]	auto[1]	auto[1]	auto[1]	1124781	1			T24	48		T25	2		T26	354
bins_for_gpio_bits[19]	auto[0]	auto[0]	auto[0]	4394731	1			T24	117		T25	33		T26	342
bins_for_gpio_bits[19]	auto[0]	auto[0]	auto[1]	3372568	1			T24	14		T25	7		T26	17
bins_for_gpio_bits[19]	auto[0]	auto[1]	auto[0]	1131536	1			T24	48		T26	359		T1	313
bins_for_gpio_bits[19]	auto[1]	auto[0]	auto[0]	1379851	1			T24	140		T25	43		T26	358
bins_for_gpio_bits[19]	auto[1]	auto[0]	auto[1]	411460	1			T24	29		T25	9		T26	21
bins_for_gpio_bits[19]	auto[1]	auto[1]	auto[1]	1121001	1			T24	72		T26	519		T1	285
bins_for_gpio_bits[20]	auto[0]	auto[0]	auto[0]	4375622	1			T24	154		T25	49		T26	412
bins_for_gpio_bits[20]	auto[0]	auto[0]	auto[1]	3381308	1			T24	31		T25	8		T26	17
bins_for_gpio_bits[20]	auto[0]	auto[1]	auto[0]	1134600	1			T24	65		T25	5		T26	315
bins_for_gpio_bits[20]	auto[1]	auto[0]	auto[0]	1384255	1			T24	122		T25	22		T26	534
bins_for_gpio_bits[20]	auto[1]	auto[0]	auto[1]	413356	1			T24	12		T25	6		T26	17
bins_for_gpio_bits[20]	auto[1]	auto[1]	auto[1]	1122006	1			T24	36		T25	2		T26	321
bins_for_gpio_bits[21]	auto[0]	auto[0]	auto[0]	4376449	1			T24	150		T25	46		T26	502
bins_for_gpio_bits[21]	auto[0]	auto[0]	auto[1]	3375852	1			T24	26		T25	8		T26	15
bins_for_gpio_bits[21]	auto[0]	auto[1]	auto[0]	1133821	1			T24	60		T26	365		T1	309
bins_for_gpio_bits[21]	auto[1]	auto[0]	auto[0]	1381060	1			T24	101		T25	35		T26	489
bins_for_gpio_bits[21]	auto[1]	auto[0]	auto[1]	414796	1			T24	13		T25	3		T26	13
bins_for_gpio_bits[21]	auto[1]	auto[1]	auto[1]	1129169	1			T24	70		T26	232		T1	342
bins_for_gpio_bits[22]	auto[0]	auto[0]	auto[0]	4367953	1			T24	166		T25	47		T26	382
bins_for_gpio_bits[22]	auto[0]	auto[0]	auto[1]	3386168	1			T24	13		T25	10		T26	11
bins_for_gpio_bits[22]	auto[0]	auto[1]	auto[0]	1135619	1			T24	62		T25	2		T26	329
bins_for_gpio_bits[22]	auto[1]	auto[0]	auto[0]	1383919	1			T24	121		T25	29		T26	470
bins_for_gpio_bits[22]	auto[1]	auto[0]	auto[1]	414320	1			T24	20		T25	4		T26	21
bins_for_gpio_bits[22]	auto[1]	auto[1]	auto[1]	1123168	1			T24	38		T26	403		T1	318
bins_for_gpio_bits[23]	auto[0]	auto[0]	auto[0]	4388655	1			T24	156		T25	66		T26	507
bins_for_gpio_bits[23]	auto[0]	auto[0]	auto[1]	3374442	1			T24	21		T25	14		T26	16
bins_for_gpio_bits[23]	auto[0]	auto[1]	auto[0]	1132982	1			T24	24		T25	3		T26	345
bins_for_gpio_bits[23]	auto[1]	auto[0]	auto[0]	1380464	1			T24	145		T25	6		T26	415
bins_for_gpio_bits[23]	auto[1]	auto[0]	auto[1]	411991	1			T24	14		T25	1		T26	7
bins_for_gpio_bits[23]	auto[1]	auto[1]	auto[1]	1122613	1			T24	60		T25	2		T26	326
bins_for_gpio_bits[24]	auto[0]	auto[0]	auto[0]	4382343	1			T24	138		T25	53		T26	449
bins_for_gpio_bits[24]	auto[0]	auto[0]	auto[1]	3378380	1			T24	18		T25	18		T26	15
bins_for_gpio_bits[24]	auto[0]	auto[1]	auto[0]	1135206	1			T24	52		T25	3		T26	291
bins_for_gpio_bits[24]	auto[1]	auto[0]	auto[0]	1381124	1			T24	151		T25	18		T26	462
bins_for_gpio_bits[24]	auto[1]	auto[0]	auto[1]	413671	1			T24	17		T26	17		T1	397
bins_for_gpio_bits[24]	auto[1]	auto[1]	auto[1]	1120423	1			T24	44		T26	382		T1	330
bins_for_gpio_bits[25]	auto[0]	auto[0]	auto[0]	4385141	1			T24	114		T25	48		T26	379
bins_for_gpio_bits[25]	auto[0]	auto[0]	auto[1]	3381439	1			T24	28		T25	9		T26	15
bins_for_gpio_bits[25]	auto[0]	auto[1]	auto[0]	1134015	1			T24	57		T25	10		T26	309
bins_for_gpio_bits[25]	auto[1]	auto[0]	auto[0]	1380668	1			T24	146		T25	19		T26	406
bins_for_gpio_bits[25]	auto[1]	auto[0]	auto[1]	414325	1			T24	15		T25	6		T26	20
bins_for_gpio_bits[25]	auto[1]	auto[1]	auto[1]	1115559	1			T24	60		T26	487		T1	266
bins_for_gpio_bits[26]	auto[0]	auto[0]	auto[0]	4375113	1			T24	112		T25	60		T26	394
bins_for_gpio_bits[26]	auto[0]	auto[0]	auto[1]	3381208	1			T24	7		T25	15		T26	12
bins_for_gpio_bits[26]	auto[0]	auto[1]	auto[0]	1133656	1			T24	28		T25	8		T26	410
bins_for_gpio_bits[26]	auto[1]	auto[0]	auto[0]	1380997	1			T24	178		T25	7		T26	444
bins_for_gpio_bits[26]	auto[1]	auto[0]	auto[1]	412934	1			T24	23		T26	13		T1	336
bins_for_gpio_bits[26]	auto[1]	auto[1]	auto[1]	1127239	1			T24	72		T25	2		T26	343
bins_for_gpio_bits[27]	auto[0]	auto[0]	auto[0]	4372113	1			T24	99		T25	31		T26	470
bins_for_gpio_bits[27]	auto[0]	auto[0]	auto[1]	3382178	1			T24	10		T25	7		T26	23
bins_for_gpio_bits[27]	auto[0]	auto[1]	auto[0]	1134987	1			T24	59		T25	6		T26	344
bins_for_gpio_bits[27]	auto[1]	auto[0]	auto[0]	1382924	1			T24	163		T25	37		T26	396
bins_for_gpio_bits[27]	auto[1]	auto[0]	auto[1]	412281	1			T24	36		T25	11		T26	11
bins_for_gpio_bits[27]	auto[1]	auto[1]	auto[1]	1126664	1			T24	53		T26	372		T1	318
bins_for_gpio_bits[28]	auto[0]	auto[0]	auto[0]	4382220	1			T24	156		T25	26		T26	478
bins_for_gpio_bits[28]	auto[0]	auto[0]	auto[1]	3380792	1			T24	17		T25	9		T26	8
bins_for_gpio_bits[28]	auto[0]	auto[1]	auto[0]	1130791	1			T24	86		T26	292		T1	269
bins_for_gpio_bits[28]	auto[1]	auto[0]	auto[0]	1381826	1			T24	98		T25	47		T26	474
bins_for_gpio_bits[28]	auto[1]	auto[0]	auto[1]	412409	1			T24	15		T25	10		T26	28
bins_for_gpio_bits[28]	auto[1]	auto[1]	auto[1]	1123109	1			T24	48		T26	336		T1	328
bins_for_gpio_bits[29]	auto[0]	auto[0]	auto[0]	4379632	1			T24	177		T25	31		T26	460
bins_for_gpio_bits[29]	auto[0]	auto[0]	auto[1]	3378248	1			T24	28		T25	7		T26	15
bins_for_gpio_bits[29]	auto[0]	auto[1]	auto[0]	1134688	1			T24	43		T25	2		T26	426
bins_for_gpio_bits[29]	auto[1]	auto[0]	auto[0]	1379720	1			T24	124		T25	42		T26	405
bins_for_gpio_bits[29]	auto[1]	auto[0]	auto[1]	414120	1			T24	13		T25	8		T26	14
bins_for_gpio_bits[29]	auto[1]	auto[1]	auto[1]	1124739	1			T24	35		T25	2		T26	296
bins_for_gpio_bits[30]	auto[0]	auto[0]	auto[0]	4378472	1			T24	114		T25	37		T26	432
bins_for_gpio_bits[30]	auto[0]	auto[0]	auto[1]	3386062	1			T24	23		T25	11		T26	10
bins_for_gpio_bits[30]	auto[0]	auto[1]	auto[0]	1126233	1			T24	89		T25	2		T26	283
bins_for_gpio_bits[30]	auto[1]	auto[0]	auto[0]	1382657	1			T24	121		T25	36		T26	549
bins_for_gpio_bits[30]	auto[1]	auto[0]	auto[1]	414123	1			T24	12		T25	6		T26	17
bins_for_gpio_bits[30]	auto[1]	auto[1]	auto[1]	1123600	1			T24	61		T26	325		T1	315
bins_for_gpio_bits[31]	auto[0]	auto[0]	auto[0]	4373601	1			T24	136		T25	59		T26	505
bins_for_gpio_bits[31]	auto[0]	auto[0]	auto[1]	3389596	1			T24	21		T25	15		T26	18
bins_for_gpio_bits[31]	auto[0]	auto[1]	auto[0]	1129621	1			T24	62		T25	3		T26	433
bins_for_gpio_bits[31]	auto[1]	auto[0]	auto[0]	1382882	1			T24	148		T25	14		T26	362
bins_for_gpio_bits[31]	auto[1]	auto[0]	auto[1]	413118	1			T24	19		T25	1		T26	14
bins_for_gpio_bits[31]	auto[1]	auto[1]	auto[1]	1122329	1			T24	34		T26	284		T1	280

User Defined Cross Bins for cp_cross_all

Excluded/Illegal bins

NAME	COUNT	STATUS
data_oe_1_data_out_0_data_in_1	0	Illegal
data_oe_1_data_out_1_data_in_0	0	Illegal