Unified Coverage Report :: Group :: gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

Group : gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_gpio_env_0.1/gpio_env_cov.sv

---

Summary for Group gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	36	0	36	100.00
Crosses	128	0	128	100.00

Variables for Group gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_pin	32	0	32	100.00	100	1	1	0
data_in	2	0	2	100.00	100	1	1	2
gpio_value	2	0	2	100.00	100	1	1	2

Crosses for Group gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_cross_pins_data_in	128	0	128	100.00	100	1	1	0

Summary for Variable cp_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	32	0	32	100.00

User Defined Bins for cp_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bins_for_gpio_bits[0]	11811147	1			T24	420		T25	92		T26	1616
bins_for_gpio_bits[1]	11811147	1			T24	420		T25	92		T26	1616
bins_for_gpio_bits[2]	11811147	1			T24	420		T25	92		T26	1616
bins_for_gpio_bits[3]	11811147	1			T24	420		T25	92		T26	1616
bins_for_gpio_bits[4]	11811147	1			T24	420		T25	92		T26	1616
bins_for_gpio_bits[5]	11811147	1			T24	420		T25	92		T26	1616
bins_for_gpio_bits[6]	11811147	1			T24	420		T25	92		T26	1616
bins_for_gpio_bits[7]	11811147	1			T24	420		T25	92		T26	1616
bins_for_gpio_bits[8]	11811147	1			T24	420		T25	92		T26	1616
bins_for_gpio_bits[9]	11811147	1			T24	420		T25	92		T26	1616
bins_for_gpio_bits[10]	11811147	1			T24	420		T25	92		T26	1616
bins_for_gpio_bits[11]	11811147	1			T24	420		T25	92		T26	1616
bins_for_gpio_bits[12]	11811147	1			T24	420		T25	92		T26	1616
bins_for_gpio_bits[13]	11811147	1			T24	420		T25	92		T26	1616
bins_for_gpio_bits[14]	11811147	1			T24	420		T25	92		T26	1616
bins_for_gpio_bits[15]	11811147	1			T24	420		T25	92		T26	1616
bins_for_gpio_bits[16]	11811147	1			T24	420		T25	92		T26	1616
bins_for_gpio_bits[17]	11811147	1			T24	420		T25	92		T26	1616
bins_for_gpio_bits[18]	11811147	1			T24	420		T25	92		T26	1616
bins_for_gpio_bits[19]	11811147	1			T24	420		T25	92		T26	1616
bins_for_gpio_bits[20]	11811147	1			T24	420		T25	92		T26	1616
bins_for_gpio_bits[21]	11811147	1			T24	420		T25	92		T26	1616
bins_for_gpio_bits[22]	11811147	1			T24	420		T25	92		T26	1616
bins_for_gpio_bits[23]	11811147	1			T24	420		T25	92		T26	1616
bins_for_gpio_bits[24]	11811147	1			T24	420		T25	92		T26	1616
bins_for_gpio_bits[25]	11811147	1			T24	420		T25	92		T26	1616
bins_for_gpio_bits[26]	11811147	1			T24	420		T25	92		T26	1616
bins_for_gpio_bits[27]	11811147	1			T24	420		T25	92		T26	1616
bins_for_gpio_bits[28]	11811147	1			T24	420		T25	92		T26	1616
bins_for_gpio_bits[29]	11811147	1			T24	420		T25	92		T26	1616
bins_for_gpio_bits[30]	11811147	1			T24	420		T25	92		T26	1616
bins_for_gpio_bits[31]	11811147	1			T24	420		T25	92		T26	1616

---

Summary for Variable data_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for data_in

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

220514980

1

T24

10634

T25

2359

T26

39716

auto[1]

157441724

1

T24

2806

T25

585

T26

11996

---

Summary for Variable gpio_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for gpio_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

220507904

1

T24

10634

T25

2358

T26

39716

auto[1]

157448800

1

T24

2806

T25

586

T26

11996

---

Summary for Cross cp_cross_pins_data_in

Samples crossed: cp_pin gpio_value data_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cp_cross_pins_data_in

Bins

cp_pin	gpio_value	data_in	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bins_for_gpio_bits[0]	auto[0]	auto[0]	6685355	1			T24	328		T25	72		T26	1146
bins_for_gpio_bits[0]	auto[0]	auto[1]	202564	1			T24	11		T26	57		T1	47
bins_for_gpio_bits[0]	auto[1]	auto[0]	202813	1			T24	11		T26	57		T1	47
bins_for_gpio_bits[0]	auto[1]	auto[1]	4720415	1			T24	70		T25	20		T26	356
bins_for_gpio_bits[1]	auto[0]	auto[0]	6692050	1			T24	293		T25	62		T26	1190
bins_for_gpio_bits[1]	auto[0]	auto[1]	202796	1			T24	12		T25	2		T26	51
bins_for_gpio_bits[1]	auto[1]	auto[0]	203055	1			T24	12		T25	2		T26	51
bins_for_gpio_bits[1]	auto[1]	auto[1]	4713246	1			T24	103		T25	26		T26	324
bins_for_gpio_bits[2]	auto[0]	auto[0]	6682901	1			T24	345		T25	73		T26	1245
bins_for_gpio_bits[2]	auto[0]	auto[1]	201730	1			T24	8		T26	46		T1	50
bins_for_gpio_bits[2]	auto[1]	auto[0]	201932	1			T24	8		T26	46		T1	50
bins_for_gpio_bits[2]	auto[1]	auto[1]	4724584	1			T24	59		T25	19		T26	279
bins_for_gpio_bits[3]	auto[0]	auto[0]	6685429	1			T24	328		T25	70		T26	1114
bins_for_gpio_bits[3]	auto[0]	auto[1]	203250	1			T24	10		T25	2		T26	57
bins_for_gpio_bits[3]	auto[1]	auto[0]	203449	1			T24	10		T25	2		T26	57
bins_for_gpio_bits[3]	auto[1]	auto[1]	4719019	1			T24	72		T25	18		T26	388
bins_for_gpio_bits[4]	auto[0]	auto[0]	6684460	1			T24	310		T25	79		T26	1168
bins_for_gpio_bits[4]	auto[0]	auto[1]	201876	1			T24	11		T25	1		T26	54
bins_for_gpio_bits[4]	auto[1]	auto[0]	202096	1			T24	11		T25	1		T26	54
bins_for_gpio_bits[4]	auto[1]	auto[1]	4722715	1			T24	88		T25	11		T26	340
bins_for_gpio_bits[5]	auto[0]	auto[0]	6682888	1			T24	325		T25	79		T26	1227
bins_for_gpio_bits[5]	auto[0]	auto[1]	202271	1			T24	9		T26	47		T1	41
bins_for_gpio_bits[5]	auto[1]	auto[0]	202462	1			T24	9		T26	47		T1	41
bins_for_gpio_bits[5]	auto[1]	auto[1]	4723526	1			T24	77		T25	13		T26	295
bins_for_gpio_bits[6]	auto[0]	auto[0]	6674548	1			T24	319		T25	61		T26	1244
bins_for_gpio_bits[6]	auto[0]	auto[1]	203134	1			T24	9		T25	2		T26	50
bins_for_gpio_bits[6]	auto[1]	auto[0]	203358	1			T24	9		T25	2		T26	50
bins_for_gpio_bits[6]	auto[1]	auto[1]	4730107	1			T24	83		T25	27		T26	272
bins_for_gpio_bits[7]	auto[0]	auto[0]	6680262	1			T24	300		T25	74		T26	1275
bins_for_gpio_bits[7]	auto[0]	auto[1]	202645	1			T24	12		T25	1		T26	42
bins_for_gpio_bits[7]	auto[1]	auto[0]	202874	1			T24	12		T25	1		T26	42
bins_for_gpio_bits[7]	auto[1]	auto[1]	4725366	1			T24	96		T25	16		T26	257
bins_for_gpio_bits[8]	auto[0]	auto[0]	6691052	1			T24	356		T25	65		T26	1239
bins_for_gpio_bits[8]	auto[0]	auto[1]	202425	1			T24	6		T25	1		T26	40
bins_for_gpio_bits[8]	auto[1]	auto[0]	202662	1			T24	6		T25	1		T26	40
bins_for_gpio_bits[8]	auto[1]	auto[1]	4715008	1			T24	52		T25	25		T26	297
bins_for_gpio_bits[9]	auto[0]	auto[0]	6686562	1			T24	352		T25	74		T26	1099
bins_for_gpio_bits[9]	auto[0]	auto[1]	202745	1			T24	6		T26	53		T1	39
bins_for_gpio_bits[9]	auto[1]	auto[0]	202954	1			T24	6		T26	53		T1	39
bins_for_gpio_bits[9]	auto[1]	auto[1]	4718886	1			T24	56		T25	18		T26	411
bins_for_gpio_bits[10]	auto[0]	auto[0]	6685248	1			T24	327		T25	63		T26	1274
bins_for_gpio_bits[10]	auto[0]	auto[1]	202603	1			T24	9		T25	2		T26	46
bins_for_gpio_bits[10]	auto[1]	auto[0]	202822	1			T24	9		T25	2		T26	46
bins_for_gpio_bits[10]	auto[1]	auto[1]	4720474	1			T24	75		T25	25		T26	250
bins_for_gpio_bits[11]	auto[0]	auto[0]	6681469	1			T24	321		T25	70		T26	1246
bins_for_gpio_bits[11]	auto[0]	auto[1]	203081	1			T24	9		T25	1		T26	39
bins_for_gpio_bits[11]	auto[1]	auto[0]	203252	1			T24	9		T25	1		T26	39
bins_for_gpio_bits[11]	auto[1]	auto[1]	4723345	1			T24	81		T25	20		T26	292
bins_for_gpio_bits[12]	auto[0]	auto[0]	6689963	1			T24	311		T25	72		T26	1202
bins_for_gpio_bits[12]	auto[0]	auto[1]	202579	1			T24	10		T25	1		T26	56
bins_for_gpio_bits[12]	auto[1]	auto[0]	202807	1			T24	10		T25	1		T26	56
bins_for_gpio_bits[12]	auto[1]	auto[1]	4715798	1			T24	89		T25	18		T26	302
bins_for_gpio_bits[13]	auto[0]	auto[0]	6695013	1			T24	318		T25	70		T26	1247
bins_for_gpio_bits[13]	auto[0]	auto[1]	202721	1			T24	9		T25	2		T26	47
bins_for_gpio_bits[13]	auto[1]	auto[0]	202947	1			T24	9		T25	2		T26	47
bins_for_gpio_bits[13]	auto[1]	auto[1]	4710466	1			T24	84		T25	18		T26	275
bins_for_gpio_bits[14]	auto[0]	auto[0]	6683106	1			T24	321		T25	67		T26	1219
bins_for_gpio_bits[14]	auto[0]	auto[1]	202885	1			T24	8		T25	1		T26	43
bins_for_gpio_bits[14]	auto[1]	auto[0]	203119	1			T24	8		T25	1		T26	43
bins_for_gpio_bits[14]	auto[1]	auto[1]	4722037	1			T24	83		T25	23		T26	311
bins_for_gpio_bits[15]	auto[0]	auto[0]	6683968	1			T24	331		T25	80		T26	1179
bins_for_gpio_bits[15]	auto[0]	auto[1]	202312	1			T24	10		T26	49		T1	51
bins_for_gpio_bits[15]	auto[1]	auto[0]	202519	1			T24	10		T26	49		T1	51
bins_for_gpio_bits[15]	auto[1]	auto[1]	4722348	1			T24	69		T25	12		T26	339
bins_for_gpio_bits[16]	auto[0]	auto[0]	6686550	1			T24	331		T25	80		T26	1179
bins_for_gpio_bits[16]	auto[0]	auto[1]	202647	1			T24	9		T26	53		T1	45
bins_for_gpio_bits[16]	auto[1]	auto[0]	202846	1			T24	9		T26	53		T1	45
bins_for_gpio_bits[16]	auto[1]	auto[1]	4719104	1			T24	71		T25	12		T26	331
bins_for_gpio_bits[17]	auto[0]	auto[0]	6699286	1			T24	334		T25	73		T26	1126
bins_for_gpio_bits[17]	auto[0]	auto[1]	202425	1			T24	8		T26	61		T1	41
bins_for_gpio_bits[17]	auto[1]	auto[0]	202621	1			T24	8		T25	1		T26	61
bins_for_gpio_bits[17]	auto[1]	auto[1]	4706815	1			T24	70		T25	18		T26	368
bins_for_gpio_bits[18]	auto[0]	auto[0]	6689196	1			T24	325		T25	72		T26	1180
bins_for_gpio_bits[18]	auto[0]	auto[1]	202695	1			T24	11		T25	1		T26	49
bins_for_gpio_bits[18]	auto[1]	auto[0]	202939	1			T24	11		T25	1		T26	49
bins_for_gpio_bits[18]	auto[1]	auto[1]	4716317	1			T24	73		T25	18		T26	338
bins_for_gpio_bits[19]	auto[0]	auto[0]	6703036	1			T24	293		T25	76		T26	991
bins_for_gpio_bits[19]	auto[0]	auto[1]	202856	1			T24	12		T26	68		T1	44
bins_for_gpio_bits[19]	auto[1]	auto[0]	203082	1			T24	12		T26	68		T1	44
bins_for_gpio_bits[19]	auto[1]	auto[1]	4702173	1			T24	103		T25	16		T26	489
bins_for_gpio_bits[20]	auto[0]	auto[0]	6691268	1			T24	336		T25	75		T26	1206
bins_for_gpio_bits[20]	auto[0]	auto[1]	202989	1			T24	5		T25	1		T26	55
bins_for_gpio_bits[20]	auto[1]	auto[0]	203209	1			T24	5		T25	1		T26	55
bins_for_gpio_bits[20]	auto[1]	auto[1]	4713681	1			T24	74		T25	15		T26	300
bins_for_gpio_bits[21]	auto[0]	auto[0]	6688034	1			T24	301		T25	81		T26	1316
bins_for_gpio_bits[21]	auto[0]	auto[1]	203053	1			T24	10		T26	40		T1	41
bins_for_gpio_bits[21]	auto[1]	auto[0]	203296	1			T24	10		T26	40		T1	41
bins_for_gpio_bits[21]	auto[1]	auto[1]	4716764	1			T24	99		T25	11		T26	220
bins_for_gpio_bits[22]	auto[0]	auto[0]	6684427	1			T24	341		T25	78		T26	1116
bins_for_gpio_bits[22]	auto[0]	auto[1]	202801	1			T24	8		T26	65		T1	40
bins_for_gpio_bits[22]	auto[1]	auto[0]	203064	1			T24	8		T26	65		T1	40
bins_for_gpio_bits[22]	auto[1]	auto[1]	4720855	1			T24	63		T25	14		T26	370
bins_for_gpio_bits[23]	auto[0]	auto[0]	6698883	1			T24	315		T25	74		T26	1224
bins_for_gpio_bits[23]	auto[0]	auto[1]	202975	1			T24	10		T25	1		T26	43
bins_for_gpio_bits[23]	auto[1]	auto[0]	203218	1			T24	10		T25	1		T26	43
bins_for_gpio_bits[23]	auto[1]	auto[1]	4706071	1			T24	85		T25	16		T26	306
bins_for_gpio_bits[24]	auto[0]	auto[0]	6695529	1			T24	332		T25	74		T26	1152
bins_for_gpio_bits[24]	auto[0]	auto[1]	202921	1			T24	9		T26	50		T1	39
bins_for_gpio_bits[24]	auto[1]	auto[0]	203144	1			T24	9		T26	50		T1	39
bins_for_gpio_bits[24]	auto[1]	auto[1]	4709553	1			T24	70		T25	18		T26	364
bins_for_gpio_bits[25]	auto[0]	auto[0]	6697632	1			T24	308		T25	77		T26	1038
bins_for_gpio_bits[25]	auto[0]	auto[1]	201973	1			T24	9		T26	56		T1	51
bins_for_gpio_bits[25]	auto[1]	auto[0]	202192	1			T24	9		T26	56		T1	51
bins_for_gpio_bits[25]	auto[1]	auto[1]	4709350	1			T24	94		T25	15		T26	466
bins_for_gpio_bits[26]	auto[0]	auto[0]	6685904	1			T24	307		T25	74		T26	1194
bins_for_gpio_bits[26]	auto[0]	auto[1]	203615	1			T24	11		T25	1		T26	54
bins_for_gpio_bits[26]	auto[1]	auto[0]	203862	1			T24	11		T25	1		T26	54
bins_for_gpio_bits[26]	auto[1]	auto[1]	4717766	1			T24	91		T25	16		T26	314
bins_for_gpio_bits[27]	auto[0]	auto[0]	6686739	1			T24	311		T25	74		T26	1157
bins_for_gpio_bits[27]	auto[0]	auto[1]	203074	1			T24	10		T26	53		T1	40
bins_for_gpio_bits[27]	auto[1]	auto[0]	203285	1			T24	10		T26	53		T1	40
bins_for_gpio_bits[27]	auto[1]	auto[1]	4718049	1			T24	89		T25	18		T26	353
bins_for_gpio_bits[28]	auto[0]	auto[0]	6692134	1			T24	332		T25	73		T26	1196
bins_for_gpio_bits[28]	auto[0]	auto[1]	202478	1			T24	8		T26	48		T1	43
bins_for_gpio_bits[28]	auto[1]	auto[0]	202703	1			T24	8		T26	48		T1	43
bins_for_gpio_bits[28]	auto[1]	auto[1]	4713832	1			T24	72		T25	19		T26	324
bins_for_gpio_bits[29]	auto[0]	auto[0]	6690637	1			T24	337		T25	74		T26	1248
bins_for_gpio_bits[29]	auto[0]	auto[1]	203210	1			T24	7		T25	1		T26	43
bins_for_gpio_bits[29]	auto[1]	auto[0]	203403	1			T24	7		T25	1		T26	43
bins_for_gpio_bits[29]	auto[1]	auto[1]	4713897	1			T24	69		T25	16		T26	282
bins_for_gpio_bits[30]	auto[0]	auto[0]	6684796	1			T24	317		T25	75		T26	1211
bins_for_gpio_bits[30]	auto[0]	auto[1]	202335	1			T24	7		T26	53		T1	36
bins_for_gpio_bits[30]	auto[1]	auto[0]	202566	1			T24	7		T26	53		T1	36
bins_for_gpio_bits[30]	auto[1]	auto[1]	4721450	1			T24	89		T25	17		T26	299
bins_for_gpio_bits[31]	auto[0]	auto[0]	6683501	1			T24	338		T25	76		T26	1257
bins_for_gpio_bits[31]	auto[0]	auto[1]	202414	1			T24	8		T26	43		T1	44
bins_for_gpio_bits[31]	auto[1]	auto[0]	202603	1			T24	8		T26	43		T1	44
bins_for_gpio_bits[31]	auto[1]	auto[1]	4722629	1			T24	66		T25	16		T26	273