Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7065407 |
1 |
|
|
T24 |
212 |
|
T25 |
48 |
|
T26 |
839 |
| auto[1] |
4950065 |
1 |
|
|
T26 |
849 |
|
T1 |
534 |
|
T11 |
190 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11383836 |
1 |
|
|
T24 |
212 |
|
T25 |
48 |
|
T26 |
1649 |
| auto[1] |
631636 |
1 |
|
|
T26 |
39 |
|
T1 |
28 |
|
T11 |
20 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7102711 |
1 |
|
|
T24 |
212 |
|
T25 |
48 |
|
T26 |
890 |
| auto[1] |
4912761 |
1 |
|
|
T26 |
798 |
|
T1 |
743 |
|
T11 |
248 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2132086 |
1 |
|
|
T26 |
348 |
|
T1 |
403 |
|
T11 |
111 |
| auto[1] |
auto[0] |
auto[1] |
313791 |
1 |
|
|
T26 |
20 |
|
T1 |
16 |
|
T11 |
10 |
| auto[1] |
auto[1] |
auto[0] |
2149039 |
1 |
|
|
T26 |
411 |
|
T1 |
312 |
|
T11 |
117 |
| auto[1] |
auto[1] |
auto[1] |
317845 |
1 |
|
|
T26 |
19 |
|
T1 |
12 |
|
T11 |
10 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7138695 |
1 |
|
|
T24 |
212 |
|
T25 |
48 |
|
T26 |
741 |
| auto[1] |
4876777 |
1 |
|
|
T26 |
947 |
|
T1 |
833 |
|
T11 |
200 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11383258 |
1 |
|
|
T24 |
212 |
|
T25 |
48 |
|
T26 |
1658 |
| auto[1] |
632214 |
1 |
|
|
T26 |
30 |
|
T1 |
23 |
|
T11 |
8 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7091301 |
1 |
|
|
T24 |
212 |
|
T25 |
48 |
|
T26 |
952 |
| auto[1] |
4924171 |
1 |
|
|
T26 |
736 |
|
T1 |
793 |
|
T11 |
186 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2166660 |
1 |
|
|
T26 |
378 |
|
T1 |
315 |
|
T11 |
104 |
| auto[1] |
auto[0] |
auto[1] |
319214 |
1 |
|
|
T26 |
19 |
|
T1 |
10 |
|
T11 |
6 |
| auto[1] |
auto[1] |
auto[0] |
2125297 |
1 |
|
|
T26 |
328 |
|
T1 |
455 |
|
T11 |
74 |
| auto[1] |
auto[1] |
auto[1] |
313000 |
1 |
|
|
T26 |
11 |
|
T1 |
13 |
|
T11 |
2 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7100721 |
1 |
|
|
T24 |
212 |
|
T25 |
48 |
|
T26 |
726 |
| auto[1] |
4914751 |
1 |
|
|
T26 |
962 |
|
T1 |
611 |
|
T11 |
267 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11376100 |
1 |
|
|
T24 |
212 |
|
T25 |
48 |
|
T26 |
1660 |
| auto[1] |
639372 |
1 |
|
|
T26 |
28 |
|
T1 |
28 |
|
T11 |
15 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7046164 |
1 |
|
|
T24 |
212 |
|
T25 |
48 |
|
T26 |
941 |
| auto[1] |
4969308 |
1 |
|
|
T26 |
747 |
|
T1 |
877 |
|
T11 |
249 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2167923 |
1 |
|
|
T26 |
251 |
|
T1 |
477 |
|
T11 |
82 |
| auto[1] |
auto[0] |
auto[1] |
319553 |
1 |
|
|
T26 |
4 |
|
T1 |
14 |
|
T11 |
3 |
| auto[1] |
auto[1] |
auto[0] |
2162013 |
1 |
|
|
T26 |
468 |
|
T1 |
372 |
|
T11 |
152 |
| auto[1] |
auto[1] |
auto[1] |
319819 |
1 |
|
|
T26 |
24 |
|
T1 |
14 |
|
T11 |
12 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7089749 |
1 |
|
|
T24 |
212 |
|
T25 |
48 |
|
T26 |
917 |
| auto[1] |
4925723 |
1 |
|
|
T26 |
771 |
|
T1 |
594 |
|
T11 |
213 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11389042 |
1 |
|
|
T24 |
212 |
|
T25 |
48 |
|
T26 |
1658 |
| auto[1] |
626430 |
1 |
|
|
T26 |
30 |
|
T1 |
29 |
|
T11 |
5 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7132122 |
1 |
|
|
T24 |
212 |
|
T25 |
48 |
|
T26 |
945 |
| auto[1] |
4883350 |
1 |
|
|
T26 |
743 |
|
T1 |
756 |
|
T11 |
178 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2134036 |
1 |
|
|
T26 |
398 |
|
T1 |
407 |
|
T11 |
75 |
| auto[1] |
auto[0] |
auto[1] |
313676 |
1 |
|
|
T26 |
17 |
|
T1 |
19 |
|
T11 |
1 |
| auto[1] |
auto[1] |
auto[0] |
2122884 |
1 |
|
|
T26 |
315 |
|
T1 |
320 |
|
T11 |
98 |
| auto[1] |
auto[1] |
auto[1] |
312754 |
1 |
|
|
T26 |
13 |
|
T1 |
10 |
|
T11 |
4 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7068897 |
1 |
|
|
T24 |
212 |
|
T25 |
48 |
|
T26 |
928 |
| auto[1] |
4946575 |
1 |
|
|
T26 |
760 |
|
T1 |
772 |
|
T11 |
227 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11385727 |
1 |
|
|
T24 |
212 |
|
T25 |
48 |
|
T26 |
1651 |
| auto[1] |
629745 |
1 |
|
|
T26 |
37 |
|
T1 |
34 |
|
T11 |
7 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7108089 |
1 |
|
|
T24 |
212 |
|
T25 |
48 |
|
T26 |
829 |
| auto[1] |
4907383 |
1 |
|
|
T26 |
859 |
|
T1 |
806 |
|
T11 |
122 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2122948 |
1 |
|
|
T26 |
453 |
|
T1 |
328 |
|
T11 |
33 |
| auto[1] |
auto[0] |
auto[1] |
312610 |
1 |
|
|
T26 |
19 |
|
T1 |
14 |
|
T19 |
101 |
| auto[1] |
auto[1] |
auto[0] |
2154690 |
1 |
|
|
T26 |
369 |
|
T1 |
444 |
|
T11 |
82 |
| auto[1] |
auto[1] |
auto[1] |
317135 |
1 |
|
|
T26 |
18 |
|
T1 |
20 |
|
T11 |
7 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7067116 |
1 |
|
|
T24 |
212 |
|
T25 |
48 |
|
T26 |
955 |
| auto[1] |
4948356 |
1 |
|
|
T26 |
733 |
|
T1 |
819 |
|
T11 |
206 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11387701 |
1 |
|
|
T24 |
212 |
|
T25 |
48 |
|
T26 |
1648 |
| auto[1] |
627771 |
1 |
|
|
T26 |
40 |
|
T1 |
26 |
|
T11 |
19 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7122830 |
1 |
|
|
T24 |
212 |
|
T25 |
48 |
|
T26 |
785 |
| auto[1] |
4892642 |
1 |
|
|
T26 |
903 |
|
T1 |
695 |
|
T11 |
237 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2131562 |
1 |
|
|
T26 |
501 |
|
T1 |
275 |
|
T11 |
98 |
| auto[1] |
auto[0] |
auto[1] |
313383 |
1 |
|
|
T26 |
32 |
|
T1 |
11 |
|
T11 |
10 |
| auto[1] |
auto[1] |
auto[0] |
2133309 |
1 |
|
|
T26 |
362 |
|
T1 |
394 |
|
T11 |
120 |
| auto[1] |
auto[1] |
auto[1] |
314388 |
1 |
|
|
T26 |
8 |
|
T1 |
15 |
|
T11 |
9 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7083486 |
1 |
|
|
T24 |
212 |
|
T25 |
48 |
|
T26 |
834 |
| auto[1] |
4931986 |
1 |
|
|
T26 |
854 |
|
T1 |
789 |
|
T11 |
151 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11385491 |
1 |
|
|
T24 |
212 |
|
T25 |
48 |
|
T26 |
1657 |
| auto[1] |
629981 |
1 |
|
|
T26 |
31 |
|
T1 |
28 |
|
T11 |
17 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7109589 |
1 |
|
|
T24 |
212 |
|
T25 |
48 |
|
T26 |
787 |
| auto[1] |
4905883 |
1 |
|
|
T26 |
901 |
|
T1 |
775 |
|
T11 |
232 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2134068 |
1 |
|
|
T26 |
399 |
|
T1 |
354 |
|
T11 |
128 |
| auto[1] |
auto[0] |
auto[1] |
313785 |
1 |
|
|
T26 |
14 |
|
T1 |
14 |
|
T11 |
12 |
| auto[1] |
auto[1] |
auto[0] |
2141834 |
1 |
|
|
T26 |
471 |
|
T1 |
393 |
|
T11 |
87 |
| auto[1] |
auto[1] |
auto[1] |
316196 |
1 |
|
|
T26 |
17 |
|
T1 |
14 |
|
T11 |
5 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7077255 |
1 |
|
|
T24 |
212 |
|
T25 |
48 |
|
T26 |
793 |
| auto[1] |
4938217 |
1 |
|
|
T26 |
895 |
|
T1 |
700 |
|
T11 |
141 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11379561 |
1 |
|
|
T24 |
212 |
|
T25 |
48 |
|
T26 |
1651 |
| auto[1] |
635911 |
1 |
|
|
T26 |
37 |
|
T1 |
35 |
|
T11 |
9 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7076965 |
1 |
|
|
T24 |
212 |
|
T25 |
48 |
|
T26 |
870 |
| auto[1] |
4938507 |
1 |
|
|
T26 |
818 |
|
T1 |
785 |
|
T11 |
181 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2141164 |
1 |
|
|
T26 |
365 |
|
T1 |
440 |
|
T11 |
124 |
| auto[1] |
auto[0] |
auto[1] |
316349 |
1 |
|
|
T26 |
16 |
|
T1 |
25 |
|
T11 |
9 |
| auto[1] |
auto[1] |
auto[0] |
2161432 |
1 |
|
|
T26 |
416 |
|
T1 |
310 |
|
T11 |
48 |
| auto[1] |
auto[1] |
auto[1] |
319562 |
1 |
|
|
T26 |
21 |
|
T1 |
10 |
|
T19 |
102 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7098846 |
1 |
|
|
T24 |
212 |
|
T25 |
48 |
|
T26 |
980 |
| auto[1] |
4916626 |
1 |
|
|
T26 |
708 |
|
T1 |
770 |
|
T11 |
217 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11382609 |
1 |
|
|
T24 |
212 |
|
T25 |
48 |
|
T26 |
1656 |
| auto[1] |
632863 |
1 |
|
|
T26 |
32 |
|
T1 |
30 |
|
T11 |
10 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7091059 |
1 |
|
|
T24 |
212 |
|
T25 |
48 |
|
T26 |
767 |
| auto[1] |
4924413 |
1 |
|
|
T26 |
921 |
|
T1 |
727 |
|
T11 |
179 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2146293 |
1 |
|
|
T26 |
475 |
|
T1 |
354 |
|
T11 |
68 |
| auto[1] |
auto[0] |
auto[1] |
316711 |
1 |
|
|
T26 |
14 |
|
T1 |
16 |
|
T11 |
3 |
| auto[1] |
auto[1] |
auto[0] |
2145257 |
1 |
|
|
T26 |
414 |
|
T1 |
343 |
|
T11 |
101 |
| auto[1] |
auto[1] |
auto[1] |
316152 |
1 |
|
|
T26 |
18 |
|
T1 |
14 |
|
T11 |
7 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7079683 |
1 |
|
|
T24 |
212 |
|
T25 |
48 |
|
T26 |
784 |
| auto[1] |
4935789 |
1 |
|
|
T26 |
904 |
|
T1 |
740 |
|
T11 |
233 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11384567 |
1 |
|
|
T24 |
212 |
|
T25 |
48 |
|
T26 |
1641 |
| auto[1] |
630905 |
1 |
|
|
T26 |
47 |
|
T1 |
29 |
|
T11 |
14 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7096235 |
1 |
|
|
T24 |
212 |
|
T25 |
48 |
|
T26 |
731 |
| auto[1] |
4919237 |
1 |
|
|
T26 |
957 |
|
T1 |
740 |
|
T11 |
218 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2123033 |
1 |
|
|
T26 |
411 |
|
T1 |
394 |
|
T11 |
81 |
| auto[1] |
auto[0] |
auto[1] |
311772 |
1 |
|
|
T26 |
24 |
|
T1 |
15 |
|
T11 |
7 |
| auto[1] |
auto[1] |
auto[0] |
2165299 |
1 |
|
|
T26 |
499 |
|
T1 |
317 |
|
T11 |
123 |
| auto[1] |
auto[1] |
auto[1] |
319133 |
1 |
|
|
T26 |
23 |
|
T1 |
14 |
|
T11 |
7 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7108524 |
1 |
|
|
T24 |
212 |
|
T25 |
48 |
|
T26 |
928 |
| auto[1] |
4906948 |
1 |
|
|
T26 |
760 |
|
T1 |
848 |
|
T11 |
131 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11382234 |
1 |
|
|
T24 |
212 |
|
T25 |
48 |
|
T26 |
1664 |
| auto[1] |
633238 |
1 |
|
|
T26 |
24 |
|
T1 |
29 |
|
T11 |
16 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7100197 |
1 |
|
|
T24 |
212 |
|
T25 |
48 |
|
T26 |
950 |
| auto[1] |
4915275 |
1 |
|
|
T26 |
738 |
|
T1 |
773 |
|
T11 |
244 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2157578 |
1 |
|
|
T26 |
398 |
|
T1 |
358 |
|
T11 |
153 |
| auto[1] |
auto[0] |
auto[1] |
319455 |
1 |
|
|
T26 |
14 |
|
T1 |
16 |
|
T11 |
9 |
| auto[1] |
auto[1] |
auto[0] |
2124459 |
1 |
|
|
T26 |
316 |
|
T1 |
386 |
|
T11 |
75 |
| auto[1] |
auto[1] |
auto[1] |
313783 |
1 |
|
|
T26 |
10 |
|
T1 |
13 |
|
T11 |
7 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7100116 |
1 |
|
|
T24 |
212 |
|
T25 |
48 |
|
T26 |
805 |
| auto[1] |
4915356 |
1 |
|
|
T26 |
883 |
|
T1 |
574 |
|
T11 |
252 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11381950 |
1 |
|
|
T24 |
212 |
|
T25 |
48 |
|
T26 |
1648 |
| auto[1] |
633522 |
1 |
|
|
T26 |
40 |
|
T1 |
32 |
|
T11 |
13 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7081070 |
1 |
|
|
T24 |
212 |
|
T25 |
48 |
|
T26 |
895 |
| auto[1] |
4934402 |
1 |
|
|
T26 |
793 |
|
T1 |
858 |
|
T11 |
225 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2172309 |
1 |
|
|
T26 |
365 |
|
T1 |
514 |
|
T11 |
70 |
| auto[1] |
auto[0] |
auto[1] |
320204 |
1 |
|
|
T26 |
14 |
|
T1 |
22 |
|
T11 |
4 |
| auto[1] |
auto[1] |
auto[0] |
2128571 |
1 |
|
|
T26 |
388 |
|
T1 |
312 |
|
T11 |
142 |
| auto[1] |
auto[1] |
auto[1] |
313318 |
1 |
|
|
T26 |
26 |
|
T1 |
10 |
|
T11 |
9 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7072130 |
1 |
|
|
T24 |
212 |
|
T25 |
48 |
|
T26 |
889 |
| auto[1] |
4943342 |
1 |
|
|
T26 |
799 |
|
T1 |
813 |
|
T11 |
209 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11384859 |
1 |
|
|
T24 |
212 |
|
T25 |
48 |
|
T26 |
1645 |
| auto[1] |
630613 |
1 |
|
|
T26 |
43 |
|
T1 |
28 |
|
T11 |
15 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7101714 |
1 |
|
|
T24 |
212 |
|
T25 |
48 |
|
T26 |
698 |
| auto[1] |
4913758 |
1 |
|
|
T26 |
990 |
|
T1 |
675 |
|
T11 |
207 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2139633 |
1 |
|
|
T26 |
515 |
|
T1 |
254 |
|
T11 |
69 |
| auto[1] |
auto[0] |
auto[1] |
314662 |
1 |
|
|
T26 |
25 |
|
T1 |
10 |
|
T11 |
6 |
| auto[1] |
auto[1] |
auto[0] |
2143512 |
1 |
|
|
T26 |
432 |
|
T1 |
393 |
|
T11 |
123 |
| auto[1] |
auto[1] |
auto[1] |
315951 |
1 |
|
|
T26 |
18 |
|
T1 |
18 |
|
T11 |
9 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7111019 |
1 |
|
|
T24 |
212 |
|
T25 |
48 |
|
T26 |
632 |
| auto[1] |
4904453 |
1 |
|
|
T26 |
1056 |
|
T1 |
645 |
|
T11 |
153 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11384001 |
1 |
|
|
T24 |
212 |
|
T25 |
48 |
|
T26 |
1653 |
| auto[1] |
631471 |
1 |
|
|
T26 |
35 |
|
T1 |
25 |
|
T11 |
6 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7103236 |
1 |
|
|
T24 |
212 |
|
T25 |
48 |
|
T26 |
928 |
| auto[1] |
4912236 |
1 |
|
|
T26 |
760 |
|
T1 |
648 |
|
T11 |
197 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2153098 |
1 |
|
|
T26 |
207 |
|
T1 |
339 |
|
T11 |
118 |
| auto[1] |
auto[0] |
auto[1] |
317503 |
1 |
|
|
T26 |
9 |
|
T1 |
14 |
|
T11 |
4 |
| auto[1] |
auto[1] |
auto[0] |
2127667 |
1 |
|
|
T26 |
518 |
|
T1 |
284 |
|
T11 |
73 |
| auto[1] |
auto[1] |
auto[1] |
313968 |
1 |
|
|
T26 |
26 |
|
T1 |
11 |
|
T11 |
2 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7079873 |
1 |
|
|
T24 |
212 |
|
T25 |
48 |
|
T26 |
777 |
| auto[1] |
4935599 |
1 |
|
|
T26 |
911 |
|
T1 |
765 |
|
T11 |
205 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11383938 |
1 |
|
|
T24 |
212 |
|
T25 |
48 |
|
T26 |
1673 |
| auto[1] |
631534 |
1 |
|
|
T26 |
15 |
|
T1 |
13 |
|
T11 |
13 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7093296 |
1 |
|
|
T24 |
212 |
|
T25 |
48 |
|
T26 |
977 |
| auto[1] |
4922176 |
1 |
|
|
T26 |
711 |
|
T1 |
498 |
|
T11 |
183 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2148724 |
1 |
|
|
T26 |
249 |
|
T1 |
213 |
|
T11 |
72 |
| auto[1] |
auto[0] |
auto[1] |
315840 |
1 |
|
|
T26 |
5 |
|
T1 |
8 |
|
T11 |
3 |
| auto[1] |
auto[1] |
auto[0] |
2141918 |
1 |
|
|
T26 |
447 |
|
T1 |
272 |
|
T11 |
98 |
| auto[1] |
auto[1] |
auto[1] |
315694 |
1 |
|
|
T26 |
10 |
|
T1 |
5 |
|
T11 |
10 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7077398 |
1 |
|
|
T24 |
212 |
|
T25 |
48 |
|
T26 |
527 |
| auto[1] |
4938074 |
1 |
|
|
T26 |
1161 |
|
T1 |
858 |
|
T11 |
185 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11383216 |
1 |
|
|
T24 |
212 |
|
T25 |
48 |
|
T26 |
1636 |
| auto[1] |
632256 |
1 |
|
|
T26 |
52 |
|
T1 |
27 |
|
T11 |
7 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7095449 |
1 |
|
|
T24 |
212 |
|
T25 |
48 |
|
T26 |
676 |
| auto[1] |
4920023 |
1 |
|
|
T26 |
1012 |
|
T1 |
765 |
|
T11 |
164 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2140570 |
1 |
|
|
T26 |
252 |
|
T1 |
255 |
|
T11 |
101 |
| auto[1] |
auto[0] |
auto[1] |
314668 |
1 |
|
|
T26 |
14 |
|
T1 |
7 |
|
T11 |
4 |
| auto[1] |
auto[1] |
auto[0] |
2147197 |
1 |
|
|
T26 |
708 |
|
T1 |
483 |
|
T11 |
56 |
| auto[1] |
auto[1] |
auto[1] |
317588 |
1 |
|
|
T26 |
38 |
|
T1 |
20 |
|
T11 |
3 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7065249 |
1 |
|
|
T24 |
212 |
|
T25 |
48 |
|
T26 |
813 |
| auto[1] |
4950223 |
1 |
|
|
T26 |
875 |
|
T1 |
833 |
|
T11 |
273 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11386034 |
1 |
|
|
T24 |
212 |
|
T25 |
48 |
|
T26 |
1662 |
| auto[1] |
629438 |
1 |
|
|
T26 |
26 |
|
T1 |
32 |
|
T11 |
15 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7112272 |
1 |
|
|
T24 |
212 |
|
T25 |
48 |
|
T26 |
674 |
| auto[1] |
4903200 |
1 |
|
|
T26 |
1014 |
|
T1 |
688 |
|
T11 |
235 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2136003 |
1 |
|
|
T26 |
463 |
|
T1 |
331 |
|
T11 |
50 |
| auto[1] |
auto[0] |
auto[1] |
314124 |
1 |
|
|
T26 |
13 |
|
T1 |
16 |
|
T11 |
4 |
| auto[1] |
auto[1] |
auto[0] |
2137759 |
1 |
|
|
T26 |
525 |
|
T1 |
325 |
|
T11 |
170 |
| auto[1] |
auto[1] |
auto[1] |
315314 |
1 |
|
|
T26 |
13 |
|
T1 |
16 |
|
T11 |
11 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7068723 |
1 |
|
|
T24 |
212 |
|
T25 |
48 |
|
T26 |
708 |
| auto[1] |
4946749 |
1 |
|
|
T26 |
980 |
|
T1 |
600 |
|
T11 |
207 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11385554 |
1 |
|
|
T24 |
212 |
|
T25 |
48 |
|
T26 |
1656 |
| auto[1] |
629918 |
1 |
|
|
T26 |
32 |
|
T1 |
23 |
|
T11 |
14 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7108782 |
1 |
|
|
T24 |
212 |
|
T25 |
48 |
|
T26 |
885 |
| auto[1] |
4906690 |
1 |
|
|
T26 |
803 |
|
T1 |
629 |
|
T11 |
228 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2138014 |
1 |
|
|
T26 |
359 |
|
T1 |
356 |
|
T11 |
106 |
| auto[1] |
auto[0] |
auto[1] |
314161 |
1 |
|
|
T26 |
13 |
|
T1 |
16 |
|
T11 |
5 |
| auto[1] |
auto[1] |
auto[0] |
2138758 |
1 |
|
|
T26 |
412 |
|
T1 |
250 |
|
T11 |
108 |
| auto[1] |
auto[1] |
auto[1] |
315757 |
1 |
|
|
T26 |
19 |
|
T1 |
7 |
|
T11 |
9 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7102445 |
1 |
|
|
T24 |
212 |
|
T25 |
48 |
|
T26 |
839 |
| auto[1] |
4913027 |
1 |
|
|
T26 |
849 |
|
T1 |
744 |
|
T11 |
159 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11382953 |
1 |
|
|
T24 |
212 |
|
T25 |
48 |
|
T26 |
1650 |
| auto[1] |
632519 |
1 |
|
|
T26 |
38 |
|
T1 |
40 |
|
T11 |
19 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7085427 |
1 |
|
|
T24 |
212 |
|
T25 |
48 |
|
T26 |
824 |
| auto[1] |
4930045 |
1 |
|
|
T26 |
864 |
|
T1 |
852 |
|
T11 |
249 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2146942 |
1 |
|
|
T26 |
432 |
|
T1 |
429 |
|
T11 |
138 |
| auto[1] |
auto[0] |
auto[1] |
315682 |
1 |
|
|
T26 |
20 |
|
T1 |
22 |
|
T11 |
13 |
| auto[1] |
auto[1] |
auto[0] |
2150584 |
1 |
|
|
T26 |
394 |
|
T1 |
383 |
|
T11 |
92 |
| auto[1] |
auto[1] |
auto[1] |
316837 |
1 |
|
|
T26 |
18 |
|
T1 |
18 |
|
T11 |
6 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |