Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7055393 |
1 |
|
|
T24 |
212 |
|
T25 |
48 |
|
T26 |
683 |
| auto[1] |
4960079 |
1 |
|
|
T26 |
1005 |
|
T1 |
994 |
|
T11 |
195 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11384832 |
1 |
|
|
T24 |
212 |
|
T25 |
48 |
|
T26 |
1646 |
| auto[1] |
630640 |
1 |
|
|
T26 |
42 |
|
T1 |
27 |
|
T11 |
11 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7095692 |
1 |
|
|
T24 |
212 |
|
T25 |
48 |
|
T26 |
664 |
| auto[1] |
4919780 |
1 |
|
|
T26 |
1024 |
|
T1 |
789 |
|
T11 |
212 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2131116 |
1 |
|
|
T26 |
447 |
|
T1 |
215 |
|
T11 |
120 |
| auto[1] |
auto[0] |
auto[1] |
313185 |
1 |
|
|
T26 |
20 |
|
T1 |
8 |
|
T11 |
2 |
| auto[1] |
auto[1] |
auto[0] |
2158024 |
1 |
|
|
T26 |
535 |
|
T1 |
547 |
|
T11 |
81 |
| auto[1] |
auto[1] |
auto[1] |
317455 |
1 |
|
|
T26 |
22 |
|
T1 |
19 |
|
T11 |
9 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |