Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7108604 |
1 |
|
|
T24 |
212 |
|
T25 |
48 |
|
T26 |
864 |
| auto[1] |
4906868 |
1 |
|
|
T26 |
824 |
|
T1 |
736 |
|
T11 |
165 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11385101 |
1 |
|
|
T24 |
212 |
|
T25 |
48 |
|
T26 |
1668 |
| auto[1] |
630371 |
1 |
|
|
T26 |
20 |
|
T1 |
22 |
|
T11 |
10 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7105465 |
1 |
|
|
T24 |
212 |
|
T25 |
48 |
|
T26 |
1082 |
| auto[1] |
4910007 |
1 |
|
|
T26 |
606 |
|
T1 |
644 |
|
T11 |
135 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2143436 |
1 |
|
|
T26 |
306 |
|
T1 |
326 |
|
T11 |
70 |
| auto[1] |
auto[0] |
auto[1] |
315214 |
1 |
|
|
T26 |
9 |
|
T1 |
14 |
|
T11 |
4 |
| auto[1] |
auto[1] |
auto[0] |
2136200 |
1 |
|
|
T26 |
280 |
|
T1 |
296 |
|
T11 |
55 |
| auto[1] |
auto[1] |
auto[1] |
315157 |
1 |
|
|
T26 |
11 |
|
T1 |
8 |
|
T11 |
6 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |