Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7098881 |
1 |
|
|
T24 |
212 |
|
T25 |
48 |
|
T26 |
681 |
| auto[1] |
4916591 |
1 |
|
|
T26 |
1007 |
|
T1 |
950 |
|
T11 |
235 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11384761 |
1 |
|
|
T24 |
212 |
|
T25 |
48 |
|
T26 |
1661 |
| auto[1] |
630711 |
1 |
|
|
T26 |
27 |
|
T1 |
27 |
|
T11 |
17 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7092001 |
1 |
|
|
T24 |
212 |
|
T25 |
48 |
|
T26 |
958 |
| auto[1] |
4923471 |
1 |
|
|
T26 |
730 |
|
T1 |
764 |
|
T11 |
251 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2145102 |
1 |
|
|
T26 |
310 |
|
T1 |
267 |
|
T11 |
74 |
| auto[1] |
auto[0] |
auto[1] |
315051 |
1 |
|
|
T26 |
13 |
|
T1 |
9 |
|
T11 |
6 |
| auto[1] |
auto[1] |
auto[0] |
2147658 |
1 |
|
|
T26 |
393 |
|
T1 |
470 |
|
T11 |
160 |
| auto[1] |
auto[1] |
auto[1] |
315660 |
1 |
|
|
T26 |
14 |
|
T1 |
18 |
|
T11 |
11 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |