Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7095543 |
1 |
|
|
T24 |
212 |
|
T25 |
48 |
|
T26 |
797 |
| auto[1] |
4919929 |
1 |
|
|
T26 |
891 |
|
T1 |
731 |
|
T11 |
241 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11382526 |
1 |
|
|
T24 |
212 |
|
T25 |
48 |
|
T26 |
1654 |
| auto[1] |
632946 |
1 |
|
|
T26 |
34 |
|
T1 |
30 |
|
T11 |
16 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7089150 |
1 |
|
|
T24 |
212 |
|
T25 |
48 |
|
T26 |
787 |
| auto[1] |
4926322 |
1 |
|
|
T26 |
901 |
|
T1 |
812 |
|
T11 |
184 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2144561 |
1 |
|
|
T26 |
375 |
|
T1 |
353 |
|
T11 |
66 |
| auto[1] |
auto[0] |
auto[1] |
315081 |
1 |
|
|
T26 |
14 |
|
T1 |
20 |
|
T11 |
7 |
| auto[1] |
auto[1] |
auto[0] |
2148815 |
1 |
|
|
T26 |
492 |
|
T1 |
429 |
|
T11 |
102 |
| auto[1] |
auto[1] |
auto[1] |
317865 |
1 |
|
|
T26 |
20 |
|
T1 |
10 |
|
T11 |
9 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |