Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7110711 |
1 |
|
|
T24 |
212 |
|
T25 |
48 |
|
T26 |
723 |
| auto[1] |
4904761 |
1 |
|
|
T26 |
965 |
|
T1 |
697 |
|
T11 |
122 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11387650 |
1 |
|
|
T24 |
212 |
|
T25 |
48 |
|
T26 |
1647 |
| auto[1] |
627822 |
1 |
|
|
T26 |
41 |
|
T1 |
26 |
|
T11 |
9 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7119462 |
1 |
|
|
T24 |
212 |
|
T25 |
48 |
|
T26 |
652 |
| auto[1] |
4896010 |
1 |
|
|
T26 |
1036 |
|
T1 |
708 |
|
T11 |
151 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2149316 |
1 |
|
|
T26 |
460 |
|
T1 |
376 |
|
T11 |
105 |
| auto[1] |
auto[0] |
auto[1] |
317284 |
1 |
|
|
T26 |
19 |
|
T1 |
14 |
|
T11 |
6 |
| auto[1] |
auto[1] |
auto[0] |
2118872 |
1 |
|
|
T26 |
535 |
|
T1 |
306 |
|
T11 |
37 |
| auto[1] |
auto[1] |
auto[1] |
310538 |
1 |
|
|
T26 |
22 |
|
T1 |
12 |
|
T11 |
3 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |