Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7065407 |
1 |
|
|
T24 |
212 |
|
T25 |
48 |
|
T26 |
839 |
| auto[1] |
4950065 |
1 |
|
|
T26 |
849 |
|
T1 |
534 |
|
T11 |
190 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9937593 |
1 |
|
|
T24 |
212 |
|
T25 |
48 |
|
T26 |
1519 |
| auto[1] |
2077879 |
1 |
|
|
T26 |
169 |
|
T1 |
538 |
|
T11 |
82 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7100016 |
1 |
|
|
T24 |
212 |
|
T25 |
48 |
|
T26 |
976 |
| auto[1] |
4915456 |
1 |
|
|
T26 |
712 |
|
T1 |
695 |
|
T11 |
150 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1420954 |
1 |
|
|
T26 |
245 |
|
T1 |
103 |
|
T11 |
31 |
| auto[1] |
auto[0] |
auto[1] |
1043009 |
1 |
|
|
T26 |
87 |
|
T1 |
312 |
|
T11 |
35 |
| auto[1] |
auto[1] |
auto[0] |
1416623 |
1 |
|
|
T26 |
298 |
|
T1 |
54 |
|
T11 |
37 |
| auto[1] |
auto[1] |
auto[1] |
1034870 |
1 |
|
|
T26 |
82 |
|
T1 |
226 |
|
T11 |
47 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |