Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7138695 |
1 |
|
|
T24 |
212 |
|
T25 |
48 |
|
T26 |
741 |
| auto[1] |
4876777 |
1 |
|
|
T26 |
947 |
|
T1 |
833 |
|
T11 |
200 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9937785 |
1 |
|
|
T24 |
212 |
|
T25 |
48 |
|
T26 |
1508 |
| auto[1] |
2077687 |
1 |
|
|
T26 |
180 |
|
T1 |
440 |
|
T11 |
70 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7097720 |
1 |
|
|
T24 |
212 |
|
T25 |
48 |
|
T26 |
1008 |
| auto[1] |
4917752 |
1 |
|
|
T26 |
680 |
|
T1 |
498 |
|
T11 |
155 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1437825 |
1 |
|
|
T26 |
231 |
|
T1 |
27 |
|
T11 |
40 |
| auto[1] |
auto[0] |
auto[1] |
1051404 |
1 |
|
|
T26 |
93 |
|
T1 |
214 |
|
T11 |
24 |
| auto[1] |
auto[1] |
auto[0] |
1402240 |
1 |
|
|
T26 |
269 |
|
T1 |
31 |
|
T11 |
45 |
| auto[1] |
auto[1] |
auto[1] |
1026283 |
1 |
|
|
T26 |
87 |
|
T1 |
226 |
|
T11 |
46 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |