Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7100721 |
1 |
|
|
T24 |
212 |
|
T25 |
48 |
|
T26 |
726 |
| auto[1] |
4914751 |
1 |
|
|
T26 |
962 |
|
T1 |
611 |
|
T11 |
267 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9929242 |
1 |
|
|
T24 |
212 |
|
T25 |
48 |
|
T26 |
1506 |
| auto[1] |
2086230 |
1 |
|
|
T26 |
182 |
|
T1 |
353 |
|
T11 |
110 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7072872 |
1 |
|
|
T24 |
212 |
|
T25 |
48 |
|
T26 |
779 |
| auto[1] |
4942600 |
1 |
|
|
T26 |
909 |
|
T1 |
479 |
|
T11 |
188 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1428626 |
1 |
|
|
T26 |
266 |
|
T1 |
88 |
|
T11 |
21 |
| auto[1] |
auto[0] |
auto[1] |
1043361 |
1 |
|
|
T26 |
61 |
|
T1 |
227 |
|
T11 |
42 |
| auto[1] |
auto[1] |
auto[0] |
1427744 |
1 |
|
|
T26 |
461 |
|
T1 |
38 |
|
T11 |
57 |
| auto[1] |
auto[1] |
auto[1] |
1042869 |
1 |
|
|
T26 |
121 |
|
T1 |
126 |
|
T11 |
68 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |