Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7089749 |
1 |
|
|
T24 |
212 |
|
T25 |
48 |
|
T26 |
917 |
| auto[1] |
4925723 |
1 |
|
|
T26 |
771 |
|
T1 |
594 |
|
T11 |
213 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9935626 |
1 |
|
|
T24 |
212 |
|
T25 |
48 |
|
T26 |
1585 |
| auto[1] |
2079846 |
1 |
|
|
T26 |
103 |
|
T1 |
572 |
|
T11 |
89 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7097341 |
1 |
|
|
T24 |
212 |
|
T25 |
48 |
|
T26 |
941 |
| auto[1] |
4918131 |
1 |
|
|
T26 |
747 |
|
T1 |
771 |
|
T11 |
167 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1415928 |
1 |
|
|
T26 |
315 |
|
T1 |
129 |
|
T11 |
32 |
| auto[1] |
auto[0] |
auto[1] |
1040901 |
1 |
|
|
T26 |
38 |
|
T1 |
289 |
|
T11 |
42 |
| auto[1] |
auto[1] |
auto[0] |
1422357 |
1 |
|
|
T26 |
329 |
|
T1 |
70 |
|
T11 |
46 |
| auto[1] |
auto[1] |
auto[1] |
1038945 |
1 |
|
|
T26 |
65 |
|
T1 |
283 |
|
T11 |
47 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |