Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7068897 |
1 |
|
|
T24 |
212 |
|
T25 |
48 |
|
T26 |
928 |
| auto[1] |
4946575 |
1 |
|
|
T26 |
760 |
|
T1 |
772 |
|
T11 |
227 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9935029 |
1 |
|
|
T24 |
212 |
|
T25 |
48 |
|
T26 |
1511 |
| auto[1] |
2080443 |
1 |
|
|
T26 |
177 |
|
T1 |
662 |
|
T11 |
91 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7084580 |
1 |
|
|
T24 |
212 |
|
T25 |
48 |
|
T26 |
1001 |
| auto[1] |
4930892 |
1 |
|
|
T26 |
687 |
|
T1 |
810 |
|
T11 |
209 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1419983 |
1 |
|
|
T26 |
250 |
|
T1 |
69 |
|
T11 |
48 |
| auto[1] |
auto[0] |
auto[1] |
1040949 |
1 |
|
|
T26 |
94 |
|
T1 |
287 |
|
T11 |
58 |
| auto[1] |
auto[1] |
auto[0] |
1430466 |
1 |
|
|
T26 |
260 |
|
T1 |
79 |
|
T11 |
70 |
| auto[1] |
auto[1] |
auto[1] |
1039494 |
1 |
|
|
T26 |
83 |
|
T1 |
375 |
|
T11 |
33 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |