Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7101612 |
1 |
|
|
T24 |
212 |
|
T25 |
48 |
|
T26 |
854 |
| auto[1] |
4913860 |
1 |
|
|
T26 |
834 |
|
T1 |
615 |
|
T11 |
161 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11382927 |
1 |
|
|
T24 |
212 |
|
T25 |
48 |
|
T26 |
1658 |
| auto[1] |
632545 |
1 |
|
|
T26 |
30 |
|
T1 |
23 |
|
T11 |
12 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7103038 |
1 |
|
|
T24 |
212 |
|
T25 |
48 |
|
T26 |
944 |
| auto[1] |
4912434 |
1 |
|
|
T26 |
744 |
|
T1 |
607 |
|
T11 |
218 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2155844 |
1 |
|
|
T26 |
371 |
|
T1 |
427 |
|
T11 |
107 |
| auto[1] |
auto[0] |
auto[1] |
320223 |
1 |
|
|
T26 |
13 |
|
T1 |
15 |
|
T11 |
9 |
| auto[1] |
auto[1] |
auto[0] |
2124045 |
1 |
|
|
T26 |
343 |
|
T1 |
157 |
|
T11 |
99 |
| auto[1] |
auto[1] |
auto[1] |
312322 |
1 |
|
|
T26 |
17 |
|
T1 |
8 |
|
T11 |
3 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |