Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7083486 |
1 |
|
|
T24 |
212 |
|
T25 |
48 |
|
T26 |
834 |
| auto[1] |
4931986 |
1 |
|
|
T26 |
854 |
|
T1 |
789 |
|
T11 |
151 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9935474 |
1 |
|
|
T24 |
212 |
|
T25 |
48 |
|
T26 |
1486 |
| auto[1] |
2079998 |
1 |
|
|
T26 |
202 |
|
T1 |
486 |
|
T11 |
64 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7104343 |
1 |
|
|
T24 |
212 |
|
T25 |
48 |
|
T26 |
821 |
| auto[1] |
4911129 |
1 |
|
|
T26 |
867 |
|
T1 |
613 |
|
T11 |
195 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1416876 |
1 |
|
|
T26 |
343 |
|
T1 |
64 |
|
T11 |
83 |
| auto[1] |
auto[0] |
auto[1] |
1043291 |
1 |
|
|
T26 |
116 |
|
T1 |
201 |
|
T11 |
36 |
| auto[1] |
auto[1] |
auto[0] |
1414255 |
1 |
|
|
T26 |
322 |
|
T1 |
63 |
|
T11 |
48 |
| auto[1] |
auto[1] |
auto[1] |
1036707 |
1 |
|
|
T26 |
86 |
|
T1 |
285 |
|
T11 |
28 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |