Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7077255 |
1 |
|
|
T24 |
212 |
|
T25 |
48 |
|
T26 |
793 |
| auto[1] |
4938217 |
1 |
|
|
T26 |
895 |
|
T1 |
700 |
|
T11 |
141 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9941058 |
1 |
|
|
T24 |
212 |
|
T25 |
48 |
|
T26 |
1473 |
| auto[1] |
2074414 |
1 |
|
|
T26 |
215 |
|
T1 |
431 |
|
T11 |
129 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7102190 |
1 |
|
|
T24 |
212 |
|
T25 |
48 |
|
T26 |
829 |
| auto[1] |
4913282 |
1 |
|
|
T26 |
859 |
|
T1 |
649 |
|
T11 |
207 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1410291 |
1 |
|
|
T26 |
330 |
|
T1 |
112 |
|
T11 |
55 |
| auto[1] |
auto[0] |
auto[1] |
1038909 |
1 |
|
|
T26 |
91 |
|
T1 |
232 |
|
T11 |
75 |
| auto[1] |
auto[1] |
auto[0] |
1428577 |
1 |
|
|
T26 |
314 |
|
T1 |
106 |
|
T11 |
23 |
| auto[1] |
auto[1] |
auto[1] |
1035505 |
1 |
|
|
T26 |
124 |
|
T1 |
199 |
|
T11 |
54 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |