Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7098846 |
1 |
|
|
T24 |
212 |
|
T25 |
48 |
|
T26 |
980 |
| auto[1] |
4916626 |
1 |
|
|
T26 |
708 |
|
T1 |
770 |
|
T11 |
217 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9940939 |
1 |
|
|
T24 |
212 |
|
T25 |
48 |
|
T26 |
1541 |
| auto[1] |
2074533 |
1 |
|
|
T26 |
147 |
|
T1 |
417 |
|
T11 |
100 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7113984 |
1 |
|
|
T24 |
212 |
|
T25 |
48 |
|
T26 |
867 |
| auto[1] |
4901488 |
1 |
|
|
T26 |
821 |
|
T1 |
483 |
|
T11 |
186 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1417200 |
1 |
|
|
T26 |
384 |
|
T1 |
39 |
|
T11 |
19 |
| auto[1] |
auto[0] |
auto[1] |
1037656 |
1 |
|
|
T26 |
89 |
|
T1 |
183 |
|
T11 |
38 |
| auto[1] |
auto[1] |
auto[0] |
1409755 |
1 |
|
|
T26 |
290 |
|
T1 |
27 |
|
T11 |
67 |
| auto[1] |
auto[1] |
auto[1] |
1036877 |
1 |
|
|
T26 |
58 |
|
T1 |
234 |
|
T11 |
62 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |