Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7079683 |
1 |
|
|
T24 |
212 |
|
T25 |
48 |
|
T26 |
784 |
| auto[1] |
4935789 |
1 |
|
|
T26 |
904 |
|
T1 |
740 |
|
T11 |
233 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9944227 |
1 |
|
|
T24 |
212 |
|
T25 |
48 |
|
T26 |
1511 |
| auto[1] |
2071245 |
1 |
|
|
T26 |
177 |
|
T1 |
638 |
|
T11 |
88 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7108600 |
1 |
|
|
T24 |
212 |
|
T25 |
48 |
|
T26 |
911 |
| auto[1] |
4906872 |
1 |
|
|
T26 |
777 |
|
T1 |
851 |
|
T11 |
168 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1420394 |
1 |
|
|
T26 |
319 |
|
T1 |
111 |
|
T11 |
33 |
| auto[1] |
auto[0] |
auto[1] |
1039408 |
1 |
|
|
T26 |
84 |
|
T1 |
324 |
|
T11 |
33 |
| auto[1] |
auto[1] |
auto[0] |
1415233 |
1 |
|
|
T26 |
281 |
|
T1 |
102 |
|
T11 |
47 |
| auto[1] |
auto[1] |
auto[1] |
1031837 |
1 |
|
|
T26 |
93 |
|
T1 |
314 |
|
T11 |
55 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |