Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7108524 |
1 |
|
|
T24 |
212 |
|
T25 |
48 |
|
T26 |
928 |
| auto[1] |
4906948 |
1 |
|
|
T26 |
760 |
|
T1 |
848 |
|
T11 |
131 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9931547 |
1 |
|
|
T24 |
212 |
|
T25 |
48 |
|
T26 |
1503 |
| auto[1] |
2083925 |
1 |
|
|
T26 |
185 |
|
T1 |
656 |
|
T11 |
100 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7081012 |
1 |
|
|
T24 |
212 |
|
T25 |
48 |
|
T26 |
914 |
| auto[1] |
4934460 |
1 |
|
|
T26 |
774 |
|
T1 |
926 |
|
T11 |
174 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1423268 |
1 |
|
|
T26 |
354 |
|
T1 |
111 |
|
T11 |
51 |
| auto[1] |
auto[0] |
auto[1] |
1043755 |
1 |
|
|
T26 |
131 |
|
T1 |
289 |
|
T11 |
59 |
| auto[1] |
auto[1] |
auto[0] |
1427267 |
1 |
|
|
T26 |
235 |
|
T1 |
159 |
|
T11 |
23 |
| auto[1] |
auto[1] |
auto[1] |
1040170 |
1 |
|
|
T26 |
54 |
|
T1 |
367 |
|
T11 |
41 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |