Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7100116 |
1 |
|
|
T24 |
212 |
|
T25 |
48 |
|
T26 |
805 |
| auto[1] |
4915356 |
1 |
|
|
T26 |
883 |
|
T1 |
574 |
|
T11 |
252 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9945712 |
1 |
|
|
T24 |
212 |
|
T25 |
48 |
|
T26 |
1453 |
| auto[1] |
2069760 |
1 |
|
|
T26 |
235 |
|
T1 |
558 |
|
T11 |
96 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7107309 |
1 |
|
|
T24 |
212 |
|
T25 |
48 |
|
T26 |
867 |
| auto[1] |
4908163 |
1 |
|
|
T26 |
821 |
|
T1 |
743 |
|
T11 |
195 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1421780 |
1 |
|
|
T26 |
242 |
|
T1 |
120 |
|
T11 |
37 |
| auto[1] |
auto[0] |
auto[1] |
1039620 |
1 |
|
|
T26 |
57 |
|
T1 |
336 |
|
T11 |
33 |
| auto[1] |
auto[1] |
auto[0] |
1416623 |
1 |
|
|
T26 |
344 |
|
T1 |
65 |
|
T11 |
62 |
| auto[1] |
auto[1] |
auto[1] |
1030140 |
1 |
|
|
T26 |
178 |
|
T1 |
222 |
|
T11 |
63 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |