Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7072130 |
1 |
|
|
T24 |
212 |
|
T25 |
48 |
|
T26 |
889 |
| auto[1] |
4943342 |
1 |
|
|
T26 |
799 |
|
T1 |
813 |
|
T11 |
209 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9938865 |
1 |
|
|
T24 |
212 |
|
T25 |
48 |
|
T26 |
1551 |
| auto[1] |
2076607 |
1 |
|
|
T26 |
137 |
|
T1 |
691 |
|
T11 |
119 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7092617 |
1 |
|
|
T24 |
212 |
|
T25 |
48 |
|
T26 |
807 |
| auto[1] |
4922855 |
1 |
|
|
T26 |
881 |
|
T1 |
944 |
|
T11 |
205 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1418668 |
1 |
|
|
T26 |
348 |
|
T1 |
105 |
|
T11 |
38 |
| auto[1] |
auto[0] |
auto[1] |
1034699 |
1 |
|
|
T26 |
86 |
|
T1 |
305 |
|
T11 |
75 |
| auto[1] |
auto[1] |
auto[0] |
1427580 |
1 |
|
|
T26 |
396 |
|
T1 |
148 |
|
T11 |
48 |
| auto[1] |
auto[1] |
auto[1] |
1041908 |
1 |
|
|
T26 |
51 |
|
T1 |
386 |
|
T11 |
44 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |