Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7111019 |
1 |
|
|
T24 |
212 |
|
T25 |
48 |
|
T26 |
632 |
| auto[1] |
4904453 |
1 |
|
|
T26 |
1056 |
|
T1 |
645 |
|
T11 |
153 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9947446 |
1 |
|
|
T24 |
212 |
|
T25 |
48 |
|
T26 |
1494 |
| auto[1] |
2068026 |
1 |
|
|
T26 |
194 |
|
T1 |
472 |
|
T11 |
96 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7105235 |
1 |
|
|
T24 |
212 |
|
T25 |
48 |
|
T26 |
782 |
| auto[1] |
4910237 |
1 |
|
|
T26 |
906 |
|
T1 |
611 |
|
T11 |
180 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1421667 |
1 |
|
|
T26 |
290 |
|
T1 |
82 |
|
T11 |
30 |
| auto[1] |
auto[0] |
auto[1] |
1033759 |
1 |
|
|
T26 |
58 |
|
T1 |
295 |
|
T11 |
49 |
| auto[1] |
auto[1] |
auto[0] |
1420544 |
1 |
|
|
T26 |
422 |
|
T1 |
57 |
|
T11 |
54 |
| auto[1] |
auto[1] |
auto[1] |
1034267 |
1 |
|
|
T26 |
136 |
|
T1 |
177 |
|
T11 |
47 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |