Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7079873 |
1 |
|
|
T24 |
212 |
|
T25 |
48 |
|
T26 |
777 |
| auto[1] |
4935599 |
1 |
|
|
T26 |
911 |
|
T1 |
765 |
|
T11 |
205 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9940875 |
1 |
|
|
T24 |
212 |
|
T25 |
48 |
|
T26 |
1560 |
| auto[1] |
2074597 |
1 |
|
|
T26 |
128 |
|
T1 |
524 |
|
T11 |
75 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7097338 |
1 |
|
|
T24 |
212 |
|
T25 |
48 |
|
T26 |
949 |
| auto[1] |
4918134 |
1 |
|
|
T26 |
739 |
|
T1 |
695 |
|
T11 |
207 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1425007 |
1 |
|
|
T26 |
284 |
|
T1 |
105 |
|
T11 |
36 |
| auto[1] |
auto[0] |
auto[1] |
1039115 |
1 |
|
|
T26 |
55 |
|
T1 |
237 |
|
T11 |
37 |
| auto[1] |
auto[1] |
auto[0] |
1418530 |
1 |
|
|
T26 |
327 |
|
T1 |
66 |
|
T11 |
96 |
| auto[1] |
auto[1] |
auto[1] |
1035482 |
1 |
|
|
T26 |
73 |
|
T1 |
287 |
|
T11 |
38 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |