Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7105231 |
1 |
|
|
T24 |
212 |
|
T25 |
48 |
|
T26 |
755 |
| auto[1] |
4910241 |
1 |
|
|
T26 |
933 |
|
T1 |
751 |
|
T11 |
187 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11381728 |
1 |
|
|
T24 |
212 |
|
T25 |
48 |
|
T26 |
1654 |
| auto[1] |
633744 |
1 |
|
|
T26 |
34 |
|
T1 |
30 |
|
T11 |
9 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7084320 |
1 |
|
|
T24 |
212 |
|
T25 |
48 |
|
T26 |
745 |
| auto[1] |
4931152 |
1 |
|
|
T26 |
943 |
|
T1 |
870 |
|
T11 |
201 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2152420 |
1 |
|
|
T26 |
405 |
|
T1 |
472 |
|
T11 |
94 |
| auto[1] |
auto[0] |
auto[1] |
317437 |
1 |
|
|
T26 |
17 |
|
T1 |
14 |
|
T11 |
4 |
| auto[1] |
auto[1] |
auto[0] |
2144988 |
1 |
|
|
T26 |
504 |
|
T1 |
368 |
|
T11 |
98 |
| auto[1] |
auto[1] |
auto[1] |
316307 |
1 |
|
|
T26 |
17 |
|
T1 |
16 |
|
T11 |
5 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |