Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7077398 |
1 |
|
|
T24 |
212 |
|
T25 |
48 |
|
T26 |
527 |
| auto[1] |
4938074 |
1 |
|
|
T26 |
1161 |
|
T1 |
858 |
|
T11 |
185 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9948054 |
1 |
|
|
T24 |
212 |
|
T25 |
48 |
|
T26 |
1454 |
| auto[1] |
2067418 |
1 |
|
|
T26 |
234 |
|
T1 |
470 |
|
T11 |
94 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7105439 |
1 |
|
|
T24 |
212 |
|
T25 |
48 |
|
T26 |
807 |
| auto[1] |
4910033 |
1 |
|
|
T26 |
881 |
|
T1 |
670 |
|
T11 |
131 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1419584 |
1 |
|
|
T26 |
196 |
|
T1 |
92 |
|
T11 |
25 |
| auto[1] |
auto[0] |
auto[1] |
1033756 |
1 |
|
|
T26 |
75 |
|
T1 |
152 |
|
T11 |
49 |
| auto[1] |
auto[1] |
auto[0] |
1423031 |
1 |
|
|
T26 |
451 |
|
T1 |
108 |
|
T11 |
12 |
| auto[1] |
auto[1] |
auto[1] |
1033662 |
1 |
|
|
T26 |
159 |
|
T1 |
318 |
|
T11 |
45 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |