Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7065249 |
1 |
|
|
T24 |
212 |
|
T25 |
48 |
|
T26 |
813 |
| auto[1] |
4950223 |
1 |
|
|
T26 |
875 |
|
T1 |
833 |
|
T11 |
273 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9937351 |
1 |
|
|
T24 |
212 |
|
T25 |
48 |
|
T26 |
1519 |
| auto[1] |
2078121 |
1 |
|
|
T26 |
169 |
|
T1 |
581 |
|
T11 |
88 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7092154 |
1 |
|
|
T24 |
212 |
|
T25 |
48 |
|
T26 |
858 |
| auto[1] |
4923318 |
1 |
|
|
T26 |
830 |
|
T1 |
828 |
|
T11 |
205 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1419164 |
1 |
|
|
T26 |
316 |
|
T1 |
119 |
|
T11 |
30 |
| auto[1] |
auto[0] |
auto[1] |
1034670 |
1 |
|
|
T26 |
90 |
|
T1 |
298 |
|
T11 |
20 |
| auto[1] |
auto[1] |
auto[0] |
1426033 |
1 |
|
|
T26 |
345 |
|
T1 |
128 |
|
T11 |
87 |
| auto[1] |
auto[1] |
auto[1] |
1043451 |
1 |
|
|
T26 |
79 |
|
T1 |
283 |
|
T11 |
68 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |