Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7068723 |
1 |
|
|
T24 |
212 |
|
T25 |
48 |
|
T26 |
708 |
| auto[1] |
4946749 |
1 |
|
|
T26 |
980 |
|
T1 |
600 |
|
T11 |
207 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9945766 |
1 |
|
|
T24 |
212 |
|
T25 |
48 |
|
T26 |
1393 |
| auto[1] |
2069706 |
1 |
|
|
T26 |
295 |
|
T1 |
644 |
|
T11 |
110 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7115777 |
1 |
|
|
T24 |
212 |
|
T25 |
48 |
|
T26 |
703 |
| auto[1] |
4899695 |
1 |
|
|
T26 |
985 |
|
T1 |
859 |
|
T11 |
193 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1415284 |
1 |
|
|
T26 |
308 |
|
T1 |
128 |
|
T11 |
25 |
| auto[1] |
auto[0] |
auto[1] |
1034814 |
1 |
|
|
T26 |
142 |
|
T1 |
397 |
|
T11 |
67 |
| auto[1] |
auto[1] |
auto[0] |
1414705 |
1 |
|
|
T26 |
382 |
|
T1 |
87 |
|
T11 |
58 |
| auto[1] |
auto[1] |
auto[1] |
1034892 |
1 |
|
|
T26 |
153 |
|
T1 |
247 |
|
T11 |
43 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |