Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7083455 |
1 |
|
|
T24 |
212 |
|
T25 |
48 |
|
T26 |
894 |
| auto[1] |
4932017 |
1 |
|
|
T26 |
794 |
|
T1 |
799 |
|
T11 |
192 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11382897 |
1 |
|
|
T24 |
212 |
|
T25 |
48 |
|
T26 |
1657 |
| auto[1] |
632575 |
1 |
|
|
T26 |
31 |
|
T1 |
36 |
|
T11 |
11 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7082311 |
1 |
|
|
T24 |
212 |
|
T25 |
48 |
|
T26 |
818 |
| auto[1] |
4933161 |
1 |
|
|
T26 |
870 |
|
T1 |
826 |
|
T11 |
184 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2146116 |
1 |
|
|
T26 |
502 |
|
T1 |
393 |
|
T11 |
72 |
| auto[1] |
auto[0] |
auto[1] |
315474 |
1 |
|
|
T26 |
16 |
|
T1 |
21 |
|
T11 |
4 |
| auto[1] |
auto[1] |
auto[0] |
2154470 |
1 |
|
|
T26 |
337 |
|
T1 |
397 |
|
T11 |
101 |
| auto[1] |
auto[1] |
auto[1] |
317101 |
1 |
|
|
T26 |
15 |
|
T1 |
15 |
|
T11 |
7 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |