Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7112318 |
1 |
|
|
T24 |
212 |
|
T25 |
48 |
|
T26 |
640 |
| auto[1] |
4903154 |
1 |
|
|
T26 |
1048 |
|
T1 |
762 |
|
T11 |
196 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11382830 |
1 |
|
|
T24 |
212 |
|
T25 |
48 |
|
T26 |
1662 |
| auto[1] |
632642 |
1 |
|
|
T26 |
26 |
|
T1 |
30 |
|
T11 |
10 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7103473 |
1 |
|
|
T24 |
212 |
|
T25 |
48 |
|
T26 |
817 |
| auto[1] |
4911999 |
1 |
|
|
T26 |
871 |
|
T1 |
755 |
|
T11 |
181 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2151578 |
1 |
|
|
T26 |
379 |
|
T1 |
339 |
|
T11 |
88 |
| auto[1] |
auto[0] |
auto[1] |
318068 |
1 |
|
|
T26 |
15 |
|
T1 |
16 |
|
T11 |
4 |
| auto[1] |
auto[1] |
auto[0] |
2127779 |
1 |
|
|
T26 |
466 |
|
T1 |
386 |
|
T11 |
83 |
| auto[1] |
auto[1] |
auto[1] |
314574 |
1 |
|
|
T26 |
11 |
|
T1 |
14 |
|
T11 |
6 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |