Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7120116 |
1 |
|
|
T24 |
212 |
|
T25 |
48 |
|
T26 |
820 |
| auto[1] |
4895356 |
1 |
|
|
T26 |
868 |
|
T1 |
653 |
|
T11 |
171 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11385206 |
1 |
|
|
T24 |
212 |
|
T25 |
48 |
|
T26 |
1660 |
| auto[1] |
630266 |
1 |
|
|
T26 |
28 |
|
T1 |
27 |
|
T11 |
13 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7107258 |
1 |
|
|
T24 |
212 |
|
T25 |
48 |
|
T26 |
938 |
| auto[1] |
4908214 |
1 |
|
|
T26 |
750 |
|
T1 |
694 |
|
T11 |
208 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2160986 |
1 |
|
|
T26 |
384 |
|
T1 |
399 |
|
T11 |
100 |
| auto[1] |
auto[0] |
auto[1] |
318928 |
1 |
|
|
T26 |
12 |
|
T1 |
15 |
|
T11 |
7 |
| auto[1] |
auto[1] |
auto[0] |
2116962 |
1 |
|
|
T26 |
338 |
|
T1 |
268 |
|
T11 |
95 |
| auto[1] |
auto[1] |
auto[1] |
311338 |
1 |
|
|
T26 |
16 |
|
T1 |
12 |
|
T11 |
6 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |