Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7097769 |
1 |
|
|
T24 |
212 |
|
T25 |
48 |
|
T26 |
844 |
| auto[1] |
4917703 |
1 |
|
|
T26 |
844 |
|
T1 |
779 |
|
T11 |
203 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11388095 |
1 |
|
|
T24 |
212 |
|
T25 |
48 |
|
T26 |
1656 |
| auto[1] |
627377 |
1 |
|
|
T26 |
32 |
|
T1 |
28 |
|
T11 |
9 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7121337 |
1 |
|
|
T24 |
212 |
|
T25 |
48 |
|
T26 |
897 |
| auto[1] |
4894135 |
1 |
|
|
T26 |
791 |
|
T1 |
916 |
|
T11 |
184 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2137420 |
1 |
|
|
T26 |
366 |
|
T1 |
450 |
|
T11 |
69 |
| auto[1] |
auto[0] |
auto[1] |
314963 |
1 |
|
|
T26 |
14 |
|
T1 |
16 |
|
T11 |
3 |
| auto[1] |
auto[1] |
auto[0] |
2129338 |
1 |
|
|
T26 |
393 |
|
T1 |
438 |
|
T11 |
106 |
| auto[1] |
auto[1] |
auto[1] |
312414 |
1 |
|
|
T26 |
18 |
|
T1 |
12 |
|
T11 |
6 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |