Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7113944 |
1 |
|
|
T24 |
212 |
|
T25 |
48 |
|
T26 |
928 |
| auto[1] |
4901528 |
1 |
|
|
T26 |
760 |
|
T1 |
819 |
|
T11 |
186 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11381858 |
1 |
|
|
T24 |
212 |
|
T25 |
48 |
|
T26 |
1660 |
| auto[1] |
633614 |
1 |
|
|
T26 |
28 |
|
T1 |
34 |
|
T11 |
16 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7075426 |
1 |
|
|
T24 |
212 |
|
T25 |
48 |
|
T26 |
737 |
| auto[1] |
4940046 |
1 |
|
|
T26 |
951 |
|
T1 |
819 |
|
T11 |
197 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2163040 |
1 |
|
|
T26 |
508 |
|
T1 |
337 |
|
T11 |
88 |
| auto[1] |
auto[0] |
auto[1] |
318665 |
1 |
|
|
T26 |
13 |
|
T1 |
16 |
|
T11 |
8 |
| auto[1] |
auto[1] |
auto[0] |
2143392 |
1 |
|
|
T26 |
415 |
|
T1 |
448 |
|
T11 |
93 |
| auto[1] |
auto[1] |
auto[1] |
314949 |
1 |
|
|
T26 |
15 |
|
T1 |
18 |
|
T11 |
8 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |