Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7102756 |
1 |
|
|
T24 |
212 |
|
T25 |
48 |
|
T26 |
1177 |
| auto[1] |
4912716 |
1 |
|
|
T26 |
511 |
|
T1 |
830 |
|
T11 |
184 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11381539 |
1 |
|
|
T24 |
212 |
|
T25 |
48 |
|
T26 |
1654 |
| auto[1] |
633933 |
1 |
|
|
T26 |
34 |
|
T1 |
26 |
|
T11 |
10 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7079954 |
1 |
|
|
T24 |
212 |
|
T25 |
48 |
|
T26 |
789 |
| auto[1] |
4935518 |
1 |
|
|
T26 |
899 |
|
T1 |
808 |
|
T11 |
181 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2154557 |
1 |
|
|
T26 |
610 |
|
T1 |
342 |
|
T11 |
87 |
| auto[1] |
auto[0] |
auto[1] |
318537 |
1 |
|
|
T26 |
25 |
|
T1 |
16 |
|
T11 |
3 |
| auto[1] |
auto[1] |
auto[0] |
2147028 |
1 |
|
|
T26 |
255 |
|
T1 |
440 |
|
T11 |
84 |
| auto[1] |
auto[1] |
auto[1] |
315396 |
1 |
|
|
T26 |
9 |
|
T1 |
10 |
|
T11 |
7 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |