Tests
dashboard | hierarchy | modlist | groups | tests | asserts
Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.63 99.06 99.24 100.00 99.80 99.68 99.97


Total test records in report: 938
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html
T768 /workspace/coverage/cover_reg_top/4.gpio_tl_errors.759237261 Jul 01 10:26:00 AM PDT 24 Jul 01 10:26:02 AM PDT 24 180346008 ps
T769 /workspace/coverage/cover_reg_top/0.gpio_intr_test.1704684403 Jul 01 10:27:13 AM PDT 24 Jul 01 10:27:14 AM PDT 24 14401737 ps
T770 /workspace/coverage/cover_reg_top/2.gpio_csr_bit_bash.578777675 Jul 01 10:22:44 AM PDT 24 Jul 01 10:22:46 AM PDT 24 122066108 ps
T771 /workspace/coverage/cover_reg_top/48.gpio_intr_test.370664683 Jul 01 10:25:35 AM PDT 24 Jul 01 10:25:36 AM PDT 24 14435668 ps
T45 /workspace/coverage/cover_reg_top/7.gpio_tl_intg_err.3288487406 Jul 01 10:28:15 AM PDT 24 Jul 01 10:28:18 AM PDT 24 1182459050 ps
T772 /workspace/coverage/cover_reg_top/12.gpio_tl_intg_err.643640775 Jul 01 10:28:23 AM PDT 24 Jul 01 10:28:24 AM PDT 24 47621614 ps
T773 /workspace/coverage/cover_reg_top/0.gpio_tl_errors.1481887631 Jul 01 10:28:47 AM PDT 24 Jul 01 10:28:51 AM PDT 24 149904200 ps
T80 /workspace/coverage/cover_reg_top/0.gpio_csr_hw_reset.1210847516 Jul 01 10:29:02 AM PDT 24 Jul 01 10:29:04 AM PDT 24 17054025 ps
T97 /workspace/coverage/cover_reg_top/19.gpio_same_csr_outstanding.3950859710 Jul 01 10:29:25 AM PDT 24 Jul 01 10:29:27 AM PDT 24 60268717 ps
T774 /workspace/coverage/cover_reg_top/19.gpio_csr_mem_rw_with_rand_reset.2592851602 Jul 01 10:27:33 AM PDT 24 Jul 01 10:27:35 AM PDT 24 17769418 ps
T775 /workspace/coverage/cover_reg_top/5.gpio_csr_mem_rw_with_rand_reset.677177822 Jul 01 10:29:40 AM PDT 24 Jul 01 10:29:43 AM PDT 24 40476388 ps
T776 /workspace/coverage/cover_reg_top/18.gpio_tl_errors.248894546 Jul 01 10:26:43 AM PDT 24 Jul 01 10:26:45 AM PDT 24 121057960 ps
T777 /workspace/coverage/cover_reg_top/16.gpio_intr_test.3939858129 Jul 01 10:30:00 AM PDT 24 Jul 01 10:30:02 AM PDT 24 12803814 ps
T81 /workspace/coverage/cover_reg_top/4.gpio_same_csr_outstanding.3719242437 Jul 01 10:29:39 AM PDT 24 Jul 01 10:29:41 AM PDT 24 62228097 ps
T778 /workspace/coverage/cover_reg_top/15.gpio_intr_test.601382369 Jul 01 10:24:06 AM PDT 24 Jul 01 10:24:07 AM PDT 24 12410358 ps
T779 /workspace/coverage/cover_reg_top/10.gpio_csr_rw.979072543 Jul 01 10:27:57 AM PDT 24 Jul 01 10:27:59 AM PDT 24 75652691 ps
T780 /workspace/coverage/cover_reg_top/19.gpio_tl_errors.1324670541 Jul 01 10:28:08 AM PDT 24 Jul 01 10:28:10 AM PDT 24 47277717 ps
T48 /workspace/coverage/cover_reg_top/10.gpio_tl_intg_err.1849681711 Jul 01 10:24:39 AM PDT 24 Jul 01 10:24:41 AM PDT 24 144121361 ps
T781 /workspace/coverage/cover_reg_top/4.gpio_csr_mem_rw_with_rand_reset.4252330692 Jul 01 10:26:43 AM PDT 24 Jul 01 10:26:45 AM PDT 24 39888905 ps
T782 /workspace/coverage/cover_reg_top/5.gpio_csr_rw.3741878711 Jul 01 10:27:03 AM PDT 24 Jul 01 10:27:04 AM PDT 24 23449334 ps
T783 /workspace/coverage/cover_reg_top/47.gpio_intr_test.853714553 Jul 01 10:28:06 AM PDT 24 Jul 01 10:28:07 AM PDT 24 11514437 ps
T784 /workspace/coverage/cover_reg_top/39.gpio_intr_test.3772943537 Jul 01 10:29:44 AM PDT 24 Jul 01 10:29:46 AM PDT 24 11521505 ps
T785 /workspace/coverage/cover_reg_top/28.gpio_intr_test.1532936169 Jul 01 10:23:39 AM PDT 24 Jul 01 10:23:40 AM PDT 24 25720251 ps
T82 /workspace/coverage/cover_reg_top/0.gpio_csr_rw.1393291772 Jul 01 10:25:13 AM PDT 24 Jul 01 10:25:14 AM PDT 24 40351061 ps
T786 /workspace/coverage/cover_reg_top/11.gpio_csr_rw.1133359642 Jul 01 10:27:01 AM PDT 24 Jul 01 10:27:02 AM PDT 24 46300098 ps
T787 /workspace/coverage/cover_reg_top/13.gpio_tl_errors.2312966608 Jul 01 10:25:34 AM PDT 24 Jul 01 10:25:35 AM PDT 24 40051538 ps
T788 /workspace/coverage/cover_reg_top/7.gpio_tl_errors.948285645 Jul 01 10:29:44 AM PDT 24 Jul 01 10:29:47 AM PDT 24 26265029 ps
T83 /workspace/coverage/cover_reg_top/7.gpio_csr_rw.3989483598 Jul 01 10:25:39 AM PDT 24 Jul 01 10:25:40 AM PDT 24 19668514 ps
T789 /workspace/coverage/cover_reg_top/7.gpio_same_csr_outstanding.3791073762 Jul 01 10:29:38 AM PDT 24 Jul 01 10:29:40 AM PDT 24 139483728 ps
T790 /workspace/coverage/cover_reg_top/1.gpio_csr_bit_bash.2399620549 Jul 01 10:28:17 AM PDT 24 Jul 01 10:28:20 AM PDT 24 1116731492 ps
T84 /workspace/coverage/cover_reg_top/4.gpio_csr_bit_bash.836019690 Jul 01 10:27:04 AM PDT 24 Jul 01 10:27:06 AM PDT 24 212000236 ps
T791 /workspace/coverage/cover_reg_top/8.gpio_csr_mem_rw_with_rand_reset.1347982360 Jul 01 10:25:03 AM PDT 24 Jul 01 10:25:04 AM PDT 24 29397792 ps
T47 /workspace/coverage/cover_reg_top/4.gpio_tl_intg_err.3603891842 Jul 01 10:28:07 AM PDT 24 Jul 01 10:28:09 AM PDT 24 133238426 ps
T792 /workspace/coverage/cover_reg_top/14.gpio_csr_rw.3605242399 Jul 01 10:26:49 AM PDT 24 Jul 01 10:26:50 AM PDT 24 30156554 ps
T793 /workspace/coverage/cover_reg_top/14.gpio_same_csr_outstanding.1503979830 Jul 01 10:26:15 AM PDT 24 Jul 01 10:26:16 AM PDT 24 31245675 ps
T794 /workspace/coverage/cover_reg_top/24.gpio_intr_test.749211672 Jul 01 10:24:41 AM PDT 24 Jul 01 10:24:42 AM PDT 24 24365455 ps
T795 /workspace/coverage/cover_reg_top/1.gpio_tl_intg_err.637253002 Jul 01 10:23:15 AM PDT 24 Jul 01 10:23:17 AM PDT 24 90476551 ps
T796 /workspace/coverage/cover_reg_top/2.gpio_csr_hw_reset.281283179 Jul 01 10:23:04 AM PDT 24 Jul 01 10:23:05 AM PDT 24 15969992 ps
T797 /workspace/coverage/cover_reg_top/16.gpio_tl_errors.2514692207 Jul 01 10:25:30 AM PDT 24 Jul 01 10:25:33 AM PDT 24 493271885 ps
T798 /workspace/coverage/cover_reg_top/18.gpio_tl_intg_err.1700674136 Jul 01 10:25:10 AM PDT 24 Jul 01 10:25:12 AM PDT 24 130406596 ps
T85 /workspace/coverage/cover_reg_top/0.gpio_csr_aliasing.2230337057 Jul 01 10:24:58 AM PDT 24 Jul 01 10:24:59 AM PDT 24 16503335 ps
T799 /workspace/coverage/cover_reg_top/9.gpio_csr_mem_rw_with_rand_reset.195003392 Jul 01 10:25:53 AM PDT 24 Jul 01 10:25:54 AM PDT 24 59532966 ps
T800 /workspace/coverage/cover_reg_top/3.gpio_csr_mem_rw_with_rand_reset.3831030139 Jul 01 10:23:04 AM PDT 24 Jul 01 10:23:05 AM PDT 24 18274576 ps
T801 /workspace/coverage/cover_reg_top/14.gpio_csr_mem_rw_with_rand_reset.1381335266 Jul 01 10:30:18 AM PDT 24 Jul 01 10:30:20 AM PDT 24 25743623 ps
T802 /workspace/coverage/cover_reg_top/18.gpio_csr_rw.3392272912 Jul 01 10:24:39 AM PDT 24 Jul 01 10:24:40 AM PDT 24 123840981 ps
T803 /workspace/coverage/cover_reg_top/15.gpio_same_csr_outstanding.1956198422 Jul 01 10:29:39 AM PDT 24 Jul 01 10:29:40 AM PDT 24 109688538 ps
T804 /workspace/coverage/cover_reg_top/0.gpio_csr_bit_bash.2949227392 Jul 01 10:28:15 AM PDT 24 Jul 01 10:28:18 AM PDT 24 357498163 ps
T805 /workspace/coverage/cover_reg_top/2.gpio_same_csr_outstanding.2127604363 Jul 01 10:24:09 AM PDT 24 Jul 01 10:24:10 AM PDT 24 74839492 ps
T86 /workspace/coverage/cover_reg_top/4.gpio_csr_aliasing.3195003195 Jul 01 10:29:40 AM PDT 24 Jul 01 10:29:42 AM PDT 24 14632168 ps
T806 /workspace/coverage/cover_reg_top/18.gpio_intr_test.2316451836 Jul 01 10:26:26 AM PDT 24 Jul 01 10:26:26 AM PDT 24 16139773 ps
T807 /workspace/coverage/cover_reg_top/46.gpio_intr_test.427112153 Jul 01 10:25:09 AM PDT 24 Jul 01 10:25:11 AM PDT 24 60770524 ps
T808 /workspace/coverage/cover_reg_top/13.gpio_intr_test.3399679303 Jul 01 10:27:02 AM PDT 24 Jul 01 10:27:03 AM PDT 24 46003994 ps
T809 /workspace/coverage/cover_reg_top/12.gpio_same_csr_outstanding.2353312112 Jul 01 10:29:43 AM PDT 24 Jul 01 10:29:45 AM PDT 24 31771963 ps
T810 /workspace/coverage/cover_reg_top/25.gpio_intr_test.1859252387 Jul 01 10:26:43 AM PDT 24 Jul 01 10:26:44 AM PDT 24 54419121 ps
T811 /workspace/coverage/cover_reg_top/10.gpio_same_csr_outstanding.2233179736 Jul 01 10:26:18 AM PDT 24 Jul 01 10:26:19 AM PDT 24 51804273 ps
T812 /workspace/coverage/cover_reg_top/29.gpio_intr_test.492329958 Jul 01 10:24:39 AM PDT 24 Jul 01 10:24:40 AM PDT 24 71054627 ps
T87 /workspace/coverage/cover_reg_top/4.gpio_csr_rw.3109967031 Jul 01 10:29:23 AM PDT 24 Jul 01 10:29:24 AM PDT 24 35387154 ps
T88 /workspace/coverage/cover_reg_top/3.gpio_csr_bit_bash.739156073 Jul 01 10:28:02 AM PDT 24 Jul 01 10:28:05 AM PDT 24 68886257 ps
T813 /workspace/coverage/cover_reg_top/8.gpio_csr_rw.3503232263 Jul 01 10:25:35 AM PDT 24 Jul 01 10:25:36 AM PDT 24 48873893 ps
T814 /workspace/coverage/cover_reg_top/10.gpio_intr_test.1489305823 Jul 01 10:24:51 AM PDT 24 Jul 01 10:24:51 AM PDT 24 30492615 ps
T815 /workspace/coverage/cover_reg_top/6.gpio_same_csr_outstanding.738880316 Jul 01 10:30:12 AM PDT 24 Jul 01 10:30:13 AM PDT 24 24320913 ps
T816 /workspace/coverage/cover_reg_top/3.gpio_tl_errors.3932061860 Jul 01 10:29:33 AM PDT 24 Jul 01 10:29:36 AM PDT 24 57453764 ps
T90 /workspace/coverage/cover_reg_top/3.gpio_csr_aliasing.491080719 Jul 01 10:23:21 AM PDT 24 Jul 01 10:23:22 AM PDT 24 13065664 ps
T817 /workspace/coverage/cover_reg_top/3.gpio_same_csr_outstanding.805098401 Jul 01 10:24:08 AM PDT 24 Jul 01 10:24:09 AM PDT 24 43114155 ps
T89 /workspace/coverage/cover_reg_top/1.gpio_csr_aliasing.3719107206 Jul 01 10:28:02 AM PDT 24 Jul 01 10:28:04 AM PDT 24 41146996 ps
T818 /workspace/coverage/cover_reg_top/5.gpio_tl_errors.1640423264 Jul 01 10:24:26 AM PDT 24 Jul 01 10:24:28 AM PDT 24 1037846630 ps
T819 /workspace/coverage/cover_reg_top/16.gpio_csr_mem_rw_with_rand_reset.1553599159 Jul 01 10:24:39 AM PDT 24 Jul 01 10:24:41 AM PDT 24 115205529 ps
T820 /workspace/coverage/cover_reg_top/9.gpio_tl_intg_err.4269781808 Jul 01 10:24:58 AM PDT 24 Jul 01 10:24:59 AM PDT 24 409565829 ps
T821 /workspace/coverage/cover_reg_top/2.gpio_tl_intg_err.2935197051 Jul 01 10:27:49 AM PDT 24 Jul 01 10:27:51 AM PDT 24 116176980 ps
T822 /workspace/coverage/cover_reg_top/17.gpio_csr_mem_rw_with_rand_reset.1144290460 Jul 01 10:24:26 AM PDT 24 Jul 01 10:24:28 AM PDT 24 124288653 ps
T823 /workspace/coverage/cover_reg_top/4.gpio_csr_hw_reset.1819293823 Jul 01 10:28:57 AM PDT 24 Jul 01 10:28:58 AM PDT 24 22143927 ps
T824 /workspace/coverage/cover_reg_top/36.gpio_intr_test.4033383192 Jul 01 10:26:33 AM PDT 24 Jul 01 10:26:34 AM PDT 24 130983809 ps
T825 /workspace/coverage/cover_reg_top/43.gpio_intr_test.3686058303 Jul 01 10:24:47 AM PDT 24 Jul 01 10:24:47 AM PDT 24 14424633 ps
T826 /workspace/coverage/cover_reg_top/23.gpio_intr_test.468415667 Jul 01 10:28:08 AM PDT 24 Jul 01 10:28:09 AM PDT 24 23865101 ps
T827 /workspace/coverage/cover_reg_top/21.gpio_intr_test.558452499 Jul 01 10:28:08 AM PDT 24 Jul 01 10:28:09 AM PDT 24 15600805 ps
T828 /workspace/coverage/cover_reg_top/3.gpio_intr_test.535100560 Jul 01 10:23:28 AM PDT 24 Jul 01 10:23:29 AM PDT 24 16243594 ps
T42 /workspace/coverage/cover_reg_top/6.gpio_tl_intg_err.752884294 Jul 01 10:28:02 AM PDT 24 Jul 01 10:28:04 AM PDT 24 190877444 ps
T829 /workspace/coverage/cover_reg_top/2.gpio_tl_errors.4175245449 Jul 01 10:29:27 AM PDT 24 Jul 01 10:29:31 AM PDT 24 406543348 ps
T830 /workspace/coverage/cover_reg_top/17.gpio_tl_errors.2577614407 Jul 01 10:22:42 AM PDT 24 Jul 01 10:22:45 AM PDT 24 162175438 ps
T831 /workspace/coverage/cover_reg_top/5.gpio_same_csr_outstanding.1551319730 Jul 01 10:22:59 AM PDT 24 Jul 01 10:23:00 AM PDT 24 56481883 ps
T832 /workspace/coverage/cover_reg_top/3.gpio_csr_hw_reset.1831458632 Jul 01 10:23:49 AM PDT 24 Jul 01 10:23:50 AM PDT 24 25907695 ps
T833 /workspace/coverage/cover_reg_top/27.gpio_intr_test.3763768204 Jul 01 10:28:23 AM PDT 24 Jul 01 10:28:24 AM PDT 24 39125852 ps
T91 /workspace/coverage/cover_reg_top/1.gpio_csr_hw_reset.1297217279 Jul 01 10:28:00 AM PDT 24 Jul 01 10:28:02 AM PDT 24 14077958 ps
T834 /workspace/coverage/cover_reg_top/41.gpio_intr_test.2523765821 Jul 01 10:27:12 AM PDT 24 Jul 01 10:27:14 AM PDT 24 30146806 ps
T835 /workspace/coverage/cover_reg_top/6.gpio_intr_test.1370646836 Jul 01 10:29:31 AM PDT 24 Jul 01 10:29:32 AM PDT 24 22990129 ps
T836 /workspace/coverage/cover_reg_top/15.gpio_tl_errors.2894984101 Jul 01 10:25:42 AM PDT 24 Jul 01 10:25:45 AM PDT 24 332320038 ps
T837 /workspace/coverage/cover_reg_top/0.gpio_same_csr_outstanding.1613557775 Jul 01 10:29:08 AM PDT 24 Jul 01 10:29:10 AM PDT 24 67210965 ps
T838 /workspace/coverage/cover_reg_top/17.gpio_intr_test.446326764 Jul 01 10:26:20 AM PDT 24 Jul 01 10:26:21 AM PDT 24 19102722 ps
T839 /workspace/coverage/en_cdc_prims/3.gpio_smoke_no_pullup_pulldown_en_cdc_prim.403757703 Jul 01 10:38:44 AM PDT 24 Jul 01 10:38:47 AM PDT 24 302219515 ps
T840 /workspace/coverage/en_cdc_prims/16.gpio_smoke_en_cdc_prim.3432792879 Jul 01 10:39:04 AM PDT 24 Jul 01 10:39:08 AM PDT 24 83940217 ps
T841 /workspace/coverage/en_cdc_prims/37.gpio_smoke_en_cdc_prim.3695744146 Jul 01 10:38:47 AM PDT 24 Jul 01 10:38:49 AM PDT 24 38479403 ps
T842 /workspace/coverage/en_cdc_prims/44.gpio_smoke_en_cdc_prim.428375725 Jul 01 10:39:16 AM PDT 24 Jul 01 10:39:18 AM PDT 24 211188417 ps
T843 /workspace/coverage/en_cdc_prims/24.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1432385743 Jul 01 10:38:38 AM PDT 24 Jul 01 10:38:40 AM PDT 24 235010316 ps
T844 /workspace/coverage/en_cdc_prims/23.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3314012477 Jul 01 10:39:06 AM PDT 24 Jul 01 10:39:10 AM PDT 24 83386406 ps
T845 /workspace/coverage/en_cdc_prims/14.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2232637783 Jul 01 10:38:37 AM PDT 24 Jul 01 10:38:40 AM PDT 24 82565104 ps
T846 /workspace/coverage/en_cdc_prims/19.gpio_smoke_en_cdc_prim.302029245 Jul 01 10:38:50 AM PDT 24 Jul 01 10:38:52 AM PDT 24 39637001 ps
T847 /workspace/coverage/en_cdc_prims/37.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1159396689 Jul 01 10:38:57 AM PDT 24 Jul 01 10:38:59 AM PDT 24 153755196 ps
T848 /workspace/coverage/en_cdc_prims/13.gpio_smoke_en_cdc_prim.1567398720 Jul 01 10:38:51 AM PDT 24 Jul 01 10:38:54 AM PDT 24 103374170 ps
T849 /workspace/coverage/en_cdc_prims/17.gpio_smoke_no_pullup_pulldown_en_cdc_prim.388158229 Jul 01 10:39:27 AM PDT 24 Jul 01 10:39:29 AM PDT 24 157700669 ps
T850 /workspace/coverage/en_cdc_prims/38.gpio_smoke_no_pullup_pulldown_en_cdc_prim.19423232 Jul 01 10:38:56 AM PDT 24 Jul 01 10:38:57 AM PDT 24 89578464 ps
T851 /workspace/coverage/en_cdc_prims/6.gpio_smoke_en_cdc_prim.377413186 Jul 01 10:38:38 AM PDT 24 Jul 01 10:38:41 AM PDT 24 165758943 ps
T852 /workspace/coverage/en_cdc_prims/22.gpio_smoke_en_cdc_prim.3505223926 Jul 01 10:39:04 AM PDT 24 Jul 01 10:39:17 AM PDT 24 49601667 ps
T853 /workspace/coverage/en_cdc_prims/32.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4287763761 Jul 01 10:38:50 AM PDT 24 Jul 01 10:38:52 AM PDT 24 40351102 ps
T854 /workspace/coverage/en_cdc_prims/1.gpio_smoke_en_cdc_prim.120868962 Jul 01 10:38:45 AM PDT 24 Jul 01 10:38:47 AM PDT 24 100437090 ps
T855 /workspace/coverage/en_cdc_prims/33.gpio_smoke_en_cdc_prim.1110518258 Jul 01 10:39:34 AM PDT 24 Jul 01 10:39:38 AM PDT 24 280339684 ps
T856 /workspace/coverage/en_cdc_prims/12.gpio_smoke_en_cdc_prim.4221078239 Jul 01 10:38:35 AM PDT 24 Jul 01 10:38:37 AM PDT 24 23779560 ps
T857 /workspace/coverage/en_cdc_prims/36.gpio_smoke_en_cdc_prim.847837905 Jul 01 10:38:49 AM PDT 24 Jul 01 10:38:51 AM PDT 24 385038876 ps
T858 /workspace/coverage/en_cdc_prims/45.gpio_smoke_en_cdc_prim.1851697670 Jul 01 10:39:03 AM PDT 24 Jul 01 10:39:07 AM PDT 24 129449535 ps
T859 /workspace/coverage/en_cdc_prims/49.gpio_smoke_no_pullup_pulldown_en_cdc_prim.493248224 Jul 01 10:39:07 AM PDT 24 Jul 01 10:39:11 AM PDT 24 195898413 ps
T860 /workspace/coverage/en_cdc_prims/20.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2687467520 Jul 01 10:38:50 AM PDT 24 Jul 01 10:38:53 AM PDT 24 106173479 ps
T861 /workspace/coverage/en_cdc_prims/9.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1515056860 Jul 01 10:38:39 AM PDT 24 Jul 01 10:38:42 AM PDT 24 187351869 ps
T862 /workspace/coverage/en_cdc_prims/5.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1045430999 Jul 01 10:38:47 AM PDT 24 Jul 01 10:38:49 AM PDT 24 38492111 ps
T863 /workspace/coverage/en_cdc_prims/12.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2081983105 Jul 01 10:38:35 AM PDT 24 Jul 01 10:38:38 AM PDT 24 215831350 ps
T864 /workspace/coverage/en_cdc_prims/9.gpio_smoke_en_cdc_prim.4011956574 Jul 01 10:38:42 AM PDT 24 Jul 01 10:38:44 AM PDT 24 87486682 ps
T865 /workspace/coverage/en_cdc_prims/10.gpio_smoke_en_cdc_prim.1003809484 Jul 01 10:38:38 AM PDT 24 Jul 01 10:38:40 AM PDT 24 67285055 ps
T866 /workspace/coverage/en_cdc_prims/47.gpio_smoke_no_pullup_pulldown_en_cdc_prim.658205673 Jul 01 10:38:51 AM PDT 24 Jul 01 10:38:54 AM PDT 24 195176845 ps
T867 /workspace/coverage/en_cdc_prims/30.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3875166536 Jul 01 10:39:27 AM PDT 24 Jul 01 10:39:29 AM PDT 24 81692298 ps
T868 /workspace/coverage/en_cdc_prims/27.gpio_smoke_en_cdc_prim.2921497398 Jul 01 10:38:51 AM PDT 24 Jul 01 10:38:54 AM PDT 24 60372804 ps
T869 /workspace/coverage/en_cdc_prims/34.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2803982689 Jul 01 10:38:50 AM PDT 24 Jul 01 10:38:53 AM PDT 24 128951539 ps
T870 /workspace/coverage/en_cdc_prims/2.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1279939262 Jul 01 10:38:43 AM PDT 24 Jul 01 10:38:46 AM PDT 24 32662593 ps
T871 /workspace/coverage/en_cdc_prims/25.gpio_smoke_en_cdc_prim.3960191748 Jul 01 10:38:49 AM PDT 24 Jul 01 10:38:51 AM PDT 24 35849313 ps
T872 /workspace/coverage/en_cdc_prims/26.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1532360684 Jul 01 10:38:50 AM PDT 24 Jul 01 10:38:52 AM PDT 24 29676936 ps
T873 /workspace/coverage/en_cdc_prims/10.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3300615292 Jul 01 10:38:39 AM PDT 24 Jul 01 10:38:41 AM PDT 24 33322179 ps
T874 /workspace/coverage/en_cdc_prims/0.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1405253120 Jul 01 10:38:37 AM PDT 24 Jul 01 10:38:49 AM PDT 24 28581779 ps
T875 /workspace/coverage/en_cdc_prims/34.gpio_smoke_en_cdc_prim.2604407001 Jul 01 10:38:41 AM PDT 24 Jul 01 10:38:43 AM PDT 24 31130713 ps
T876 /workspace/coverage/en_cdc_prims/45.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2843083549 Jul 01 10:39:03 AM PDT 24 Jul 01 10:39:07 AM PDT 24 47470503 ps
T877 /workspace/coverage/en_cdc_prims/0.gpio_smoke_en_cdc_prim.1708639644 Jul 01 10:38:33 AM PDT 24 Jul 01 10:38:35 AM PDT 24 186069142 ps
T878 /workspace/coverage/en_cdc_prims/21.gpio_smoke_en_cdc_prim.1891477445 Jul 01 10:38:48 AM PDT 24 Jul 01 10:38:50 AM PDT 24 172012686 ps
T879 /workspace/coverage/en_cdc_prims/6.gpio_smoke_no_pullup_pulldown_en_cdc_prim.385866249 Jul 01 10:38:49 AM PDT 24 Jul 01 10:38:51 AM PDT 24 69118752 ps
T880 /workspace/coverage/en_cdc_prims/19.gpio_smoke_no_pullup_pulldown_en_cdc_prim.410731246 Jul 01 10:38:46 AM PDT 24 Jul 01 10:38:48 AM PDT 24 592243955 ps
T881 /workspace/coverage/en_cdc_prims/31.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1305787627 Jul 01 10:39:13 AM PDT 24 Jul 01 10:39:16 AM PDT 24 201670120 ps
T882 /workspace/coverage/en_cdc_prims/24.gpio_smoke_en_cdc_prim.1016824399 Jul 01 10:38:50 AM PDT 24 Jul 01 10:38:54 AM PDT 24 156077199 ps
T883 /workspace/coverage/en_cdc_prims/7.gpio_smoke_en_cdc_prim.1352483258 Jul 01 10:38:33 AM PDT 24 Jul 01 10:38:36 AM PDT 24 291014656 ps
T884 /workspace/coverage/en_cdc_prims/5.gpio_smoke_en_cdc_prim.1235534142 Jul 01 10:38:49 AM PDT 24 Jul 01 10:38:51 AM PDT 24 174562396 ps
T885 /workspace/coverage/en_cdc_prims/42.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3440841187 Jul 01 10:38:37 AM PDT 24 Jul 01 10:38:40 AM PDT 24 213703639 ps
T886 /workspace/coverage/en_cdc_prims/18.gpio_smoke_en_cdc_prim.99944813 Jul 01 10:39:20 AM PDT 24 Jul 01 10:39:23 AM PDT 24 41467902 ps
T887 /workspace/coverage/en_cdc_prims/42.gpio_smoke_en_cdc_prim.3042131827 Jul 01 10:38:41 AM PDT 24 Jul 01 10:38:43 AM PDT 24 499500625 ps
T888 /workspace/coverage/en_cdc_prims/2.gpio_smoke_en_cdc_prim.2164140573 Jul 01 10:38:42 AM PDT 24 Jul 01 10:38:44 AM PDT 24 267952133 ps
T889 /workspace/coverage/en_cdc_prims/29.gpio_smoke_no_pullup_pulldown_en_cdc_prim.693244878 Jul 01 10:38:39 AM PDT 24 Jul 01 10:38:42 AM PDT 24 201960194 ps
T890 /workspace/coverage/en_cdc_prims/40.gpio_smoke_no_pullup_pulldown_en_cdc_prim.625159454 Jul 01 10:39:01 AM PDT 24 Jul 01 10:39:03 AM PDT 24 57397721 ps
T891 /workspace/coverage/en_cdc_prims/8.gpio_smoke_en_cdc_prim.1578015929 Jul 01 10:38:52 AM PDT 24 Jul 01 10:38:55 AM PDT 24 165851234 ps
T892 /workspace/coverage/en_cdc_prims/14.gpio_smoke_en_cdc_prim.4103345514 Jul 01 10:38:36 AM PDT 24 Jul 01 10:38:38 AM PDT 24 82281746 ps
T893 /workspace/coverage/en_cdc_prims/36.gpio_smoke_no_pullup_pulldown_en_cdc_prim.466449167 Jul 01 10:38:53 AM PDT 24 Jul 01 10:38:56 AM PDT 24 255765591 ps
T894 /workspace/coverage/en_cdc_prims/41.gpio_smoke_en_cdc_prim.166991121 Jul 01 10:39:13 AM PDT 24 Jul 01 10:39:16 AM PDT 24 158637247 ps
T895 /workspace/coverage/en_cdc_prims/13.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3353063329 Jul 01 10:39:27 AM PDT 24 Jul 01 10:39:29 AM PDT 24 134888186 ps
T896 /workspace/coverage/en_cdc_prims/25.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1544260709 Jul 01 10:38:44 AM PDT 24 Jul 01 10:38:46 AM PDT 24 317952061 ps
T897 /workspace/coverage/en_cdc_prims/11.gpio_smoke_en_cdc_prim.3476479344 Jul 01 10:38:43 AM PDT 24 Jul 01 10:38:45 AM PDT 24 207954708 ps
T898 /workspace/coverage/en_cdc_prims/33.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3888140245 Jul 01 10:38:50 AM PDT 24 Jul 01 10:38:52 AM PDT 24 232035259 ps
T899 /workspace/coverage/en_cdc_prims/21.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2450588224 Jul 01 10:39:18 AM PDT 24 Jul 01 10:39:21 AM PDT 24 214824738 ps
T900 /workspace/coverage/en_cdc_prims/20.gpio_smoke_en_cdc_prim.1634008785 Jul 01 10:38:53 AM PDT 24 Jul 01 10:38:55 AM PDT 24 37747714 ps
T901 /workspace/coverage/en_cdc_prims/48.gpio_smoke_no_pullup_pulldown_en_cdc_prim.376186847 Jul 01 10:38:59 AM PDT 24 Jul 01 10:39:01 AM PDT 24 48459983 ps
T902 /workspace/coverage/en_cdc_prims/4.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3807581628 Jul 01 10:39:34 AM PDT 24 Jul 01 10:39:38 AM PDT 24 96304305 ps
T903 /workspace/coverage/en_cdc_prims/41.gpio_smoke_no_pullup_pulldown_en_cdc_prim.554254843 Jul 01 10:39:00 AM PDT 24 Jul 01 10:39:01 AM PDT 24 196233070 ps
T904 /workspace/coverage/en_cdc_prims/30.gpio_smoke_en_cdc_prim.1609493341 Jul 01 10:38:53 AM PDT 24 Jul 01 10:38:55 AM PDT 24 34368325 ps
T905 /workspace/coverage/en_cdc_prims/16.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2161857623 Jul 01 10:38:45 AM PDT 24 Jul 01 10:38:48 AM PDT 24 289021825 ps
T906 /workspace/coverage/en_cdc_prims/26.gpio_smoke_en_cdc_prim.3325599315 Jul 01 10:39:12 AM PDT 24 Jul 01 10:39:14 AM PDT 24 34944210 ps
T907 /workspace/coverage/en_cdc_prims/29.gpio_smoke_en_cdc_prim.4175211167 Jul 01 10:38:53 AM PDT 24 Jul 01 10:38:55 AM PDT 24 51019296 ps
T908 /workspace/coverage/en_cdc_prims/8.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1915176373 Jul 01 10:38:52 AM PDT 24 Jul 01 10:38:54 AM PDT 24 29990772 ps
T909 /workspace/coverage/en_cdc_prims/40.gpio_smoke_en_cdc_prim.365837587 Jul 01 10:38:59 AM PDT 24 Jul 01 10:39:01 AM PDT 24 72395469 ps
T910 /workspace/coverage/en_cdc_prims/47.gpio_smoke_en_cdc_prim.1664428390 Jul 01 10:38:58 AM PDT 24 Jul 01 10:38:59 AM PDT 24 73687956 ps
T911 /workspace/coverage/en_cdc_prims/48.gpio_smoke_en_cdc_prim.417710457 Jul 01 10:38:53 AM PDT 24 Jul 01 10:38:55 AM PDT 24 66921959 ps
T912 /workspace/coverage/en_cdc_prims/44.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1095382681 Jul 01 10:39:32 AM PDT 24 Jul 01 10:39:42 AM PDT 24 31323507 ps
T913 /workspace/coverage/en_cdc_prims/28.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3671934525 Jul 01 10:39:37 AM PDT 24 Jul 01 10:39:42 AM PDT 24 114091392 ps
T914 /workspace/coverage/en_cdc_prims/46.gpio_smoke_en_cdc_prim.556406705 Jul 01 10:39:32 AM PDT 24 Jul 01 10:39:35 AM PDT 24 416944900 ps
T915 /workspace/coverage/en_cdc_prims/15.gpio_smoke_en_cdc_prim.2732373764 Jul 01 10:39:32 AM PDT 24 Jul 01 10:39:35 AM PDT 24 36018867 ps
T916 /workspace/coverage/en_cdc_prims/11.gpio_smoke_no_pullup_pulldown_en_cdc_prim.422629495 Jul 01 10:39:27 AM PDT 24 Jul 01 10:39:29 AM PDT 24 493797619 ps
T917 /workspace/coverage/en_cdc_prims/27.gpio_smoke_no_pullup_pulldown_en_cdc_prim.368974648 Jul 01 10:39:18 AM PDT 24 Jul 01 10:39:19 AM PDT 24 210668408 ps
T918 /workspace/coverage/en_cdc_prims/46.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3203262244 Jul 01 10:38:51 AM PDT 24 Jul 01 10:38:54 AM PDT 24 97227955 ps
T919 /workspace/coverage/en_cdc_prims/7.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1304734617 Jul 01 10:39:27 AM PDT 24 Jul 01 10:39:29 AM PDT 24 1100908306 ps
T920 /workspace/coverage/en_cdc_prims/28.gpio_smoke_en_cdc_prim.1371436147 Jul 01 10:39:29 AM PDT 24 Jul 01 10:39:31 AM PDT 24 62042126 ps
T921 /workspace/coverage/en_cdc_prims/35.gpio_smoke_en_cdc_prim.3002796428 Jul 01 10:38:43 AM PDT 24 Jul 01 10:38:45 AM PDT 24 203602691 ps
T922 /workspace/coverage/en_cdc_prims/43.gpio_smoke_en_cdc_prim.2477664084 Jul 01 10:38:43 AM PDT 24 Jul 01 10:38:46 AM PDT 24 123673596 ps
T923 /workspace/coverage/en_cdc_prims/15.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4086776523 Jul 01 10:38:47 AM PDT 24 Jul 01 10:38:49 AM PDT 24 384274344 ps
T924 /workspace/coverage/en_cdc_prims/35.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1872890338 Jul 01 10:38:53 AM PDT 24 Jul 01 10:38:55 AM PDT 24 53075747 ps
T925 /workspace/coverage/en_cdc_prims/31.gpio_smoke_en_cdc_prim.1067825675 Jul 01 10:38:43 AM PDT 24 Jul 01 10:38:45 AM PDT 24 75103229 ps
T926 /workspace/coverage/en_cdc_prims/18.gpio_smoke_no_pullup_pulldown_en_cdc_prim.278435231 Jul 01 10:38:50 AM PDT 24 Jul 01 10:38:53 AM PDT 24 66865569 ps
T927 /workspace/coverage/en_cdc_prims/1.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2640907360 Jul 01 10:38:43 AM PDT 24 Jul 01 10:38:46 AM PDT 24 192312628 ps
T928 /workspace/coverage/en_cdc_prims/39.gpio_smoke_en_cdc_prim.1235849738 Jul 01 10:39:03 AM PDT 24 Jul 01 10:39:07 AM PDT 24 42100746 ps
T929 /workspace/coverage/en_cdc_prims/3.gpio_smoke_en_cdc_prim.2532658763 Jul 01 10:38:32 AM PDT 24 Jul 01 10:38:34 AM PDT 24 283657235 ps
T930 /workspace/coverage/en_cdc_prims/4.gpio_smoke_en_cdc_prim.2892450690 Jul 01 10:38:49 AM PDT 24 Jul 01 10:38:52 AM PDT 24 118597351 ps
T931 /workspace/coverage/en_cdc_prims/49.gpio_smoke_en_cdc_prim.4271417044 Jul 01 10:38:59 AM PDT 24 Jul 01 10:39:00 AM PDT 24 152880656 ps
T932 /workspace/coverage/en_cdc_prims/22.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3266451804 Jul 01 10:38:53 AM PDT 24 Jul 01 10:38:55 AM PDT 24 43158811 ps
T933 /workspace/coverage/en_cdc_prims/32.gpio_smoke_en_cdc_prim.304159069 Jul 01 10:39:07 AM PDT 24 Jul 01 10:39:10 AM PDT 24 27989595 ps
T934 /workspace/coverage/en_cdc_prims/39.gpio_smoke_no_pullup_pulldown_en_cdc_prim.627675100 Jul 01 10:38:40 AM PDT 24 Jul 01 10:38:42 AM PDT 24 67417808 ps
T935 /workspace/coverage/en_cdc_prims/17.gpio_smoke_en_cdc_prim.92347386 Jul 01 10:38:52 AM PDT 24 Jul 01 10:38:54 AM PDT 24 34934773 ps
T936 /workspace/coverage/en_cdc_prims/23.gpio_smoke_en_cdc_prim.3767716850 Jul 01 10:38:43 AM PDT 24 Jul 01 10:38:46 AM PDT 24 167992295 ps
T937 /workspace/coverage/en_cdc_prims/38.gpio_smoke_en_cdc_prim.1685104036 Jul 01 10:39:03 AM PDT 24 Jul 01 10:39:07 AM PDT 24 41915515 ps
T938 /workspace/coverage/en_cdc_prims/43.gpio_smoke_no_pullup_pulldown_en_cdc_prim.338427648 Jul 01 10:39:07 AM PDT 24 Jul 01 10:39:11 AM PDT 24 67368137 ps

Test location /workspace/coverage/default/34.gpio_random_long_reg_writes_reg_reads.1827869382
Short name T26
Test name
Test status
Simulation time 174659032 ps
CPU time 4.13 seconds
Started Jul 01 10:47:28 AM PDT 24
Finished Jul 01 10:47:35 AM PDT 24
Peak memory 198628 kb
Host smart-6426fa45-6365-4db3-b0c6-091bab7fd6e9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1827869382 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_ra
ndom_long_reg_writes_reg_reads.1827869382
Directory /workspace/34.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/16.gpio_intr_with_filter_rand_intr_event.1870021341
Short name T15
Test name
Test status
Simulation time 92381403 ps
CPU time 3.66 seconds
Started Jul 01 10:46:32 AM PDT 24
Finished Jul 01 10:46:36 AM PDT 24
Peak memory 198776 kb
Host smart-0cba56b1-f501-4ddc-bd63-1216202c4b12
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1870021341 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 16.gpio_intr_with_filter_rand_intr_event.1870021341
Directory /workspace/16.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/46.gpio_stress_all_with_rand_reset.3775733111
Short name T27
Test name
Test status
Simulation time 14120962500 ps
CPU time 433.13 seconds
Started Jul 01 10:47:48 AM PDT 24
Finished Jul 01 10:55:01 AM PDT 24
Peak memory 198860 kb
Host smart-f5483b4f-8bc6-4eb0-b3fd-152dce51d4fc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3775733111 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_stress_all_with_rand_reset.3775733111
Directory /workspace/46.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_tl_intg_err.3227779497
Short name T33
Test name
Test status
Simulation time 344421176 ps
CPU time 1.19 seconds
Started Jul 01 10:28:15 AM PDT 24
Finished Jul 01 10:28:18 AM PDT 24
Peak memory 196832 kb
Host smart-63086612-b2e1-48cc-bab8-023fc76d2fbe
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3227779497 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 16.gpio_tl_intg_err.3227779497
Directory /workspace/16.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_csr_hw_reset.1210847516
Short name T80
Test name
Test status
Simulation time 17054025 ps
CPU time 0.59 seconds
Started Jul 01 10:29:02 AM PDT 24
Finished Jul 01 10:29:04 AM PDT 24
Peak memory 195616 kb
Host smart-fb546b72-65be-4ee1-b1ce-95e1326fffe4
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1210847516 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_csr_hw_reset.1210847516
Directory /workspace/0.gpio_csr_hw_reset/latest

Test location /workspace/coverage/default/21.gpio_random_long_reg_writes_reg_reads.58715981
Short name T4
Test name
Test status
Simulation time 1686965003 ps
CPU time 2.16 seconds
Started Jul 01 10:46:52 AM PDT 24
Finished Jul 01 10:46:55 AM PDT 24
Peak memory 198528 kb
Host smart-a3d6265b-7036-468d-8870-0f42dc256431
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58715981 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_w
rites_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_rand
om_long_reg_writes_reg_reads.58715981
Directory /workspace/21.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/0.gpio_alert_test.2655870889
Short name T198
Test name
Test status
Simulation time 15205422 ps
CPU time 0.6 seconds
Started Jul 01 10:46:11 AM PDT 24
Finished Jul 01 10:46:12 AM PDT 24
Peak memory 194640 kb
Host smart-30439d7c-90fe-41a6-b836-ba3ee2d55644
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2655870889 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_alert_test.2655870889
Directory /workspace/0.gpio_alert_test/latest

Test location /workspace/coverage/default/0.gpio_sec_cm.24261432
Short name T36
Test name
Test status
Simulation time 65565502 ps
CPU time 0.85 seconds
Started Jul 01 10:46:29 AM PDT 24
Finished Jul 01 10:46:30 AM PDT 24
Peak memory 214120 kb
Host smart-805d4396-80a3-4e4b-95f2-13709b692d4d
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24261432 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_sec_cm.24261432
Directory /workspace/0.gpio_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_same_csr_outstanding.2346117767
Short name T73
Test name
Test status
Simulation time 298513414 ps
CPU time 0.73 seconds
Started Jul 01 10:23:45 AM PDT 24
Finished Jul 01 10:23:46 AM PDT 24
Peak memory 196624 kb
Host smart-78d7fa9f-512f-435f-8461-9b91f3826bec
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2346117767 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 1.gpio_same_csr_outstanding.2346117767
Directory /workspace/1.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_tl_intg_err.1243318806
Short name T40
Test name
Test status
Simulation time 485195359 ps
CPU time 1.4 seconds
Started Jul 01 10:29:45 AM PDT 24
Finished Jul 01 10:29:48 AM PDT 24
Peak memory 198484 kb
Host smart-34717f41-1833-452b-9218-1ff360997df9
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1243318806 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 14.gpio_tl_intg_err.1243318806
Directory /workspace/14.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_tl_intg_err.1859769853
Short name T31
Test name
Test status
Simulation time 71313930 ps
CPU time 1.14 seconds
Started Jul 01 10:28:02 AM PDT 24
Finished Jul 01 10:28:04 AM PDT 24
Peak memory 198088 kb
Host smart-498290bb-0333-4afa-9d8e-b9b7340f1f83
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1859769853 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 13.gpio_tl_intg_err.1859769853
Directory /workspace/13.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_csr_aliasing.2230337057
Short name T85
Test name
Test status
Simulation time 16503335 ps
CPU time 0.83 seconds
Started Jul 01 10:24:58 AM PDT 24
Finished Jul 01 10:24:59 AM PDT 24
Peak memory 197024 kb
Host smart-1032ee4d-cbfd-4b71-b6ea-02373ceab6e3
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2230337057 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM
_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
0.gpio_csr_aliasing.2230337057
Directory /workspace/0.gpio_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_csr_bit_bash.2949227392
Short name T804
Test name
Test status
Simulation time 357498163 ps
CPU time 2.31 seconds
Started Jul 01 10:28:15 AM PDT 24
Finished Jul 01 10:28:18 AM PDT 24
Peak memory 198440 kb
Host smart-a06ff89a-85c5-4c83-b6f0-26c43915dda3
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2949227392 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_csr_bit_bash.2949227392
Directory /workspace/0.gpio_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_csr_mem_rw_with_rand_reset.1695879623
Short name T719
Test name
Test status
Simulation time 29564547 ps
CPU time 1.39 seconds
Started Jul 01 10:29:54 AM PDT 24
Finished Jul 01 10:29:56 AM PDT 24
Peak memory 198516 kb
Host smart-c284330a-8555-4472-81b8-3d5c9a702acb
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1695879623 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_csr_mem_rw_with_rand_reset.1695879623
Directory /workspace/0.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_csr_rw.1393291772
Short name T82
Test name
Test status
Simulation time 40351061 ps
CPU time 0.61 seconds
Started Jul 01 10:25:13 AM PDT 24
Finished Jul 01 10:25:14 AM PDT 24
Peak memory 195140 kb
Host smart-5fcf0070-32a7-4a6c-8925-fa896924efb2
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1393291772 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio
_csr_rw.1393291772
Directory /workspace/0.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_intr_test.1704684403
Short name T769
Test name
Test status
Simulation time 14401737 ps
CPU time 0.59 seconds
Started Jul 01 10:27:13 AM PDT 24
Finished Jul 01 10:27:14 AM PDT 24
Peak memory 194212 kb
Host smart-f2f9f46c-ad35-4018-9776-f8bc1d19b798
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1704684403 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_intr_test.1704684403
Directory /workspace/0.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_same_csr_outstanding.1613557775
Short name T837
Test name
Test status
Simulation time 67210965 ps
CPU time 0.81 seconds
Started Jul 01 10:29:08 AM PDT 24
Finished Jul 01 10:29:10 AM PDT 24
Peak memory 197540 kb
Host smart-8fd4e2f0-602e-4148-a598-cb512bc0c702
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1613557775 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 0.gpio_same_csr_outstanding.1613557775
Directory /workspace/0.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_tl_errors.1481887631
Short name T773
Test name
Test status
Simulation time 149904200 ps
CPU time 2.5 seconds
Started Jul 01 10:28:47 AM PDT 24
Finished Jul 01 10:28:51 AM PDT 24
Peak memory 197716 kb
Host smart-a52e0399-acd3-452f-a631-68fdf6287344
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1481887631 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_tl_errors.1481887631
Directory /workspace/0.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_tl_intg_err.1572043704
Short name T32
Test name
Test status
Simulation time 144867447 ps
CPU time 1.41 seconds
Started Jul 01 10:28:17 AM PDT 24
Finished Jul 01 10:28:20 AM PDT 24
Peak memory 198316 kb
Host smart-5d4b7e74-dfc3-44e4-a4d9-1422617b8542
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1572043704 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 0.gpio_tl_intg_err.1572043704
Directory /workspace/0.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_csr_aliasing.3719107206
Short name T89
Test name
Test status
Simulation time 41146996 ps
CPU time 0.92 seconds
Started Jul 01 10:28:02 AM PDT 24
Finished Jul 01 10:28:04 AM PDT 24
Peak memory 196456 kb
Host smart-4442035f-bf08-433d-9b6d-cc9c10a231db
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3719107206 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM
_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
1.gpio_csr_aliasing.3719107206
Directory /workspace/1.gpio_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_csr_bit_bash.2399620549
Short name T790
Test name
Test status
Simulation time 1116731492 ps
CPU time 2.34 seconds
Started Jul 01 10:28:17 AM PDT 24
Finished Jul 01 10:28:20 AM PDT 24
Peak memory 198308 kb
Host smart-816c6122-1efa-4067-a46a-969ec9b8afc1
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2399620549 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_csr_bit_bash.2399620549
Directory /workspace/1.gpio_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_csr_hw_reset.1297217279
Short name T91
Test name
Test status
Simulation time 14077958 ps
CPU time 0.7 seconds
Started Jul 01 10:28:00 AM PDT 24
Finished Jul 01 10:28:02 AM PDT 24
Peak memory 194672 kb
Host smart-88a6d1e7-c29e-4158-b414-63339c96085c
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1297217279 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_csr_hw_reset.1297217279
Directory /workspace/1.gpio_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_csr_mem_rw_with_rand_reset.2858628841
Short name T749
Test name
Test status
Simulation time 135338267 ps
CPU time 1 seconds
Started Jul 01 10:23:04 AM PDT 24
Finished Jul 01 10:23:05 AM PDT 24
Peak memory 198292 kb
Host smart-b4bc3ea2-21d3-4565-9d02-7c171b9ae30d
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2858628841 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_csr_mem_rw_with_rand_reset.2858628841
Directory /workspace/1.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_csr_rw.4079692100
Short name T75
Test name
Test status
Simulation time 37396802 ps
CPU time 0.65 seconds
Started Jul 01 10:28:15 AM PDT 24
Finished Jul 01 10:28:16 AM PDT 24
Peak memory 195776 kb
Host smart-d5f51586-b357-4f09-ba0f-4b1efcdb78cc
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4079692100 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio
_csr_rw.4079692100
Directory /workspace/1.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_intr_test.1203024283
Short name T744
Test name
Test status
Simulation time 137049981 ps
CPU time 0.61 seconds
Started Jul 01 10:28:17 AM PDT 24
Finished Jul 01 10:28:19 AM PDT 24
Peak memory 194204 kb
Host smart-c8b5b4a3-0531-42f2-832b-5a6af5772fff
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1203024283 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_intr_test.1203024283
Directory /workspace/1.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_tl_errors.824584338
Short name T723
Test name
Test status
Simulation time 31707455 ps
CPU time 1.95 seconds
Started Jul 01 10:22:44 AM PDT 24
Finished Jul 01 10:22:46 AM PDT 24
Peak memory 198484 kb
Host smart-4a6c72fd-91d3-4777-a8c2-284e494a8a9e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=824584338 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_tl_errors.824584338
Directory /workspace/1.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_tl_intg_err.637253002
Short name T795
Test name
Test status
Simulation time 90476551 ps
CPU time 1.15 seconds
Started Jul 01 10:23:15 AM PDT 24
Finished Jul 01 10:23:17 AM PDT 24
Peak memory 197900 kb
Host smart-fe987794-c409-4824-9ea5-e1945747db46
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=637253002 -assert nopostproc +UVM_TESTNAME=gpio_base_test +U
VM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 1.gpio_tl_intg_err.637253002
Directory /workspace/1.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_csr_mem_rw_with_rand_reset.48305200
Short name T717
Test name
Test status
Simulation time 21828187 ps
CPU time 0.72 seconds
Started Jul 01 10:24:32 AM PDT 24
Finished Jul 01 10:24:34 AM PDT 24
Peak memory 197624 kb
Host smart-695f3e82-92e8-4a56-82f5-6f89490a5971
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48305200 -assert
nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/
cover_reg_top.vdb -cm_log /dev/null -cm_name 10.gpio_csr_mem_rw_with_rand_reset.48305200
Directory /workspace/10.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_csr_rw.979072543
Short name T779
Test name
Test status
Simulation time 75652691 ps
CPU time 0.65 seconds
Started Jul 01 10:27:57 AM PDT 24
Finished Jul 01 10:27:59 AM PDT 24
Peak memory 194904 kb
Host smart-9b24eccd-c887-40d5-8163-956393015dca
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=979072543 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.gpio
_csr_rw.979072543
Directory /workspace/10.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_intr_test.1489305823
Short name T814
Test name
Test status
Simulation time 30492615 ps
CPU time 0.6 seconds
Started Jul 01 10:24:51 AM PDT 24
Finished Jul 01 10:24:51 AM PDT 24
Peak memory 194284 kb
Host smart-68f8428d-9151-43b0-bb37-0c9d232de821
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1489305823 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.gpio_intr_test.1489305823
Directory /workspace/10.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_same_csr_outstanding.2233179736
Short name T811
Test name
Test status
Simulation time 51804273 ps
CPU time 0.73 seconds
Started Jul 01 10:26:18 AM PDT 24
Finished Jul 01 10:26:19 AM PDT 24
Peak memory 195576 kb
Host smart-ea41a133-8d39-41d9-adb8-af368514a38d
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2233179736 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 10.gpio_same_csr_outstanding.2233179736
Directory /workspace/10.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_tl_errors.2502521692
Short name T767
Test name
Test status
Simulation time 80082395 ps
CPU time 1.62 seconds
Started Jul 01 10:26:19 AM PDT 24
Finished Jul 01 10:26:21 AM PDT 24
Peak memory 198720 kb
Host smart-2bb4dea8-c853-4a96-8cf9-3b8c009179d8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2502521692 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.gpio_tl_errors.2502521692
Directory /workspace/10.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_tl_intg_err.1849681711
Short name T48
Test name
Test status
Simulation time 144121361 ps
CPU time 1.36 seconds
Started Jul 01 10:24:39 AM PDT 24
Finished Jul 01 10:24:41 AM PDT 24
Peak memory 198772 kb
Host smart-64542fbd-9886-400a-a8bb-38c0226d4879
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1849681711 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 10.gpio_tl_intg_err.1849681711
Directory /workspace/10.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_csr_mem_rw_with_rand_reset.2289761480
Short name T722
Test name
Test status
Simulation time 121507426 ps
CPU time 1.6 seconds
Started Jul 01 10:26:34 AM PDT 24
Finished Jul 01 10:26:36 AM PDT 24
Peak memory 198596 kb
Host smart-a0309903-edb6-413a-9226-060844e7b694
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2289761480 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.gpio_csr_mem_rw_with_rand_reset.2289761480
Directory /workspace/11.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_csr_rw.1133359642
Short name T786
Test name
Test status
Simulation time 46300098 ps
CPU time 0.69 seconds
Started Jul 01 10:27:01 AM PDT 24
Finished Jul 01 10:27:02 AM PDT 24
Peak memory 195752 kb
Host smart-1c6291aa-536f-4e2b-b609-31a5dba5bdb1
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1133359642 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.gpi
o_csr_rw.1133359642
Directory /workspace/11.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_intr_test.1528332286
Short name T730
Test name
Test status
Simulation time 14630585 ps
CPU time 0.57 seconds
Started Jul 01 10:23:36 AM PDT 24
Finished Jul 01 10:23:37 AM PDT 24
Peak memory 195016 kb
Host smart-c1a1cc2d-e82f-4884-b66c-a2f3dcd8ad06
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1528332286 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.gpio_intr_test.1528332286
Directory /workspace/11.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_same_csr_outstanding.1664212595
Short name T93
Test name
Test status
Simulation time 34276136 ps
CPU time 0.86 seconds
Started Jul 01 10:29:24 AM PDT 24
Finished Jul 01 10:29:27 AM PDT 24
Peak memory 196284 kb
Host smart-d95c4e79-c14e-4419-b64e-4efb09005438
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1664212595 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 11.gpio_same_csr_outstanding.1664212595
Directory /workspace/11.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_tl_errors.1156114507
Short name T747
Test name
Test status
Simulation time 50272965 ps
CPU time 2.01 seconds
Started Jul 01 10:28:07 AM PDT 24
Finished Jul 01 10:28:10 AM PDT 24
Peak memory 198256 kb
Host smart-490fc8f2-6c79-4b65-a912-c582757541fc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1156114507 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.gpio_tl_errors.1156114507
Directory /workspace/11.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_tl_intg_err.2452312543
Short name T41
Test name
Test status
Simulation time 51339663 ps
CPU time 0.84 seconds
Started Jul 01 10:29:39 AM PDT 24
Finished Jul 01 10:29:41 AM PDT 24
Peak memory 197968 kb
Host smart-5330dedb-27b5-44b4-8358-9d3435314db1
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2452312543 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 11.gpio_tl_intg_err.2452312543
Directory /workspace/11.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_csr_mem_rw_with_rand_reset.1480111673
Short name T740
Test name
Test status
Simulation time 88471995 ps
CPU time 0.91 seconds
Started Jul 01 10:25:11 AM PDT 24
Finished Jul 01 10:25:12 AM PDT 24
Peak memory 198428 kb
Host smart-8e375ccf-3b32-47a9-b46e-a8ab2e6d7e53
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1480111673 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.gpio_csr_mem_rw_with_rand_reset.1480111673
Directory /workspace/12.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_csr_rw.1669517799
Short name T761
Test name
Test status
Simulation time 18533836 ps
CPU time 0.59 seconds
Started Jul 01 10:29:26 AM PDT 24
Finished Jul 01 10:29:28 AM PDT 24
Peak memory 194256 kb
Host smart-e54a122d-6b92-4104-bc3f-0233d05fce86
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1669517799 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.gpi
o_csr_rw.1669517799
Directory /workspace/12.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_intr_test.148170344
Short name T735
Test name
Test status
Simulation time 15097985 ps
CPU time 0.57 seconds
Started Jul 01 10:29:27 AM PDT 24
Finished Jul 01 10:29:29 AM PDT 24
Peak memory 194628 kb
Host smart-bc26af7d-8dfa-4656-9cb5-50e0d82df98b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=148170344 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.gpio_intr_test.148170344
Directory /workspace/12.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_same_csr_outstanding.2353312112
Short name T809
Test name
Test status
Simulation time 31771963 ps
CPU time 0.75 seconds
Started Jul 01 10:29:43 AM PDT 24
Finished Jul 01 10:29:45 AM PDT 24
Peak memory 197592 kb
Host smart-bc7a14f4-8a5a-43fb-b0a5-4de6fb6c690b
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2353312112 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 12.gpio_same_csr_outstanding.2353312112
Directory /workspace/12.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_tl_errors.1460547010
Short name T764
Test name
Test status
Simulation time 426693897 ps
CPU time 2.43 seconds
Started Jul 01 10:23:20 AM PDT 24
Finished Jul 01 10:23:22 AM PDT 24
Peak memory 198480 kb
Host smart-4507ba13-567e-43c2-928d-e3f8ff928801
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1460547010 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.gpio_tl_errors.1460547010
Directory /workspace/12.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_tl_intg_err.643640775
Short name T772
Test name
Test status
Simulation time 47621614 ps
CPU time 0.85 seconds
Started Jul 01 10:28:23 AM PDT 24
Finished Jul 01 10:28:24 AM PDT 24
Peak memory 198052 kb
Host smart-f5732d9f-4a74-4c46-af20-af251d052b84
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=643640775 -assert nopostproc +UVM_TESTNAME=gpio_base_test +U
VM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 12.gpio_tl_intg_err.643640775
Directory /workspace/12.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_csr_mem_rw_with_rand_reset.886078365
Short name T724
Test name
Test status
Simulation time 91002747 ps
CPU time 0.84 seconds
Started Jul 01 10:25:37 AM PDT 24
Finished Jul 01 10:25:38 AM PDT 24
Peak memory 198344 kb
Host smart-c6e874e8-1212-4ac4-ae9c-8622bf551432
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=886078365 -asser
t nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.gpio_csr_mem_rw_with_rand_reset.886078365
Directory /workspace/13.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_csr_rw.3299131344
Short name T733
Test name
Test status
Simulation time 26932606 ps
CPU time 0.63 seconds
Started Jul 01 10:27:02 AM PDT 24
Finished Jul 01 10:27:02 AM PDT 24
Peak memory 195928 kb
Host smart-daa0f03f-19c2-407a-b290-26e405e50850
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3299131344 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.gpi
o_csr_rw.3299131344
Directory /workspace/13.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_intr_test.3399679303
Short name T808
Test name
Test status
Simulation time 46003994 ps
CPU time 0.67 seconds
Started Jul 01 10:27:02 AM PDT 24
Finished Jul 01 10:27:03 AM PDT 24
Peak memory 194312 kb
Host smart-d0bb2fc2-bdb4-4a35-9c7e-a329d62ceb47
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3399679303 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.gpio_intr_test.3399679303
Directory /workspace/13.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_same_csr_outstanding.4093677127
Short name T96
Test name
Test status
Simulation time 23066153 ps
CPU time 0.65 seconds
Started Jul 01 10:25:35 AM PDT 24
Finished Jul 01 10:25:36 AM PDT 24
Peak memory 195236 kb
Host smart-6c94ae23-086f-4ecf-a8d3-0576bb1ce980
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4093677127 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 13.gpio_same_csr_outstanding.4093677127
Directory /workspace/13.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_tl_errors.2312966608
Short name T787
Test name
Test status
Simulation time 40051538 ps
CPU time 1.16 seconds
Started Jul 01 10:25:34 AM PDT 24
Finished Jul 01 10:25:35 AM PDT 24
Peak memory 198492 kb
Host smart-7406b98a-c33c-44e4-8818-13cd47e8d064
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2312966608 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.gpio_tl_errors.2312966608
Directory /workspace/13.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_csr_mem_rw_with_rand_reset.1381335266
Short name T801
Test name
Test status
Simulation time 25743623 ps
CPU time 0.8 seconds
Started Jul 01 10:30:18 AM PDT 24
Finished Jul 01 10:30:20 AM PDT 24
Peak memory 198020 kb
Host smart-039991ab-2d71-41a6-b820-c150121e9d1c
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1381335266 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.gpio_csr_mem_rw_with_rand_reset.1381335266
Directory /workspace/14.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_csr_rw.3605242399
Short name T792
Test name
Test status
Simulation time 30156554 ps
CPU time 0.63 seconds
Started Jul 01 10:26:49 AM PDT 24
Finished Jul 01 10:26:50 AM PDT 24
Peak memory 195796 kb
Host smart-33e0e203-60ed-4476-8ae1-86788c623359
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3605242399 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.gpi
o_csr_rw.3605242399
Directory /workspace/14.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_intr_test.970914819
Short name T762
Test name
Test status
Simulation time 47147834 ps
CPU time 0.58 seconds
Started Jul 01 10:30:18 AM PDT 24
Finished Jul 01 10:30:20 AM PDT 24
Peak memory 193900 kb
Host smart-5b660ad2-9c10-4f68-9a1d-8f859bc880a7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=970914819 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.gpio_intr_test.970914819
Directory /workspace/14.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_same_csr_outstanding.1503979830
Short name T793
Test name
Test status
Simulation time 31245675 ps
CPU time 0.9 seconds
Started Jul 01 10:26:15 AM PDT 24
Finished Jul 01 10:26:16 AM PDT 24
Peak memory 196828 kb
Host smart-e7822ae3-5395-49a5-a1c0-2e23ac4c33f2
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1503979830 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 14.gpio_same_csr_outstanding.1503979830
Directory /workspace/14.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_tl_errors.4255278995
Short name T737
Test name
Test status
Simulation time 106345996 ps
CPU time 1.42 seconds
Started Jul 01 10:23:03 AM PDT 24
Finished Jul 01 10:23:04 AM PDT 24
Peak memory 198464 kb
Host smart-2e57509e-0519-4bea-a44f-23ed6f55f84b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4255278995 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.gpio_tl_errors.4255278995
Directory /workspace/14.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_csr_mem_rw_with_rand_reset.1772801281
Short name T755
Test name
Test status
Simulation time 48571518 ps
CPU time 0.9 seconds
Started Jul 01 10:26:14 AM PDT 24
Finished Jul 01 10:26:15 AM PDT 24
Peak memory 198400 kb
Host smart-e5f04ec0-b29e-47f3-b216-4339a2587cda
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1772801281 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.gpio_csr_mem_rw_with_rand_reset.1772801281
Directory /workspace/15.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_csr_rw.2706377537
Short name T100
Test name
Test status
Simulation time 40886038 ps
CPU time 0.67 seconds
Started Jul 01 10:25:51 AM PDT 24
Finished Jul 01 10:25:52 AM PDT 24
Peak memory 195928 kb
Host smart-e51dda5e-255e-40ff-9b45-e7b29fb756fa
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2706377537 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.gpi
o_csr_rw.2706377537
Directory /workspace/15.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_intr_test.601382369
Short name T778
Test name
Test status
Simulation time 12410358 ps
CPU time 0.57 seconds
Started Jul 01 10:24:06 AM PDT 24
Finished Jul 01 10:24:07 AM PDT 24
Peak memory 194200 kb
Host smart-a6d104e9-7c70-4b32-ab93-df67c1dfac9f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=601382369 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.gpio_intr_test.601382369
Directory /workspace/15.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_same_csr_outstanding.1956198422
Short name T803
Test name
Test status
Simulation time 109688538 ps
CPU time 0.71 seconds
Started Jul 01 10:29:39 AM PDT 24
Finished Jul 01 10:29:40 AM PDT 24
Peak memory 196436 kb
Host smart-74b54252-d1d4-4ef8-a47a-43c9e22d89df
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1956198422 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 15.gpio_same_csr_outstanding.1956198422
Directory /workspace/15.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_tl_errors.2894984101
Short name T836
Test name
Test status
Simulation time 332320038 ps
CPU time 2.95 seconds
Started Jul 01 10:25:42 AM PDT 24
Finished Jul 01 10:25:45 AM PDT 24
Peak memory 198944 kb
Host smart-5cc8d52e-28a7-4316-a3a2-8f1daa27ae25
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2894984101 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.gpio_tl_errors.2894984101
Directory /workspace/15.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_tl_intg_err.1285042904
Short name T39
Test name
Test status
Simulation time 86039995 ps
CPU time 1.12 seconds
Started Jul 01 10:25:31 AM PDT 24
Finished Jul 01 10:25:33 AM PDT 24
Peak memory 198548 kb
Host smart-01438f0a-6da1-433c-830f-7bda21045f37
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1285042904 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 15.gpio_tl_intg_err.1285042904
Directory /workspace/15.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_csr_mem_rw_with_rand_reset.1553599159
Short name T819
Test name
Test status
Simulation time 115205529 ps
CPU time 0.88 seconds
Started Jul 01 10:24:39 AM PDT 24
Finished Jul 01 10:24:41 AM PDT 24
Peak memory 198628 kb
Host smart-7c202dbe-4242-428f-b359-a0220bcaa9ac
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1553599159 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.gpio_csr_mem_rw_with_rand_reset.1553599159
Directory /workspace/16.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_csr_rw.305811301
Short name T739
Test name
Test status
Simulation time 11224293 ps
CPU time 0.6 seconds
Started Jul 01 10:29:58 AM PDT 24
Finished Jul 01 10:30:01 AM PDT 24
Peak memory 193000 kb
Host smart-92a6f668-f21b-4c79-9535-86a253af8672
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=305811301 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.gpio
_csr_rw.305811301
Directory /workspace/16.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_intr_test.3939858129
Short name T777
Test name
Test status
Simulation time 12803814 ps
CPU time 0.57 seconds
Started Jul 01 10:30:00 AM PDT 24
Finished Jul 01 10:30:02 AM PDT 24
Peak memory 193976 kb
Host smart-519ef2aa-296e-4083-9772-f6f9ddb6d2c5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3939858129 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.gpio_intr_test.3939858129
Directory /workspace/16.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_same_csr_outstanding.1311117171
Short name T94
Test name
Test status
Simulation time 139789072 ps
CPU time 0.91 seconds
Started Jul 01 10:29:43 AM PDT 24
Finished Jul 01 10:29:45 AM PDT 24
Peak memory 196660 kb
Host smart-c260cb2e-2a4c-4338-90de-df679728346f
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1311117171 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 16.gpio_same_csr_outstanding.1311117171
Directory /workspace/16.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_tl_errors.2514692207
Short name T797
Test name
Test status
Simulation time 493271885 ps
CPU time 2.8 seconds
Started Jul 01 10:25:30 AM PDT 24
Finished Jul 01 10:25:33 AM PDT 24
Peak memory 198468 kb
Host smart-1b08c44e-54e3-4768-bd18-b188f95cff09
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2514692207 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.gpio_tl_errors.2514692207
Directory /workspace/16.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_csr_mem_rw_with_rand_reset.1144290460
Short name T822
Test name
Test status
Simulation time 124288653 ps
CPU time 1.63 seconds
Started Jul 01 10:24:26 AM PDT 24
Finished Jul 01 10:24:28 AM PDT 24
Peak memory 198648 kb
Host smart-aec6d798-b7c1-4e2a-8f99-477eecbc4ea8
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1144290460 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.gpio_csr_mem_rw_with_rand_reset.1144290460
Directory /workspace/17.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_csr_rw.2511893177
Short name T99
Test name
Test status
Simulation time 12559157 ps
CPU time 0.6 seconds
Started Jul 01 10:28:15 AM PDT 24
Finished Jul 01 10:28:18 AM PDT 24
Peak memory 194116 kb
Host smart-933a3388-2097-4443-a1e9-0e88296ad63e
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2511893177 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.gpi
o_csr_rw.2511893177
Directory /workspace/17.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_intr_test.446326764
Short name T838
Test name
Test status
Simulation time 19102722 ps
CPU time 0.67 seconds
Started Jul 01 10:26:20 AM PDT 24
Finished Jul 01 10:26:21 AM PDT 24
Peak memory 194300 kb
Host smart-c696ebe6-05f4-46c1-af66-b90873d13e4a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=446326764 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.gpio_intr_test.446326764
Directory /workspace/17.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_same_csr_outstanding.2746380049
Short name T76
Test name
Test status
Simulation time 108437428 ps
CPU time 0.8 seconds
Started Jul 01 10:25:32 AM PDT 24
Finished Jul 01 10:25:33 AM PDT 24
Peak memory 196732 kb
Host smart-4a892c0b-2002-452e-8604-d0ff7da97f9b
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2746380049 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 17.gpio_same_csr_outstanding.2746380049
Directory /workspace/17.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_tl_errors.2577614407
Short name T830
Test name
Test status
Simulation time 162175438 ps
CPU time 2.69 seconds
Started Jul 01 10:22:42 AM PDT 24
Finished Jul 01 10:22:45 AM PDT 24
Peak memory 198676 kb
Host smart-b2a73a15-dd93-41a6-9cf5-7163f9137881
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2577614407 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.gpio_tl_errors.2577614407
Directory /workspace/17.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_tl_intg_err.2001672794
Short name T43
Test name
Test status
Simulation time 128287124 ps
CPU time 0.86 seconds
Started Jul 01 10:29:07 AM PDT 24
Finished Jul 01 10:29:08 AM PDT 24
Peak memory 197300 kb
Host smart-eeacea92-e0cd-44fb-a58c-603588e02ee2
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2001672794 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 17.gpio_tl_intg_err.2001672794
Directory /workspace/17.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_csr_mem_rw_with_rand_reset.405633386
Short name T758
Test name
Test status
Simulation time 85014561 ps
CPU time 0.79 seconds
Started Jul 01 10:25:10 AM PDT 24
Finished Jul 01 10:25:11 AM PDT 24
Peak memory 198312 kb
Host smart-9a7b0759-e268-4da7-aa53-b0ec5b72b35f
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=405633386 -asser
t nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.gpio_csr_mem_rw_with_rand_reset.405633386
Directory /workspace/18.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_csr_rw.3392272912
Short name T802
Test name
Test status
Simulation time 123840981 ps
CPU time 0.63 seconds
Started Jul 01 10:24:39 AM PDT 24
Finished Jul 01 10:24:40 AM PDT 24
Peak memory 195380 kb
Host smart-c317ba21-adc3-434b-838f-029fa63b4447
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3392272912 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.gpi
o_csr_rw.3392272912
Directory /workspace/18.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_intr_test.2316451836
Short name T806
Test name
Test status
Simulation time 16139773 ps
CPU time 0.6 seconds
Started Jul 01 10:26:26 AM PDT 24
Finished Jul 01 10:26:26 AM PDT 24
Peak memory 194168 kb
Host smart-78305835-ccf0-485e-9d09-a3705944a849
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2316451836 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.gpio_intr_test.2316451836
Directory /workspace/18.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_same_csr_outstanding.3406310502
Short name T92
Test name
Test status
Simulation time 51656090 ps
CPU time 0.59 seconds
Started Jul 01 10:27:27 AM PDT 24
Finished Jul 01 10:27:28 AM PDT 24
Peak memory 194740 kb
Host smart-fcb6fa59-c5c8-4fd8-862f-02a0d62ec9d5
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3406310502 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 18.gpio_same_csr_outstanding.3406310502
Directory /workspace/18.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_tl_errors.248894546
Short name T776
Test name
Test status
Simulation time 121057960 ps
CPU time 1.65 seconds
Started Jul 01 10:26:43 AM PDT 24
Finished Jul 01 10:26:45 AM PDT 24
Peak memory 198736 kb
Host smart-8aba2abb-e263-478a-a269-ece11172f686
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=248894546 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.gpio_tl_errors.248894546
Directory /workspace/18.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_tl_intg_err.1700674136
Short name T798
Test name
Test status
Simulation time 130406596 ps
CPU time 1.2 seconds
Started Jul 01 10:25:10 AM PDT 24
Finished Jul 01 10:25:12 AM PDT 24
Peak memory 198540 kb
Host smart-5564e2b4-ad8a-48bf-8b4d-5381b59cdf40
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1700674136 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 18.gpio_tl_intg_err.1700674136
Directory /workspace/18.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_csr_mem_rw_with_rand_reset.2592851602
Short name T774
Test name
Test status
Simulation time 17769418 ps
CPU time 0.67 seconds
Started Jul 01 10:27:33 AM PDT 24
Finished Jul 01 10:27:35 AM PDT 24
Peak memory 196668 kb
Host smart-7c888c17-5a4d-4d0b-a067-d9b1c4c03005
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2592851602 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.gpio_csr_mem_rw_with_rand_reset.2592851602
Directory /workspace/19.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_csr_rw.1898133354
Short name T79
Test name
Test status
Simulation time 38668289 ps
CPU time 0.62 seconds
Started Jul 01 10:27:57 AM PDT 24
Finished Jul 01 10:27:59 AM PDT 24
Peak memory 193992 kb
Host smart-46ac43ba-334e-41e5-8397-f9439c62c0eb
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1898133354 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.gpi
o_csr_rw.1898133354
Directory /workspace/19.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_intr_test.708104008
Short name T754
Test name
Test status
Simulation time 15510326 ps
CPU time 0.6 seconds
Started Jul 01 10:26:49 AM PDT 24
Finished Jul 01 10:26:50 AM PDT 24
Peak memory 194188 kb
Host smart-dbb6ee3c-fb1b-46dc-9ebc-c6e242748496
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=708104008 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.gpio_intr_test.708104008
Directory /workspace/19.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_same_csr_outstanding.3950859710
Short name T97
Test name
Test status
Simulation time 60268717 ps
CPU time 0.77 seconds
Started Jul 01 10:29:25 AM PDT 24
Finished Jul 01 10:29:27 AM PDT 24
Peak memory 195956 kb
Host smart-cf712f8e-fee5-4d3d-b1a5-cbc91d3e9809
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3950859710 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 19.gpio_same_csr_outstanding.3950859710
Directory /workspace/19.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_tl_errors.1324670541
Short name T780
Test name
Test status
Simulation time 47277717 ps
CPU time 1.34 seconds
Started Jul 01 10:28:08 AM PDT 24
Finished Jul 01 10:28:10 AM PDT 24
Peak memory 198372 kb
Host smart-3e9413bc-d078-4fb5-b990-57b929922c9e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1324670541 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.gpio_tl_errors.1324670541
Directory /workspace/19.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_tl_intg_err.2203723890
Short name T46
Test name
Test status
Simulation time 303172495 ps
CPU time 1.07 seconds
Started Jul 01 10:28:07 AM PDT 24
Finished Jul 01 10:28:08 AM PDT 24
Peak memory 198136 kb
Host smart-debc9487-4de9-4ae3-ac14-67b4bc45c98c
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2203723890 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 19.gpio_tl_intg_err.2203723890
Directory /workspace/19.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_csr_aliasing.1477869825
Short name T77
Test name
Test status
Simulation time 19500957 ps
CPU time 0.69 seconds
Started Jul 01 10:27:00 AM PDT 24
Finished Jul 01 10:27:01 AM PDT 24
Peak memory 194964 kb
Host smart-260fc00f-ecba-4fe8-b575-0d3855b8c03c
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1477869825 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM
_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
2.gpio_csr_aliasing.1477869825
Directory /workspace/2.gpio_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_csr_bit_bash.578777675
Short name T770
Test name
Test status
Simulation time 122066108 ps
CPU time 1.39 seconds
Started Jul 01 10:22:44 AM PDT 24
Finished Jul 01 10:22:46 AM PDT 24
Peak memory 197112 kb
Host smart-1c082fad-b6c1-4b2f-bb7c-d7414cbb40b5
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=578777675 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_csr_bit_bash.578777675
Directory /workspace/2.gpio_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_csr_hw_reset.281283179
Short name T796
Test name
Test status
Simulation time 15969992 ps
CPU time 0.67 seconds
Started Jul 01 10:23:04 AM PDT 24
Finished Jul 01 10:23:05 AM PDT 24
Peak memory 195784 kb
Host smart-0dcabcda-589d-4025-8abe-0d4df5e9dc24
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=281283179 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_csr_hw_reset.281283179
Directory /workspace/2.gpio_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_csr_mem_rw_with_rand_reset.3235260604
Short name T738
Test name
Test status
Simulation time 299594534 ps
CPU time 1.03 seconds
Started Jul 01 10:28:01 AM PDT 24
Finished Jul 01 10:28:04 AM PDT 24
Peak memory 197104 kb
Host smart-1a1fe7d8-7b98-43ed-98fe-2723c3a56780
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3235260604 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_csr_mem_rw_with_rand_reset.3235260604
Directory /workspace/2.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_csr_rw.1953821305
Short name T72
Test name
Test status
Simulation time 38324696 ps
CPU time 0.59 seconds
Started Jul 01 10:24:00 AM PDT 24
Finished Jul 01 10:24:01 AM PDT 24
Peak memory 195088 kb
Host smart-bee5de7d-6ae5-4a62-9cce-d774ab748623
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1953821305 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio
_csr_rw.1953821305
Directory /workspace/2.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_intr_test.3079755806
Short name T732
Test name
Test status
Simulation time 40756174 ps
CPU time 0.59 seconds
Started Jul 01 10:24:39 AM PDT 24
Finished Jul 01 10:24:40 AM PDT 24
Peak memory 194464 kb
Host smart-ca48cacb-c5c3-4884-bdba-4c828901cfa9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3079755806 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_intr_test.3079755806
Directory /workspace/2.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_same_csr_outstanding.2127604363
Short name T805
Test name
Test status
Simulation time 74839492 ps
CPU time 0.71 seconds
Started Jul 01 10:24:09 AM PDT 24
Finished Jul 01 10:24:10 AM PDT 24
Peak memory 195380 kb
Host smart-6c8674b0-6a76-434c-8cea-4d777b934e59
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2127604363 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 2.gpio_same_csr_outstanding.2127604363
Directory /workspace/2.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_tl_errors.4175245449
Short name T829
Test name
Test status
Simulation time 406543348 ps
CPU time 2.18 seconds
Started Jul 01 10:29:27 AM PDT 24
Finished Jul 01 10:29:31 AM PDT 24
Peak memory 198356 kb
Host smart-dbe33949-b974-479f-b209-e3a9edb9b436
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4175245449 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_tl_errors.4175245449
Directory /workspace/2.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_tl_intg_err.2935197051
Short name T821
Test name
Test status
Simulation time 116176980 ps
CPU time 1.48 seconds
Started Jul 01 10:27:49 AM PDT 24
Finished Jul 01 10:27:51 AM PDT 24
Peak memory 198484 kb
Host smart-eb8d1b0d-2e64-4d61-9502-de096a237aa1
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2935197051 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 2.gpio_tl_intg_err.2935197051
Directory /workspace/2.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.gpio_intr_test.3261030064
Short name T757
Test name
Test status
Simulation time 37825913 ps
CPU time 0.56 seconds
Started Jul 01 10:28:08 AM PDT 24
Finished Jul 01 10:28:09 AM PDT 24
Peak memory 193944 kb
Host smart-8072894b-3a9e-44c5-8ffd-ef5cf6b8a574
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3261030064 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.gpio_intr_test.3261030064
Directory /workspace/20.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.gpio_intr_test.558452499
Short name T827
Test name
Test status
Simulation time 15600805 ps
CPU time 0.63 seconds
Started Jul 01 10:28:08 AM PDT 24
Finished Jul 01 10:28:09 AM PDT 24
Peak memory 194628 kb
Host smart-7fc02060-1b28-4e2c-88f0-cdd28f8ecd2b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=558452499 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.gpio_intr_test.558452499
Directory /workspace/21.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.gpio_intr_test.14947477
Short name T721
Test name
Test status
Simulation time 137336459 ps
CPU time 0.61 seconds
Started Jul 01 10:23:56 AM PDT 24
Finished Jul 01 10:23:57 AM PDT 24
Peak memory 194192 kb
Host smart-8b887d9a-6740-494e-9cac-5ff836851f1e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14947477 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.gpio_intr_test.14947477
Directory /workspace/22.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.gpio_intr_test.468415667
Short name T826
Test name
Test status
Simulation time 23865101 ps
CPU time 0.56 seconds
Started Jul 01 10:28:08 AM PDT 24
Finished Jul 01 10:28:09 AM PDT 24
Peak memory 194120 kb
Host smart-6d354862-e125-46a9-8280-830db7cdc907
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=468415667 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.gpio_intr_test.468415667
Directory /workspace/23.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.gpio_intr_test.749211672
Short name T794
Test name
Test status
Simulation time 24365455 ps
CPU time 0.65 seconds
Started Jul 01 10:24:41 AM PDT 24
Finished Jul 01 10:24:42 AM PDT 24
Peak memory 194232 kb
Host smart-5e027295-ce2a-4fd3-87be-ef022f46e488
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=749211672 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.gpio_intr_test.749211672
Directory /workspace/24.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.gpio_intr_test.1859252387
Short name T810
Test name
Test status
Simulation time 54419121 ps
CPU time 0.61 seconds
Started Jul 01 10:26:43 AM PDT 24
Finished Jul 01 10:26:44 AM PDT 24
Peak memory 194444 kb
Host smart-4c317316-0055-46ef-a365-3332d792e9a2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1859252387 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.gpio_intr_test.1859252387
Directory /workspace/25.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.gpio_intr_test.2241782469
Short name T760
Test name
Test status
Simulation time 101446022 ps
CPU time 0.61 seconds
Started Jul 01 10:28:22 AM PDT 24
Finished Jul 01 10:28:23 AM PDT 24
Peak memory 193400 kb
Host smart-67a9c2db-bb70-45f5-9064-2224416f25b5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2241782469 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.gpio_intr_test.2241782469
Directory /workspace/26.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.gpio_intr_test.3763768204
Short name T833
Test name
Test status
Simulation time 39125852 ps
CPU time 0.58 seconds
Started Jul 01 10:28:23 AM PDT 24
Finished Jul 01 10:28:24 AM PDT 24
Peak memory 194744 kb
Host smart-9bf838f6-85c4-4e19-9c1d-9509280868e0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3763768204 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.gpio_intr_test.3763768204
Directory /workspace/27.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.gpio_intr_test.1532936169
Short name T785
Test name
Test status
Simulation time 25720251 ps
CPU time 0.6 seconds
Started Jul 01 10:23:39 AM PDT 24
Finished Jul 01 10:23:40 AM PDT 24
Peak memory 194512 kb
Host smart-0c27aedf-2fc1-4efd-b3aa-ca0ee8a2489e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1532936169 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.gpio_intr_test.1532936169
Directory /workspace/28.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.gpio_intr_test.492329958
Short name T812
Test name
Test status
Simulation time 71054627 ps
CPU time 0.65 seconds
Started Jul 01 10:24:39 AM PDT 24
Finished Jul 01 10:24:40 AM PDT 24
Peak memory 194468 kb
Host smart-3029c229-6734-4047-ac83-0d9e2f62ed49
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=492329958 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.gpio_intr_test.492329958
Directory /workspace/29.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_csr_aliasing.491080719
Short name T90
Test name
Test status
Simulation time 13065664 ps
CPU time 0.68 seconds
Started Jul 01 10:23:21 AM PDT 24
Finished Jul 01 10:23:22 AM PDT 24
Peak memory 195192 kb
Host smart-8d293618-9ab0-46f0-9ff5-28fcc3d9478b
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=491080719 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3
.gpio_csr_aliasing.491080719
Directory /workspace/3.gpio_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_csr_bit_bash.739156073
Short name T88
Test name
Test status
Simulation time 68886257 ps
CPU time 1.36 seconds
Started Jul 01 10:28:02 AM PDT 24
Finished Jul 01 10:28:05 AM PDT 24
Peak memory 196944 kb
Host smart-38641e15-74ac-4044-a629-71af9fe9d4ad
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=739156073 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_csr_bit_bash.739156073
Directory /workspace/3.gpio_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_csr_hw_reset.1831458632
Short name T832
Test name
Test status
Simulation time 25907695 ps
CPU time 0.62 seconds
Started Jul 01 10:23:49 AM PDT 24
Finished Jul 01 10:23:50 AM PDT 24
Peak memory 194764 kb
Host smart-d170e755-6b29-4bdb-b232-c293eb1c951f
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1831458632 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_csr_hw_reset.1831458632
Directory /workspace/3.gpio_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_csr_mem_rw_with_rand_reset.3831030139
Short name T800
Test name
Test status
Simulation time 18274576 ps
CPU time 0.8 seconds
Started Jul 01 10:23:04 AM PDT 24
Finished Jul 01 10:23:05 AM PDT 24
Peak memory 198368 kb
Host smart-ee960786-778f-40fb-9d9a-83cfaf4c35f3
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3831030139 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_csr_mem_rw_with_rand_reset.3831030139
Directory /workspace/3.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_csr_rw.1902850425
Short name T753
Test name
Test status
Simulation time 37702327 ps
CPU time 0.61 seconds
Started Jul 01 10:27:13 AM PDT 24
Finished Jul 01 10:27:14 AM PDT 24
Peak memory 195284 kb
Host smart-1e6a7399-9cff-4c4e-b79c-e051dd015d9f
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1902850425 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio
_csr_rw.1902850425
Directory /workspace/3.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_intr_test.535100560
Short name T828
Test name
Test status
Simulation time 16243594 ps
CPU time 0.62 seconds
Started Jul 01 10:23:28 AM PDT 24
Finished Jul 01 10:23:29 AM PDT 24
Peak memory 194252 kb
Host smart-c90439d9-bdaa-4faf-a5cb-f6873090bfa8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=535100560 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_intr_test.535100560
Directory /workspace/3.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_same_csr_outstanding.805098401
Short name T817
Test name
Test status
Simulation time 43114155 ps
CPU time 0.65 seconds
Started Jul 01 10:24:08 AM PDT 24
Finished Jul 01 10:24:09 AM PDT 24
Peak memory 195164 kb
Host smart-93ef5169-77b7-4232-a742-a5137bbc76cf
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=805098401 -assert nopostproc +UVM_TESTNAME=gpio_bas
e_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 3.gpio_same_csr_outstanding.805098401
Directory /workspace/3.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_tl_errors.3932061860
Short name T816
Test name
Test status
Simulation time 57453764 ps
CPU time 1.66 seconds
Started Jul 01 10:29:33 AM PDT 24
Finished Jul 01 10:29:36 AM PDT 24
Peak memory 197716 kb
Host smart-aabeb3fe-c112-4c29-9295-e1c3bc40016e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3932061860 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_tl_errors.3932061860
Directory /workspace/3.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_tl_intg_err.4124480594
Short name T44
Test name
Test status
Simulation time 186122985 ps
CPU time 0.84 seconds
Started Jul 01 10:29:42 AM PDT 24
Finished Jul 01 10:29:43 AM PDT 24
Peak memory 197056 kb
Host smart-bf7d53c4-334a-45e3-bf4a-1f17e01bd801
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4124480594 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 3.gpio_tl_intg_err.4124480594
Directory /workspace/3.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.gpio_intr_test.752759396
Short name T727
Test name
Test status
Simulation time 42544519 ps
CPU time 0.6 seconds
Started Jul 01 10:25:18 AM PDT 24
Finished Jul 01 10:25:19 AM PDT 24
Peak memory 194932 kb
Host smart-6b22bd06-0f54-40ac-9e50-34f87ccca138
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=752759396 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.gpio_intr_test.752759396
Directory /workspace/30.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.gpio_intr_test.3900990236
Short name T734
Test name
Test status
Simulation time 87797576 ps
CPU time 0.62 seconds
Started Jul 01 10:24:39 AM PDT 24
Finished Jul 01 10:24:40 AM PDT 24
Peak memory 194928 kb
Host smart-7c8f47f2-a0df-4f4a-971a-5b86b90dc1e2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3900990236 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.gpio_intr_test.3900990236
Directory /workspace/31.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.gpio_intr_test.3832410187
Short name T742
Test name
Test status
Simulation time 19540638 ps
CPU time 0.59 seconds
Started Jul 01 10:26:12 AM PDT 24
Finished Jul 01 10:26:13 AM PDT 24
Peak memory 194264 kb
Host smart-451b3166-1029-469b-b930-57b9f55c8492
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3832410187 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.gpio_intr_test.3832410187
Directory /workspace/32.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.gpio_intr_test.1345390852
Short name T765
Test name
Test status
Simulation time 21238046 ps
CPU time 0.64 seconds
Started Jul 01 10:25:39 AM PDT 24
Finished Jul 01 10:25:40 AM PDT 24
Peak memory 195068 kb
Host smart-07a5d198-3eb9-4961-a1be-301b9d7720ac
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1345390852 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.gpio_intr_test.1345390852
Directory /workspace/33.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.gpio_intr_test.2905784035
Short name T751
Test name
Test status
Simulation time 15933382 ps
CPU time 0.59 seconds
Started Jul 01 10:24:39 AM PDT 24
Finished Jul 01 10:24:41 AM PDT 24
Peak memory 194184 kb
Host smart-8a48b415-6c03-4457-8c0d-29373b7d2d3f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2905784035 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.gpio_intr_test.2905784035
Directory /workspace/34.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.gpio_intr_test.2424652958
Short name T756
Test name
Test status
Simulation time 12504629 ps
CPU time 0.67 seconds
Started Jul 01 10:26:47 AM PDT 24
Finished Jul 01 10:26:48 AM PDT 24
Peak memory 194944 kb
Host smart-0a1e6454-94e2-4e57-b141-d8449995c22d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2424652958 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.gpio_intr_test.2424652958
Directory /workspace/35.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.gpio_intr_test.4033383192
Short name T824
Test name
Test status
Simulation time 130983809 ps
CPU time 0.75 seconds
Started Jul 01 10:26:33 AM PDT 24
Finished Jul 01 10:26:34 AM PDT 24
Peak memory 194476 kb
Host smart-d94afe53-08e2-4e40-b88a-83b53a11ae38
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4033383192 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.gpio_intr_test.4033383192
Directory /workspace/36.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.gpio_intr_test.3214430824
Short name T748
Test name
Test status
Simulation time 14493074 ps
CPU time 0.64 seconds
Started Jul 01 10:24:47 AM PDT 24
Finished Jul 01 10:24:47 AM PDT 24
Peak memory 194276 kb
Host smart-7794ecf8-db02-4743-923d-a38d189d0f6d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3214430824 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.gpio_intr_test.3214430824
Directory /workspace/37.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.gpio_intr_test.272046339
Short name T736
Test name
Test status
Simulation time 12993112 ps
CPU time 0.65 seconds
Started Jul 01 10:30:00 AM PDT 24
Finished Jul 01 10:30:03 AM PDT 24
Peak memory 193440 kb
Host smart-703e62a9-6261-4732-bac5-0fe542e2834b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=272046339 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.gpio_intr_test.272046339
Directory /workspace/38.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.gpio_intr_test.3772943537
Short name T784
Test name
Test status
Simulation time 11521505 ps
CPU time 0.61 seconds
Started Jul 01 10:29:44 AM PDT 24
Finished Jul 01 10:29:46 AM PDT 24
Peak memory 194860 kb
Host smart-9e3cc427-5d47-4af4-b1e5-2a71c840210a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3772943537 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.gpio_intr_test.3772943537
Directory /workspace/39.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_csr_aliasing.3195003195
Short name T86
Test name
Test status
Simulation time 14632168 ps
CPU time 0.73 seconds
Started Jul 01 10:29:40 AM PDT 24
Finished Jul 01 10:29:42 AM PDT 24
Peak memory 196448 kb
Host smart-08a74d6b-7183-4658-9535-df4d7384e6e8
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3195003195 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM
_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
4.gpio_csr_aliasing.3195003195
Directory /workspace/4.gpio_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_csr_bit_bash.836019690
Short name T84
Test name
Test status
Simulation time 212000236 ps
CPU time 2.22 seconds
Started Jul 01 10:27:04 AM PDT 24
Finished Jul 01 10:27:06 AM PDT 24
Peak memory 198504 kb
Host smart-59f4fc57-fb9e-4e6d-aa40-169d8b0a5d6e
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=836019690 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_csr_bit_bash.836019690
Directory /workspace/4.gpio_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_csr_hw_reset.1819293823
Short name T823
Test name
Test status
Simulation time 22143927 ps
CPU time 0.59 seconds
Started Jul 01 10:28:57 AM PDT 24
Finished Jul 01 10:28:58 AM PDT 24
Peak memory 194596 kb
Host smart-363dc118-266c-41fc-b1f4-3a5c0c8aadac
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1819293823 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_csr_hw_reset.1819293823
Directory /workspace/4.gpio_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_csr_mem_rw_with_rand_reset.4252330692
Short name T781
Test name
Test status
Simulation time 39888905 ps
CPU time 1.86 seconds
Started Jul 01 10:26:43 AM PDT 24
Finished Jul 01 10:26:45 AM PDT 24
Peak memory 198840 kb
Host smart-10ec5836-cdd5-4141-8075-4f7c204e35cd
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4252330692 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_csr_mem_rw_with_rand_reset.4252330692
Directory /workspace/4.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_csr_rw.3109967031
Short name T87
Test name
Test status
Simulation time 35387154 ps
CPU time 0.61 seconds
Started Jul 01 10:29:23 AM PDT 24
Finished Jul 01 10:29:24 AM PDT 24
Peak memory 194764 kb
Host smart-88ecad7a-1097-4c57-af95-5295abfdeaf6
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3109967031 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio
_csr_rw.3109967031
Directory /workspace/4.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_intr_test.2645881022
Short name T725
Test name
Test status
Simulation time 54849973 ps
CPU time 0.66 seconds
Started Jul 01 10:26:02 AM PDT 24
Finished Jul 01 10:26:03 AM PDT 24
Peak memory 194328 kb
Host smart-09b4fffa-498e-4407-bcc4-c1ebc13f7a14
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2645881022 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_intr_test.2645881022
Directory /workspace/4.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_same_csr_outstanding.3719242437
Short name T81
Test name
Test status
Simulation time 62228097 ps
CPU time 0.69 seconds
Started Jul 01 10:29:39 AM PDT 24
Finished Jul 01 10:29:41 AM PDT 24
Peak memory 196336 kb
Host smart-546926b9-5b05-4470-9a93-25966fc09c7c
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3719242437 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 4.gpio_same_csr_outstanding.3719242437
Directory /workspace/4.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_tl_errors.759237261
Short name T768
Test name
Test status
Simulation time 180346008 ps
CPU time 1.25 seconds
Started Jul 01 10:26:00 AM PDT 24
Finished Jul 01 10:26:02 AM PDT 24
Peak memory 198544 kb
Host smart-f2ae11e3-fc8a-4708-8d49-eb1ef05366bb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=759237261 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_tl_errors.759237261
Directory /workspace/4.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_tl_intg_err.3603891842
Short name T47
Test name
Test status
Simulation time 133238426 ps
CPU time 0.95 seconds
Started Jul 01 10:28:07 AM PDT 24
Finished Jul 01 10:28:09 AM PDT 24
Peak memory 197476 kb
Host smart-7ec588f1-d73e-41e2-b437-3c21fa493fe8
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3603891842 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 4.gpio_tl_intg_err.3603891842
Directory /workspace/4.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.gpio_intr_test.1887626107
Short name T752
Test name
Test status
Simulation time 57790015 ps
CPU time 0.57 seconds
Started Jul 01 10:27:27 AM PDT 24
Finished Jul 01 10:27:28 AM PDT 24
Peak memory 194180 kb
Host smart-9a09fafd-5b46-487a-82f2-d7eaeb97bd52
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1887626107 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.gpio_intr_test.1887626107
Directory /workspace/40.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.gpio_intr_test.2523765821
Short name T834
Test name
Test status
Simulation time 30146806 ps
CPU time 0.67 seconds
Started Jul 01 10:27:12 AM PDT 24
Finished Jul 01 10:27:14 AM PDT 24
Peak memory 193224 kb
Host smart-5e3b703b-0fd9-4851-b941-7f37516a69ff
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2523765821 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.gpio_intr_test.2523765821
Directory /workspace/41.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.gpio_intr_test.2102863652
Short name T720
Test name
Test status
Simulation time 28482926 ps
CPU time 0.57 seconds
Started Jul 01 10:22:53 AM PDT 24
Finished Jul 01 10:22:54 AM PDT 24
Peak memory 194148 kb
Host smart-c9c903c2-ef8c-470d-bf6d-c96ff1a99d98
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2102863652 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.gpio_intr_test.2102863652
Directory /workspace/42.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.gpio_intr_test.3686058303
Short name T825
Test name
Test status
Simulation time 14424633 ps
CPU time 0.66 seconds
Started Jul 01 10:24:47 AM PDT 24
Finished Jul 01 10:24:47 AM PDT 24
Peak memory 194172 kb
Host smart-3df76569-35f6-4242-b6f9-46fd7f089a00
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3686058303 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.gpio_intr_test.3686058303
Directory /workspace/43.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.gpio_intr_test.710402326
Short name T716
Test name
Test status
Simulation time 42039250 ps
CPU time 0.61 seconds
Started Jul 01 10:26:50 AM PDT 24
Finished Jul 01 10:26:50 AM PDT 24
Peak memory 194852 kb
Host smart-d8635e6a-6773-4a25-9328-e8c5f3850d55
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=710402326 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.gpio_intr_test.710402326
Directory /workspace/44.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.gpio_intr_test.1835867044
Short name T759
Test name
Test status
Simulation time 56524198 ps
CPU time 0.64 seconds
Started Jul 01 10:29:02 AM PDT 24
Finished Jul 01 10:29:03 AM PDT 24
Peak memory 194780 kb
Host smart-0cadc731-83c5-4936-b7a1-f391aba64023
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1835867044 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.gpio_intr_test.1835867044
Directory /workspace/45.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.gpio_intr_test.427112153
Short name T807
Test name
Test status
Simulation time 60770524 ps
CPU time 0.64 seconds
Started Jul 01 10:25:09 AM PDT 24
Finished Jul 01 10:25:11 AM PDT 24
Peak memory 194296 kb
Host smart-6c5e47ca-5c6d-4323-b7cd-db6e866ada83
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=427112153 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.gpio_intr_test.427112153
Directory /workspace/46.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.gpio_intr_test.853714553
Short name T783
Test name
Test status
Simulation time 11514437 ps
CPU time 0.68 seconds
Started Jul 01 10:28:06 AM PDT 24
Finished Jul 01 10:28:07 AM PDT 24
Peak memory 194304 kb
Host smart-c8ee7028-9431-4aba-a6b0-a98e369e9570
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=853714553 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.gpio_intr_test.853714553
Directory /workspace/47.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.gpio_intr_test.370664683
Short name T771
Test name
Test status
Simulation time 14435668 ps
CPU time 0.58 seconds
Started Jul 01 10:25:35 AM PDT 24
Finished Jul 01 10:25:36 AM PDT 24
Peak memory 194628 kb
Host smart-b729500e-190a-484b-9ad3-0f263df42819
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=370664683 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.gpio_intr_test.370664683
Directory /workspace/48.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.gpio_intr_test.823863758
Short name T746
Test name
Test status
Simulation time 29837841 ps
CPU time 0.65 seconds
Started Jul 01 10:29:55 AM PDT 24
Finished Jul 01 10:29:57 AM PDT 24
Peak memory 194240 kb
Host smart-2d5f2035-dd61-451f-8855-8d8c8df36407
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=823863758 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.gpio_intr_test.823863758
Directory /workspace/49.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_csr_mem_rw_with_rand_reset.677177822
Short name T775
Test name
Test status
Simulation time 40476388 ps
CPU time 1.71 seconds
Started Jul 01 10:29:40 AM PDT 24
Finished Jul 01 10:29:43 AM PDT 24
Peak memory 198616 kb
Host smart-c321bb67-f6bd-4be2-8ba3-44e3a44cf45f
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=677177822 -asser
t nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.gpio_csr_mem_rw_with_rand_reset.677177822
Directory /workspace/5.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_csr_rw.3741878711
Short name T782
Test name
Test status
Simulation time 23449334 ps
CPU time 0.64 seconds
Started Jul 01 10:27:03 AM PDT 24
Finished Jul 01 10:27:04 AM PDT 24
Peak memory 195964 kb
Host smart-54b1ceac-9397-4e1d-8af1-cc8aecc87f97
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3741878711 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.gpio
_csr_rw.3741878711
Directory /workspace/5.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_intr_test.2508286391
Short name T741
Test name
Test status
Simulation time 14750947 ps
CPU time 0.64 seconds
Started Jul 01 10:29:30 AM PDT 24
Finished Jul 01 10:29:32 AM PDT 24
Peak memory 193648 kb
Host smart-07263d1a-65db-4802-9849-977b7ebc9a82
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2508286391 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.gpio_intr_test.2508286391
Directory /workspace/5.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_same_csr_outstanding.1551319730
Short name T831
Test name
Test status
Simulation time 56481883 ps
CPU time 0.62 seconds
Started Jul 01 10:22:59 AM PDT 24
Finished Jul 01 10:23:00 AM PDT 24
Peak memory 195184 kb
Host smart-a35366cf-6723-4642-b3ed-9ea8bd83a0d3
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1551319730 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 5.gpio_same_csr_outstanding.1551319730
Directory /workspace/5.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_tl_errors.1640423264
Short name T818
Test name
Test status
Simulation time 1037846630 ps
CPU time 1.66 seconds
Started Jul 01 10:24:26 AM PDT 24
Finished Jul 01 10:24:28 AM PDT 24
Peak memory 198576 kb
Host smart-ee74412b-acc1-4ed1-8f0b-05cdb8571aee
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1640423264 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.gpio_tl_errors.1640423264
Directory /workspace/5.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_tl_intg_err.1507011719
Short name T763
Test name
Test status
Simulation time 198599680 ps
CPU time 0.91 seconds
Started Jul 01 10:29:42 AM PDT 24
Finished Jul 01 10:29:44 AM PDT 24
Peak memory 197616 kb
Host smart-5c83011b-3f5f-4b60-ad30-b2cc81a198c1
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1507011719 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 5.gpio_tl_intg_err.1507011719
Directory /workspace/5.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_csr_mem_rw_with_rand_reset.2827893738
Short name T731
Test name
Test status
Simulation time 16876989 ps
CPU time 0.71 seconds
Started Jul 01 10:27:24 AM PDT 24
Finished Jul 01 10:27:25 AM PDT 24
Peak memory 198276 kb
Host smart-e0c1657a-a822-4034-8927-7645d25eb8dc
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2827893738 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.gpio_csr_mem_rw_with_rand_reset.2827893738
Directory /workspace/6.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_csr_rw.2640248187
Short name T78
Test name
Test status
Simulation time 26918236 ps
CPU time 0.65 seconds
Started Jul 01 10:29:27 AM PDT 24
Finished Jul 01 10:29:30 AM PDT 24
Peak memory 194492 kb
Host smart-7520ab16-ce8b-42fd-811a-b24a313a622d
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2640248187 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.gpio
_csr_rw.2640248187
Directory /workspace/6.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_intr_test.1370646836
Short name T835
Test name
Test status
Simulation time 22990129 ps
CPU time 0.6 seconds
Started Jul 01 10:29:31 AM PDT 24
Finished Jul 01 10:29:32 AM PDT 24
Peak memory 194636 kb
Host smart-d8280e87-af73-4ec5-be1a-a1d569955f68
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1370646836 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.gpio_intr_test.1370646836
Directory /workspace/6.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_same_csr_outstanding.738880316
Short name T815
Test name
Test status
Simulation time 24320913 ps
CPU time 0.65 seconds
Started Jul 01 10:30:12 AM PDT 24
Finished Jul 01 10:30:13 AM PDT 24
Peak memory 194656 kb
Host smart-d94a30bc-cd6a-4625-ab46-7212bbc0f8a5
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=738880316 -assert nopostproc +UVM_TESTNAME=gpio_bas
e_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 6.gpio_same_csr_outstanding.738880316
Directory /workspace/6.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_tl_errors.988244839
Short name T766
Test name
Test status
Simulation time 150772003 ps
CPU time 2.3 seconds
Started Jul 01 10:29:30 AM PDT 24
Finished Jul 01 10:29:33 AM PDT 24
Peak memory 197244 kb
Host smart-c01981a7-43cf-47f4-8bbd-91118ed64dd0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=988244839 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.gpio_tl_errors.988244839
Directory /workspace/6.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_tl_intg_err.752884294
Short name T42
Test name
Test status
Simulation time 190877444 ps
CPU time 0.96 seconds
Started Jul 01 10:28:02 AM PDT 24
Finished Jul 01 10:28:04 AM PDT 24
Peak memory 197260 kb
Host smart-a04f5222-ee53-4f08-b94f-ec625d5dd0c4
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=752884294 -assert nopostproc +UVM_TESTNAME=gpio_base_test +U
VM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 6.gpio_tl_intg_err.752884294
Directory /workspace/6.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_csr_mem_rw_with_rand_reset.1248293040
Short name T728
Test name
Test status
Simulation time 71168250 ps
CPU time 1.04 seconds
Started Jul 01 10:22:58 AM PDT 24
Finished Jul 01 10:23:00 AM PDT 24
Peak memory 198444 kb
Host smart-0b2322ce-e5fe-4724-bf7a-4b12c4015ad2
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1248293040 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.gpio_csr_mem_rw_with_rand_reset.1248293040
Directory /workspace/7.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_csr_rw.3989483598
Short name T83
Test name
Test status
Simulation time 19668514 ps
CPU time 0.63 seconds
Started Jul 01 10:25:39 AM PDT 24
Finished Jul 01 10:25:40 AM PDT 24
Peak memory 195680 kb
Host smart-2e4b65b2-0082-4131-8b3f-72be3b90d518
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3989483598 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.gpio
_csr_rw.3989483598
Directory /workspace/7.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_intr_test.662228760
Short name T726
Test name
Test status
Simulation time 13530925 ps
CPU time 0.6 seconds
Started Jul 01 10:28:15 AM PDT 24
Finished Jul 01 10:28:18 AM PDT 24
Peak memory 193680 kb
Host smart-57751cdd-ac6a-4674-900f-445ab317b8b5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=662228760 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.gpio_intr_test.662228760
Directory /workspace/7.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_same_csr_outstanding.3791073762
Short name T789
Test name
Test status
Simulation time 139483728 ps
CPU time 0.8 seconds
Started Jul 01 10:29:38 AM PDT 24
Finished Jul 01 10:29:40 AM PDT 24
Peak memory 196480 kb
Host smart-e8297d9a-c78a-49ea-9210-d94d9d00a653
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3791073762 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 7.gpio_same_csr_outstanding.3791073762
Directory /workspace/7.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_tl_errors.948285645
Short name T788
Test name
Test status
Simulation time 26265029 ps
CPU time 1.51 seconds
Started Jul 01 10:29:44 AM PDT 24
Finished Jul 01 10:29:47 AM PDT 24
Peak memory 198368 kb
Host smart-0d2a1996-d033-4907-8cae-ccf03860dc57
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=948285645 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.gpio_tl_errors.948285645
Directory /workspace/7.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_tl_intg_err.3288487406
Short name T45
Test name
Test status
Simulation time 1182459050 ps
CPU time 1.2 seconds
Started Jul 01 10:28:15 AM PDT 24
Finished Jul 01 10:28:18 AM PDT 24
Peak memory 196824 kb
Host smart-6e7f2ec3-adf3-4694-bb4d-903106815495
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3288487406 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 7.gpio_tl_intg_err.3288487406
Directory /workspace/7.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_csr_mem_rw_with_rand_reset.1347982360
Short name T791
Test name
Test status
Simulation time 29397792 ps
CPU time 1.27 seconds
Started Jul 01 10:25:03 AM PDT 24
Finished Jul 01 10:25:04 AM PDT 24
Peak memory 198964 kb
Host smart-7793e08c-8d25-4970-9cb4-57c8177f2514
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1347982360 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.gpio_csr_mem_rw_with_rand_reset.1347982360
Directory /workspace/8.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_csr_rw.3503232263
Short name T813
Test name
Test status
Simulation time 48873893 ps
CPU time 0.59 seconds
Started Jul 01 10:25:35 AM PDT 24
Finished Jul 01 10:25:36 AM PDT 24
Peak memory 195592 kb
Host smart-b28ef35d-651e-44ba-a5c6-cdf46b9ed5c4
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3503232263 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.gpio
_csr_rw.3503232263
Directory /workspace/8.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_intr_test.2333182352
Short name T745
Test name
Test status
Simulation time 50500671 ps
CPU time 0.61 seconds
Started Jul 01 10:26:30 AM PDT 24
Finished Jul 01 10:26:31 AM PDT 24
Peak memory 194880 kb
Host smart-e1dd6d22-7cff-46b7-83c5-9d43aa1e0a43
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2333182352 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.gpio_intr_test.2333182352
Directory /workspace/8.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_same_csr_outstanding.3184985334
Short name T74
Test name
Test status
Simulation time 70950606 ps
CPU time 0.89 seconds
Started Jul 01 10:25:18 AM PDT 24
Finished Jul 01 10:25:19 AM PDT 24
Peak memory 197036 kb
Host smart-4dc35d41-454c-44e6-9f94-fac080f2e58b
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3184985334 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 8.gpio_same_csr_outstanding.3184985334
Directory /workspace/8.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_tl_errors.2045177233
Short name T718
Test name
Test status
Simulation time 139031801 ps
CPU time 2.37 seconds
Started Jul 01 10:25:27 AM PDT 24
Finished Jul 01 10:25:30 AM PDT 24
Peak memory 198492 kb
Host smart-f42be99b-230e-49ff-8779-ddeedd083985
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2045177233 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.gpio_tl_errors.2045177233
Directory /workspace/8.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_tl_intg_err.1423535546
Short name T750
Test name
Test status
Simulation time 59530521 ps
CPU time 0.86 seconds
Started Jul 01 10:24:30 AM PDT 24
Finished Jul 01 10:24:31 AM PDT 24
Peak memory 197656 kb
Host smart-ea5ba607-14de-4578-88b8-b2ee3168bb7e
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1423535546 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 8.gpio_tl_intg_err.1423535546
Directory /workspace/8.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_csr_mem_rw_with_rand_reset.195003392
Short name T799
Test name
Test status
Simulation time 59532966 ps
CPU time 0.69 seconds
Started Jul 01 10:25:53 AM PDT 24
Finished Jul 01 10:25:54 AM PDT 24
Peak memory 197464 kb
Host smart-8345f3c4-7176-474a-99e3-2b198556f25f
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=195003392 -asser
t nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.gpio_csr_mem_rw_with_rand_reset.195003392
Directory /workspace/9.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_csr_rw.2993782603
Short name T98
Test name
Test status
Simulation time 46302955 ps
CPU time 0.6 seconds
Started Jul 01 10:25:44 AM PDT 24
Finished Jul 01 10:25:45 AM PDT 24
Peak memory 195304 kb
Host smart-cfccbb2b-bea0-453f-80f2-97be0feb9101
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2993782603 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.gpio
_csr_rw.2993782603
Directory /workspace/9.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_intr_test.2855645934
Short name T729
Test name
Test status
Simulation time 148237623 ps
CPU time 0.62 seconds
Started Jul 01 10:25:08 AM PDT 24
Finished Jul 01 10:25:09 AM PDT 24
Peak memory 194836 kb
Host smart-f345f544-7f07-418c-bdcd-cdea225003c3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2855645934 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.gpio_intr_test.2855645934
Directory /workspace/9.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_same_csr_outstanding.2027357161
Short name T95
Test name
Test status
Simulation time 25754828 ps
CPU time 0.76 seconds
Started Jul 01 10:24:40 AM PDT 24
Finished Jul 01 10:24:41 AM PDT 24
Peak memory 197344 kb
Host smart-67b7d5ee-8740-401c-b629-e9cc2314d587
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2027357161 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 9.gpio_same_csr_outstanding.2027357161
Directory /workspace/9.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_tl_errors.4218482916
Short name T743
Test name
Test status
Simulation time 62819712 ps
CPU time 1.52 seconds
Started Jul 01 10:22:44 AM PDT 24
Finished Jul 01 10:22:46 AM PDT 24
Peak memory 198492 kb
Host smart-e9e0e8de-7ae3-4c6c-a5a1-d2277f92bd7d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4218482916 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.gpio_tl_errors.4218482916
Directory /workspace/9.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_tl_intg_err.4269781808
Short name T820
Test name
Test status
Simulation time 409565829 ps
CPU time 1.45 seconds
Started Jul 01 10:24:58 AM PDT 24
Finished Jul 01 10:24:59 AM PDT 24
Peak memory 198540 kb
Host smart-7bdf4dce-47d1-4b7f-9c43-bcf9e63609b9
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4269781808 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 9.gpio_tl_intg_err.4269781808
Directory /workspace/9.gpio_tl_intg_err/latest

Test location /workspace/coverage/default/0.gpio_dout_din_regs_random_rw.3718809075
Short name T158
Test name
Test status
Simulation time 322635190 ps
CPU time 0.77 seconds
Started Jul 01 10:46:07 AM PDT 24
Finished Jul 01 10:46:08 AM PDT 24
Peak memory 196008 kb
Host smart-bedaf61f-557e-4fff-9351-3a9ae2ee9baa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3718809075 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_dout_din_regs_random_rw.3718809075
Directory /workspace/0.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/0.gpio_filter_stress.1098112999
Short name T581
Test name
Test status
Simulation time 158285074 ps
CPU time 3.7 seconds
Started Jul 01 10:46:28 AM PDT 24
Finished Jul 01 10:46:32 AM PDT 24
Peak memory 196348 kb
Host smart-533fb6d7-9a9d-4495-ba49-595efd6907a8
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1098112999 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_filter_stres
s.1098112999
Directory /workspace/0.gpio_filter_stress/latest

Test location /workspace/coverage/default/0.gpio_full_random.3031298013
Short name T242
Test name
Test status
Simulation time 47151022 ps
CPU time 0.86 seconds
Started Jul 01 10:46:01 AM PDT 24
Finished Jul 01 10:46:02 AM PDT 24
Peak memory 197324 kb
Host smart-279786c1-2b21-4cae-8103-e184870b388e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3031298013 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_full_random.3031298013
Directory /workspace/0.gpio_full_random/latest

Test location /workspace/coverage/default/0.gpio_intr_rand_pgm.543359621
Short name T683
Test name
Test status
Simulation time 299346143 ps
CPU time 1.33 seconds
Started Jul 01 10:46:44 AM PDT 24
Finished Jul 01 10:46:47 AM PDT 24
Peak memory 198764 kb
Host smart-fed532ea-2705-410d-91c5-8ee75919a8c2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=543359621 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_intr_rand_pgm.543359621
Directory /workspace/0.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/0.gpio_intr_with_filter_rand_intr_event.1678277480
Short name T407
Test name
Test status
Simulation time 292655385 ps
CPU time 3.27 seconds
Started Jul 01 10:46:10 AM PDT 24
Finished Jul 01 10:46:19 AM PDT 24
Peak memory 198668 kb
Host smart-d65fe9d9-dbe4-4651-806a-179bc5487517
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1678277480 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 0.gpio_intr_with_filter_rand_intr_event.1678277480
Directory /workspace/0.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/0.gpio_rand_intr_trigger.2291029264
Short name T317
Test name
Test status
Simulation time 451327496 ps
CPU time 3.51 seconds
Started Jul 01 10:46:04 AM PDT 24
Finished Jul 01 10:46:08 AM PDT 24
Peak memory 197792 kb
Host smart-7bf7dc6a-0462-49c9-8c33-a59776a35747
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2291029264 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_rand_intr_trigger.
2291029264
Directory /workspace/0.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/0.gpio_random_dout_din.3569188916
Short name T208
Test name
Test status
Simulation time 70014001 ps
CPU time 1.29 seconds
Started Jul 01 10:46:35 AM PDT 24
Finished Jul 01 10:46:41 AM PDT 24
Peak memory 197096 kb
Host smart-fb7c4cab-38f0-4993-892a-032b19652670
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3569188916 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_random_dout_din.3569188916
Directory /workspace/0.gpio_random_dout_din/latest

Test location /workspace/coverage/default/0.gpio_random_dout_din_no_pullup_pulldown.588549433
Short name T246
Test name
Test status
Simulation time 75291406 ps
CPU time 0.81 seconds
Started Jul 01 10:46:39 AM PDT 24
Finished Jul 01 10:46:44 AM PDT 24
Peak memory 196176 kb
Host smart-47d67286-3afe-4b23-bf33-f189d55e7c5c
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=588549433 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_random_dout_din_no_pullup_
pulldown.588549433
Directory /workspace/0.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/0.gpio_random_long_reg_writes_reg_reads.4062396279
Short name T643
Test name
Test status
Simulation time 135835100 ps
CPU time 2.04 seconds
Started Jul 01 10:46:01 AM PDT 24
Finished Jul 01 10:46:04 AM PDT 24
Peak memory 198624 kb
Host smart-1383e3d4-7bac-4be4-bf60-f7bb06247567
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4062396279 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_ran
dom_long_reg_writes_reg_reads.4062396279
Directory /workspace/0.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/0.gpio_smoke.415328379
Short name T289
Test name
Test status
Simulation time 61704768 ps
CPU time 0.79 seconds
Started Jul 01 10:46:31 AM PDT 24
Finished Jul 01 10:46:33 AM PDT 24
Peak memory 195872 kb
Host smart-cc3b3bdc-25da-442e-bb1d-b2aefddc0fdc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=415328379 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_smoke.415328379
Directory /workspace/0.gpio_smoke/latest

Test location /workspace/coverage/default/0.gpio_smoke_no_pullup_pulldown.2312123397
Short name T263
Test name
Test status
Simulation time 325711977 ps
CPU time 1.35 seconds
Started Jul 01 10:46:21 AM PDT 24
Finished Jul 01 10:46:23 AM PDT 24
Peak memory 196248 kb
Host smart-fa090006-4190-43c5-9aa1-a6ec13cff8a8
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2312123397 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_smoke_no_pullup_pulldown.2312123397
Directory /workspace/0.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/0.gpio_stress_all.3699992054
Short name T536
Test name
Test status
Simulation time 18298469843 ps
CPU time 128.28 seconds
Started Jul 01 10:46:03 AM PDT 24
Finished Jul 01 10:48:13 AM PDT 24
Peak memory 198752 kb
Host smart-aab772ee-2cf7-428c-8787-20dd08cb0bb6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3699992054 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.g
pio_stress_all.3699992054
Directory /workspace/0.gpio_stress_all/latest

Test location /workspace/coverage/default/1.gpio_alert_test.4186984235
Short name T697
Test name
Test status
Simulation time 14680389 ps
CPU time 0.58 seconds
Started Jul 01 10:46:11 AM PDT 24
Finished Jul 01 10:46:13 AM PDT 24
Peak memory 195324 kb
Host smart-2a503d8f-2779-4243-835b-4ce4cc159105
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4186984235 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_alert_test.4186984235
Directory /workspace/1.gpio_alert_test/latest

Test location /workspace/coverage/default/1.gpio_dout_din_regs_random_rw.1376683263
Short name T377
Test name
Test status
Simulation time 27900084 ps
CPU time 0.8 seconds
Started Jul 01 10:46:01 AM PDT 24
Finished Jul 01 10:46:03 AM PDT 24
Peak memory 196520 kb
Host smart-45d0db92-fb56-4eec-9bfb-7374556c5887
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1376683263 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_dout_din_regs_random_rw.1376683263
Directory /workspace/1.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/1.gpio_filter_stress.704101002
Short name T433
Test name
Test status
Simulation time 887275235 ps
CPU time 25.89 seconds
Started Jul 01 10:46:03 AM PDT 24
Finished Jul 01 10:46:30 AM PDT 24
Peak memory 197212 kb
Host smart-d05640e1-b2a9-4838-9c75-dfb0c9dd0f9c
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=704101002 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_filter_stress
.704101002
Directory /workspace/1.gpio_filter_stress/latest

Test location /workspace/coverage/default/1.gpio_full_random.2733601734
Short name T167
Test name
Test status
Simulation time 134590470 ps
CPU time 0.74 seconds
Started Jul 01 10:46:31 AM PDT 24
Finished Jul 01 10:46:32 AM PDT 24
Peak memory 196472 kb
Host smart-3b50d383-4fa1-40da-a677-1dc0ec12e6cc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2733601734 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_full_random.2733601734
Directory /workspace/1.gpio_full_random/latest

Test location /workspace/coverage/default/1.gpio_intr_rand_pgm.2126799673
Short name T544
Test name
Test status
Simulation time 321418288 ps
CPU time 1.4 seconds
Started Jul 01 10:46:03 AM PDT 24
Finished Jul 01 10:46:05 AM PDT 24
Peak memory 198336 kb
Host smart-1bcf51e4-4fe4-4042-9805-e6d0d61038cd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2126799673 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_intr_rand_pgm.2126799673
Directory /workspace/1.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/1.gpio_intr_with_filter_rand_intr_event.3931859441
Short name T470
Test name
Test status
Simulation time 308897919 ps
CPU time 3.03 seconds
Started Jul 01 10:46:33 AM PDT 24
Finished Jul 01 10:46:37 AM PDT 24
Peak memory 198656 kb
Host smart-bfb5ca0f-d5f6-4a44-ae44-190892b79a27
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3931859441 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 1.gpio_intr_with_filter_rand_intr_event.3931859441
Directory /workspace/1.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/1.gpio_rand_intr_trigger.1345549546
Short name T612
Test name
Test status
Simulation time 26656456 ps
CPU time 0.9 seconds
Started Jul 01 10:46:23 AM PDT 24
Finished Jul 01 10:46:24 AM PDT 24
Peak memory 195944 kb
Host smart-fa3b1dfe-043a-4b5a-9654-4a71b43baff9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1345549546 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_rand_intr_trigger.
1345549546
Directory /workspace/1.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/1.gpio_random_dout_din.3123355954
Short name T608
Test name
Test status
Simulation time 32686498 ps
CPU time 1.23 seconds
Started Jul 01 10:46:01 AM PDT 24
Finished Jul 01 10:46:08 AM PDT 24
Peak memory 197684 kb
Host smart-331ffb8d-b490-4955-a9e2-d31c18913281
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3123355954 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_random_dout_din.3123355954
Directory /workspace/1.gpio_random_dout_din/latest

Test location /workspace/coverage/default/1.gpio_random_dout_din_no_pullup_pulldown.2073970521
Short name T340
Test name
Test status
Simulation time 48616971 ps
CPU time 0.94 seconds
Started Jul 01 10:46:03 AM PDT 24
Finished Jul 01 10:46:05 AM PDT 24
Peak memory 197336 kb
Host smart-5ba9cf34-2c5c-42bf-b4c5-324c2695fcf7
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2073970521 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_random_dout_din_no_pullup
_pulldown.2073970521
Directory /workspace/1.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/1.gpio_random_long_reg_writes_reg_reads.242062618
Short name T422
Test name
Test status
Simulation time 2781201901 ps
CPU time 6.18 seconds
Started Jul 01 10:46:11 AM PDT 24
Finished Jul 01 10:46:23 AM PDT 24
Peak memory 198712 kb
Host smart-35c6de22-fe2a-4abc-9d4a-f4fd42bd2aac
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=242062618 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_rand
om_long_reg_writes_reg_reads.242062618
Directory /workspace/1.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/1.gpio_sec_cm.4114652467
Short name T35
Test name
Test status
Simulation time 72750395 ps
CPU time 0.77 seconds
Started Jul 01 10:46:34 AM PDT 24
Finished Jul 01 10:46:40 AM PDT 24
Peak memory 214144 kb
Host smart-844ccdee-3482-4e8f-a9da-f80a9c1eac92
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4114652467 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_sec_cm.4114652467
Directory /workspace/1.gpio_sec_cm/latest

Test location /workspace/coverage/default/1.gpio_smoke.2720605383
Short name T648
Test name
Test status
Simulation time 234184217 ps
CPU time 1.18 seconds
Started Jul 01 10:46:08 AM PDT 24
Finished Jul 01 10:46:09 AM PDT 24
Peak memory 197396 kb
Host smart-95fed7d8-5214-4262-bfad-cc98de312afe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2720605383 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_smoke.2720605383
Directory /workspace/1.gpio_smoke/latest

Test location /workspace/coverage/default/1.gpio_smoke_no_pullup_pulldown.3422247440
Short name T605
Test name
Test status
Simulation time 65160763 ps
CPU time 1.06 seconds
Started Jul 01 10:46:30 AM PDT 24
Finished Jul 01 10:46:32 AM PDT 24
Peak memory 196980 kb
Host smart-91798802-f633-4f82-93fe-9da98ff76fcd
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3422247440 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_smoke_no_pullup_pulldown.3422247440
Directory /workspace/1.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/1.gpio_stress_all.3061802817
Short name T397
Test name
Test status
Simulation time 54693371470 ps
CPU time 112.26 seconds
Started Jul 01 10:46:04 AM PDT 24
Finished Jul 01 10:47:57 AM PDT 24
Peak memory 198820 kb
Host smart-87906cb9-df19-496f-9505-21c5ee219f83
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3061802817 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.g
pio_stress_all.3061802817
Directory /workspace/1.gpio_stress_all/latest

Test location /workspace/coverage/default/10.gpio_alert_test.958206537
Short name T446
Test name
Test status
Simulation time 39412268 ps
CPU time 0.58 seconds
Started Jul 01 10:46:31 AM PDT 24
Finished Jul 01 10:46:32 AM PDT 24
Peak memory 195328 kb
Host smart-e9d03528-f4a2-4635-9909-c3b5a9fbf341
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=958206537 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_alert_test.958206537
Directory /workspace/10.gpio_alert_test/latest

Test location /workspace/coverage/default/10.gpio_dout_din_regs_random_rw.1667093459
Short name T229
Test name
Test status
Simulation time 18687142 ps
CPU time 0.64 seconds
Started Jul 01 10:46:38 AM PDT 24
Finished Jul 01 10:46:43 AM PDT 24
Peak memory 194668 kb
Host smart-4d918933-9b8b-4a7d-997b-7caf72b0969b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1667093459 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_dout_din_regs_random_rw.1667093459
Directory /workspace/10.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/10.gpio_filter_stress.1549268075
Short name T338
Test name
Test status
Simulation time 236574427 ps
CPU time 12.43 seconds
Started Jul 01 10:46:34 AM PDT 24
Finished Jul 01 10:46:49 AM PDT 24
Peak memory 198632 kb
Host smart-263b9690-cd98-48ae-b01d-338c2365458c
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1549268075 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_filter_stre
ss.1549268075
Directory /workspace/10.gpio_filter_stress/latest

Test location /workspace/coverage/default/10.gpio_full_random.1175656952
Short name T654
Test name
Test status
Simulation time 620282360 ps
CPU time 1.09 seconds
Started Jul 01 10:46:21 AM PDT 24
Finished Jul 01 10:46:22 AM PDT 24
Peak memory 197060 kb
Host smart-f4566360-4090-4489-a3f1-124a99bee820
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1175656952 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_full_random.1175656952
Directory /workspace/10.gpio_full_random/latest

Test location /workspace/coverage/default/10.gpio_intr_rand_pgm.1083967034
Short name T332
Test name
Test status
Simulation time 78185747 ps
CPU time 0.84 seconds
Started Jul 01 10:46:22 AM PDT 24
Finished Jul 01 10:46:23 AM PDT 24
Peak memory 195984 kb
Host smart-29498cae-cf3b-4c79-892a-04618d159c76
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1083967034 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_intr_rand_pgm.1083967034
Directory /workspace/10.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/10.gpio_intr_with_filter_rand_intr_event.2090699908
Short name T693
Test name
Test status
Simulation time 76654036 ps
CPU time 3.02 seconds
Started Jul 01 10:46:28 AM PDT 24
Finished Jul 01 10:46:32 AM PDT 24
Peak memory 198648 kb
Host smart-0a31f039-54f7-4945-80ba-08fbc96d5f25
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2090699908 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 10.gpio_intr_with_filter_rand_intr_event.2090699908
Directory /workspace/10.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/10.gpio_rand_intr_trigger.3401965917
Short name T620
Test name
Test status
Simulation time 969909598 ps
CPU time 2.8 seconds
Started Jul 01 10:46:36 AM PDT 24
Finished Jul 01 10:46:43 AM PDT 24
Peak memory 196488 kb
Host smart-9d57ba86-b694-4a3d-af9e-5e952a60aaca
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3401965917 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_rand_intr_trigger
.3401965917
Directory /workspace/10.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/10.gpio_random_dout_din.323749964
Short name T294
Test name
Test status
Simulation time 18355135 ps
CPU time 0.8 seconds
Started Jul 01 10:46:44 AM PDT 24
Finished Jul 01 10:46:46 AM PDT 24
Peak memory 198020 kb
Host smart-e809d878-c3db-4296-a733-4869880dc82d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=323749964 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_random_dout_din.323749964
Directory /workspace/10.gpio_random_dout_din/latest

Test location /workspace/coverage/default/10.gpio_random_dout_din_no_pullup_pulldown.70899724
Short name T152
Test name
Test status
Simulation time 33004484 ps
CPU time 1.26 seconds
Started Jul 01 10:46:23 AM PDT 24
Finished Jul 01 10:46:25 AM PDT 24
Peak memory 197672 kb
Host smart-b49e1c8f-a75a-43ae-8ebc-9083204628d4
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70899724 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_random_dout_din_no_pullup_
pulldown.70899724
Directory /workspace/10.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/10.gpio_random_long_reg_writes_reg_reads.931463053
Short name T351
Test name
Test status
Simulation time 26086727 ps
CPU time 1.15 seconds
Started Jul 01 10:46:33 AM PDT 24
Finished Jul 01 10:46:35 AM PDT 24
Peak memory 198652 kb
Host smart-3968ac5f-7cc1-427c-b580-3270d1c264c4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=931463053 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_ran
dom_long_reg_writes_reg_reads.931463053
Directory /workspace/10.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/10.gpio_smoke.2834009132
Short name T239
Test name
Test status
Simulation time 19486621 ps
CPU time 0.74 seconds
Started Jul 01 10:46:54 AM PDT 24
Finished Jul 01 10:46:57 AM PDT 24
Peak memory 195852 kb
Host smart-76793540-9596-4851-9cec-59554fe76a34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2834009132 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_smoke.2834009132
Directory /workspace/10.gpio_smoke/latest

Test location /workspace/coverage/default/10.gpio_smoke_no_pullup_pulldown.4063989295
Short name T637
Test name
Test status
Simulation time 208746593 ps
CPU time 1.14 seconds
Started Jul 01 10:46:38 AM PDT 24
Finished Jul 01 10:46:44 AM PDT 24
Peak memory 196344 kb
Host smart-e6f0079d-d61d-4d7f-bf36-6437c1e0133d
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4063989295 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_smoke_no_pullup_pulldown.4063989295
Directory /workspace/10.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/10.gpio_stress_all.1656936389
Short name T348
Test name
Test status
Simulation time 24018166184 ps
CPU time 133.12 seconds
Started Jul 01 10:46:34 AM PDT 24
Finished Jul 01 10:48:52 AM PDT 24
Peak memory 198692 kb
Host smart-b313be44-2b03-4d3f-82c3-c6da36b83d31
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1656936389 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.
gpio_stress_all.1656936389
Directory /workspace/10.gpio_stress_all/latest

Test location /workspace/coverage/default/11.gpio_alert_test.3102581702
Short name T253
Test name
Test status
Simulation time 12303129 ps
CPU time 0.56 seconds
Started Jul 01 10:46:34 AM PDT 24
Finished Jul 01 10:46:39 AM PDT 24
Peak memory 194632 kb
Host smart-275d2453-32fe-4361-ae57-b85468dbfdd9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3102581702 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_alert_test.3102581702
Directory /workspace/11.gpio_alert_test/latest

Test location /workspace/coverage/default/11.gpio_dout_din_regs_random_rw.1277149681
Short name T271
Test name
Test status
Simulation time 18973736 ps
CPU time 0.64 seconds
Started Jul 01 10:46:54 AM PDT 24
Finished Jul 01 10:46:57 AM PDT 24
Peak memory 194728 kb
Host smart-d7e0ffbe-1f64-499d-9876-334c578d2900
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1277149681 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_dout_din_regs_random_rw.1277149681
Directory /workspace/11.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/11.gpio_filter_stress.2435785528
Short name T119
Test name
Test status
Simulation time 766759830 ps
CPU time 18.95 seconds
Started Jul 01 10:46:34 AM PDT 24
Finished Jul 01 10:46:56 AM PDT 24
Peak memory 197664 kb
Host smart-34550d40-bae2-4a31-a93a-8c0bcd9b9fed
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2435785528 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_filter_stre
ss.2435785528
Directory /workspace/11.gpio_filter_stress/latest

Test location /workspace/coverage/default/11.gpio_full_random.369726706
Short name T51
Test name
Test status
Simulation time 98425355 ps
CPU time 0.68 seconds
Started Jul 01 10:46:43 AM PDT 24
Finished Jul 01 10:46:46 AM PDT 24
Peak memory 195304 kb
Host smart-95590674-7bbe-48d8-b2f0-35a3ea9b8034
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=369726706 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_full_random.369726706
Directory /workspace/11.gpio_full_random/latest

Test location /workspace/coverage/default/11.gpio_intr_rand_pgm.1123373145
Short name T488
Test name
Test status
Simulation time 55686063 ps
CPU time 1 seconds
Started Jul 01 10:46:32 AM PDT 24
Finished Jul 01 10:46:34 AM PDT 24
Peak memory 196828 kb
Host smart-c056103d-2c51-41e1-8c4c-d1ce14f9927d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1123373145 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_intr_rand_pgm.1123373145
Directory /workspace/11.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/11.gpio_intr_with_filter_rand_intr_event.2723501879
Short name T212
Test name
Test status
Simulation time 392891941 ps
CPU time 1.57 seconds
Started Jul 01 10:46:27 AM PDT 24
Finished Jul 01 10:46:29 AM PDT 24
Peak memory 197088 kb
Host smart-b4cc2f13-c391-48d6-9a7e-e83491460510
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2723501879 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 11.gpio_intr_with_filter_rand_intr_event.2723501879
Directory /workspace/11.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/11.gpio_rand_intr_trigger.2922147708
Short name T439
Test name
Test status
Simulation time 109378901 ps
CPU time 2.92 seconds
Started Jul 01 10:46:42 AM PDT 24
Finished Jul 01 10:46:47 AM PDT 24
Peak memory 198728 kb
Host smart-e874801b-448e-4ad8-a130-2e574c517b1d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2922147708 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_rand_intr_trigger
.2922147708
Directory /workspace/11.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/11.gpio_random_dout_din.630617077
Short name T155
Test name
Test status
Simulation time 228842338 ps
CPU time 1.14 seconds
Started Jul 01 10:46:34 AM PDT 24
Finished Jul 01 10:46:40 AM PDT 24
Peak memory 197300 kb
Host smart-5dfd8037-6a43-406b-918c-ec6f183ae7cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=630617077 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_random_dout_din.630617077
Directory /workspace/11.gpio_random_dout_din/latest

Test location /workspace/coverage/default/11.gpio_random_dout_din_no_pullup_pulldown.1977941031
Short name T384
Test name
Test status
Simulation time 27141306 ps
CPU time 0.79 seconds
Started Jul 01 10:46:34 AM PDT 24
Finished Jul 01 10:46:39 AM PDT 24
Peak memory 195972 kb
Host smart-eeb1efc0-7c58-442a-8c4a-df39b32a6601
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1977941031 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_random_dout_din_no_pullu
p_pulldown.1977941031
Directory /workspace/11.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/11.gpio_random_long_reg_writes_reg_reads.3386334474
Short name T133
Test name
Test status
Simulation time 353525323 ps
CPU time 4.46 seconds
Started Jul 01 10:46:49 AM PDT 24
Finished Jul 01 10:46:55 AM PDT 24
Peak memory 198632 kb
Host smart-31315235-75bd-4725-9968-4f3d4a452495
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3386334474 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_ra
ndom_long_reg_writes_reg_reads.3386334474
Directory /workspace/11.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/11.gpio_smoke.471023056
Short name T251
Test name
Test status
Simulation time 112447874 ps
CPU time 1.05 seconds
Started Jul 01 10:46:24 AM PDT 24
Finished Jul 01 10:46:25 AM PDT 24
Peak memory 196532 kb
Host smart-9be0efe1-38eb-49a9-a321-48afdf08ddd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=471023056 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_smoke.471023056
Directory /workspace/11.gpio_smoke/latest

Test location /workspace/coverage/default/11.gpio_smoke_no_pullup_pulldown.2236530687
Short name T476
Test name
Test status
Simulation time 67399012 ps
CPU time 1.2 seconds
Started Jul 01 10:46:45 AM PDT 24
Finished Jul 01 10:46:47 AM PDT 24
Peak memory 196948 kb
Host smart-382d67e6-9cda-413b-8988-272389a99c7e
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2236530687 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_smoke_no_pullup_pulldown.2236530687
Directory /workspace/11.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/11.gpio_stress_all.8233074
Short name T710
Test name
Test status
Simulation time 15441388067 ps
CPU time 208.18 seconds
Started Jul 01 10:46:34 AM PDT 24
Finished Jul 01 10:50:06 AM PDT 24
Peak memory 198632 kb
Host smart-886df274-e5b3-4dfb-94a3-475c72b013ac
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=8233074 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TES
T_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpi
o_stress_all.8233074
Directory /workspace/11.gpio_stress_all/latest

Test location /workspace/coverage/default/12.gpio_alert_test.3557300427
Short name T678
Test name
Test status
Simulation time 38469672 ps
CPU time 0.61 seconds
Started Jul 01 10:46:59 AM PDT 24
Finished Jul 01 10:47:01 AM PDT 24
Peak memory 195208 kb
Host smart-ba298ac7-3732-435e-96f1-3766943be198
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3557300427 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_alert_test.3557300427
Directory /workspace/12.gpio_alert_test/latest

Test location /workspace/coverage/default/12.gpio_dout_din_regs_random_rw.655948953
Short name T563
Test name
Test status
Simulation time 28007535 ps
CPU time 0.87 seconds
Started Jul 01 10:46:42 AM PDT 24
Finished Jul 01 10:46:46 AM PDT 24
Peak memory 197996 kb
Host smart-8e09eff9-d354-4df4-ae7e-d5f22da841c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=655948953 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_dout_din_regs_random_rw.655948953
Directory /workspace/12.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/12.gpio_filter_stress.39903609
Short name T370
Test name
Test status
Simulation time 447302152 ps
CPU time 14.86 seconds
Started Jul 01 10:46:32 AM PDT 24
Finished Jul 01 10:46:47 AM PDT 24
Peak memory 197584 kb
Host smart-4ca7b837-2949-45d5-b84f-b1e82adccbd4
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39903609 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter_
stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_filter_stress
.39903609
Directory /workspace/12.gpio_filter_stress/latest

Test location /workspace/coverage/default/12.gpio_full_random.1894168874
Short name T142
Test name
Test status
Simulation time 45565249 ps
CPU time 0.84 seconds
Started Jul 01 10:46:39 AM PDT 24
Finished Jul 01 10:46:44 AM PDT 24
Peak memory 196676 kb
Host smart-48b019e3-a165-43a4-98e9-b8bb5dd4233b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1894168874 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_full_random.1894168874
Directory /workspace/12.gpio_full_random/latest

Test location /workspace/coverage/default/12.gpio_intr_rand_pgm.1740293029
Short name T672
Test name
Test status
Simulation time 465733372 ps
CPU time 0.8 seconds
Started Jul 01 10:46:59 AM PDT 24
Finished Jul 01 10:47:02 AM PDT 24
Peak memory 197388 kb
Host smart-50435510-0c1e-4d62-8df6-6067dfa3a07f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1740293029 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_intr_rand_pgm.1740293029
Directory /workspace/12.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/12.gpio_intr_with_filter_rand_intr_event.575944246
Short name T290
Test name
Test status
Simulation time 73445017 ps
CPU time 3.04 seconds
Started Jul 01 10:46:35 AM PDT 24
Finished Jul 01 10:46:43 AM PDT 24
Peak memory 198632 kb
Host smart-4853fcac-35bd-4f0c-8f28-b0f639175717
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=575944246 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 12.gpio_intr_with_filter_rand_intr_event.575944246
Directory /workspace/12.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/12.gpio_rand_intr_trigger.868357642
Short name T635
Test name
Test status
Simulation time 114106636 ps
CPU time 2.2 seconds
Started Jul 01 10:46:44 AM PDT 24
Finished Jul 01 10:46:48 AM PDT 24
Peak memory 198724 kb
Host smart-366c94d9-7a70-4304-a40f-f3972b85e1af
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=868357642 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_rand_intr_trigger.
868357642
Directory /workspace/12.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/12.gpio_random_dout_din.3242007988
Short name T504
Test name
Test status
Simulation time 150187070 ps
CPU time 1.01 seconds
Started Jul 01 10:46:37 AM PDT 24
Finished Jul 01 10:46:42 AM PDT 24
Peak memory 196664 kb
Host smart-b8f28513-ae29-47bc-b290-468e5412a4b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3242007988 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_random_dout_din.3242007988
Directory /workspace/12.gpio_random_dout_din/latest

Test location /workspace/coverage/default/12.gpio_random_dout_din_no_pullup_pulldown.2210900549
Short name T166
Test name
Test status
Simulation time 37540226 ps
CPU time 0.7 seconds
Started Jul 01 10:46:38 AM PDT 24
Finished Jul 01 10:46:43 AM PDT 24
Peak memory 194840 kb
Host smart-9053dd51-fb6f-4d53-84dd-01b4e0ec9945
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2210900549 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_random_dout_din_no_pullu
p_pulldown.2210900549
Directory /workspace/12.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/12.gpio_random_long_reg_writes_reg_reads.916936092
Short name T653
Test name
Test status
Simulation time 270334679 ps
CPU time 3.11 seconds
Started Jul 01 10:46:46 AM PDT 24
Finished Jul 01 10:46:49 AM PDT 24
Peak memory 198484 kb
Host smart-1159c09b-d2c9-4013-9b48-1cb7f452e7b4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=916936092 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_ran
dom_long_reg_writes_reg_reads.916936092
Directory /workspace/12.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/12.gpio_smoke.1402168715
Short name T576
Test name
Test status
Simulation time 213689809 ps
CPU time 0.75 seconds
Started Jul 01 10:46:34 AM PDT 24
Finished Jul 01 10:46:38 AM PDT 24
Peak memory 195964 kb
Host smart-163cb0d2-465e-45c6-89e9-39dd3aa3be17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1402168715 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_smoke.1402168715
Directory /workspace/12.gpio_smoke/latest

Test location /workspace/coverage/default/12.gpio_smoke_no_pullup_pulldown.525470193
Short name T597
Test name
Test status
Simulation time 29199494 ps
CPU time 0.73 seconds
Started Jul 01 10:46:13 AM PDT 24
Finished Jul 01 10:46:15 AM PDT 24
Peak memory 195872 kb
Host smart-8864f2aa-7e15-47fa-8586-b866df5b3797
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=525470193 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_smoke_no_pullup_pulldown.525470193
Directory /workspace/12.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/12.gpio_stress_all.3241126715
Short name T52
Test name
Test status
Simulation time 7398470355 ps
CPU time 24.85 seconds
Started Jul 01 10:46:37 AM PDT 24
Finished Jul 01 10:47:06 AM PDT 24
Peak memory 198812 kb
Host smart-a671bc5f-b95e-4568-91aa-b1da07e0fb80
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3241126715 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.
gpio_stress_all.3241126715
Directory /workspace/12.gpio_stress_all/latest

Test location /workspace/coverage/default/12.gpio_stress_all_with_rand_reset.3919113794
Short name T63
Test name
Test status
Simulation time 358503117413 ps
CPU time 1990.83 seconds
Started Jul 01 10:46:35 AM PDT 24
Finished Jul 01 11:19:51 AM PDT 24
Peak memory 198856 kb
Host smart-5a361d6b-ac0a-4b1d-a2be-af3ff938cd76
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3919113794 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_stress_all_with_rand_reset.3919113794
Directory /workspace/12.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.gpio_alert_test.1468841968
Short name T117
Test name
Test status
Simulation time 13151851 ps
CPU time 0.57 seconds
Started Jul 01 10:46:47 AM PDT 24
Finished Jul 01 10:46:54 AM PDT 24
Peak memory 195536 kb
Host smart-f39d245e-d0f6-4d7a-9122-dca4598aab73
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1468841968 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_alert_test.1468841968
Directory /workspace/13.gpio_alert_test/latest

Test location /workspace/coverage/default/13.gpio_dout_din_regs_random_rw.1062007791
Short name T423
Test name
Test status
Simulation time 123983614 ps
CPU time 0.8 seconds
Started Jul 01 10:46:35 AM PDT 24
Finished Jul 01 10:46:41 AM PDT 24
Peak memory 196688 kb
Host smart-f118765c-da92-419a-aa8c-21c3b015c29d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1062007791 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_dout_din_regs_random_rw.1062007791
Directory /workspace/13.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/13.gpio_filter_stress.2376063736
Short name T17
Test name
Test status
Simulation time 1596351278 ps
CPU time 25.64 seconds
Started Jul 01 10:46:25 AM PDT 24
Finished Jul 01 10:46:51 AM PDT 24
Peak memory 198680 kb
Host smart-d19a8f82-3187-4e7c-bb11-7826a2989c05
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2376063736 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_filter_stre
ss.2376063736
Directory /workspace/13.gpio_filter_stress/latest

Test location /workspace/coverage/default/13.gpio_full_random.2837369186
Short name T13
Test name
Test status
Simulation time 24274437 ps
CPU time 0.65 seconds
Started Jul 01 10:46:35 AM PDT 24
Finished Jul 01 10:46:41 AM PDT 24
Peak memory 195764 kb
Host smart-f9b10b25-d169-492c-81a2-02d129f4bcf5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2837369186 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_full_random.2837369186
Directory /workspace/13.gpio_full_random/latest

Test location /workspace/coverage/default/13.gpio_intr_rand_pgm.3018408348
Short name T260
Test name
Test status
Simulation time 64014208 ps
CPU time 1.36 seconds
Started Jul 01 10:46:33 AM PDT 24
Finished Jul 01 10:46:36 AM PDT 24
Peak memory 197756 kb
Host smart-32038976-56b4-4992-9f42-c27a6f09d55f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3018408348 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_intr_rand_pgm.3018408348
Directory /workspace/13.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/13.gpio_intr_with_filter_rand_intr_event.1448792319
Short name T707
Test name
Test status
Simulation time 328923898 ps
CPU time 3.33 seconds
Started Jul 01 10:46:35 AM PDT 24
Finished Jul 01 10:46:43 AM PDT 24
Peak memory 198780 kb
Host smart-9ff960af-5eeb-4691-8ba1-7dec11065469
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1448792319 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 13.gpio_intr_with_filter_rand_intr_event.1448792319
Directory /workspace/13.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/13.gpio_rand_intr_trigger.1617390310
Short name T689
Test name
Test status
Simulation time 295018897 ps
CPU time 1.72 seconds
Started Jul 01 10:46:34 AM PDT 24
Finished Jul 01 10:46:41 AM PDT 24
Peak memory 197384 kb
Host smart-6015bbe1-320d-426e-852c-baf84b21f0e9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1617390310 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_rand_intr_trigger
.1617390310
Directory /workspace/13.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/13.gpio_random_dout_din.2050938052
Short name T431
Test name
Test status
Simulation time 104809979 ps
CPU time 1.08 seconds
Started Jul 01 10:46:59 AM PDT 24
Finished Jul 01 10:47:02 AM PDT 24
Peak memory 196552 kb
Host smart-93db95d0-e218-4f9e-8ffd-29bb59b332bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2050938052 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_random_dout_din.2050938052
Directory /workspace/13.gpio_random_dout_din/latest

Test location /workspace/coverage/default/13.gpio_random_dout_din_no_pullup_pulldown.3801599137
Short name T469
Test name
Test status
Simulation time 235433325 ps
CPU time 1.03 seconds
Started Jul 01 10:46:35 AM PDT 24
Finished Jul 01 10:46:40 AM PDT 24
Peak memory 196592 kb
Host smart-af9159c7-251c-44b2-b152-26d3d0e0ace9
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3801599137 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_random_dout_din_no_pullu
p_pulldown.3801599137
Directory /workspace/13.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/13.gpio_random_long_reg_writes_reg_reads.2412019314
Short name T409
Test name
Test status
Simulation time 55002463 ps
CPU time 2.52 seconds
Started Jul 01 10:46:37 AM PDT 24
Finished Jul 01 10:46:43 AM PDT 24
Peak memory 198544 kb
Host smart-037cea0b-b5ce-4c6f-8dfb-2e0b54393bbc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2412019314 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_ra
ndom_long_reg_writes_reg_reads.2412019314
Directory /workspace/13.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/13.gpio_smoke.938544140
Short name T281
Test name
Test status
Simulation time 116215050 ps
CPU time 1.15 seconds
Started Jul 01 10:46:34 AM PDT 24
Finished Jul 01 10:46:40 AM PDT 24
Peak memory 196448 kb
Host smart-676d256f-c6e7-43de-9449-24a9f5fda27c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=938544140 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_smoke.938544140
Directory /workspace/13.gpio_smoke/latest

Test location /workspace/coverage/default/13.gpio_smoke_no_pullup_pulldown.2117322425
Short name T412
Test name
Test status
Simulation time 43404751 ps
CPU time 1.13 seconds
Started Jul 01 10:46:38 AM PDT 24
Finished Jul 01 10:46:43 AM PDT 24
Peak memory 196416 kb
Host smart-28ab6be7-4902-445d-8624-173b78b7c0e0
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2117322425 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_smoke_no_pullup_pulldown.2117322425
Directory /workspace/13.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/13.gpio_stress_all.661087528
Short name T293
Test name
Test status
Simulation time 18680881800 ps
CPU time 65.42 seconds
Started Jul 01 10:46:33 AM PDT 24
Finished Jul 01 10:47:41 AM PDT 24
Peak memory 198680 kb
Host smart-cb660c61-ffbc-4747-92cb-4249d7b60e18
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=661087528 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.g
pio_stress_all.661087528
Directory /workspace/13.gpio_stress_all/latest

Test location /workspace/coverage/default/14.gpio_alert_test.1775344063
Short name T244
Test name
Test status
Simulation time 15331064 ps
CPU time 0.63 seconds
Started Jul 01 10:46:56 AM PDT 24
Finished Jul 01 10:47:01 AM PDT 24
Peak memory 194532 kb
Host smart-e29394da-7e11-415f-9092-223e29d2bdf5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1775344063 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_alert_test.1775344063
Directory /workspace/14.gpio_alert_test/latest

Test location /workspace/coverage/default/14.gpio_dout_din_regs_random_rw.3490972568
Short name T196
Test name
Test status
Simulation time 235972564 ps
CPU time 0.91 seconds
Started Jul 01 10:46:35 AM PDT 24
Finished Jul 01 10:46:40 AM PDT 24
Peak memory 197248 kb
Host smart-f978da72-4757-4824-aa0c-2471cf885e28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3490972568 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_dout_din_regs_random_rw.3490972568
Directory /workspace/14.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/14.gpio_filter_stress.530281982
Short name T712
Test name
Test status
Simulation time 2351752006 ps
CPU time 17.84 seconds
Started Jul 01 10:46:34 AM PDT 24
Finished Jul 01 10:46:56 AM PDT 24
Peak memory 198696 kb
Host smart-91a1d3fe-d5c7-41ff-9d90-1c0ac0f71d70
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=530281982 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_filter_stres
s.530281982
Directory /workspace/14.gpio_filter_stress/latest

Test location /workspace/coverage/default/14.gpio_full_random.2506401861
Short name T522
Test name
Test status
Simulation time 58488910 ps
CPU time 0.87 seconds
Started Jul 01 10:46:35 AM PDT 24
Finished Jul 01 10:46:40 AM PDT 24
Peak memory 198420 kb
Host smart-a63c7188-0049-4a2f-8bcf-637ff8974607
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2506401861 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_full_random.2506401861
Directory /workspace/14.gpio_full_random/latest

Test location /workspace/coverage/default/14.gpio_intr_rand_pgm.206935948
Short name T222
Test name
Test status
Simulation time 85972356 ps
CPU time 1.27 seconds
Started Jul 01 10:46:34 AM PDT 24
Finished Jul 01 10:46:40 AM PDT 24
Peak memory 196632 kb
Host smart-29492577-911f-454e-9f33-c035d76f756e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=206935948 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_intr_rand_pgm.206935948
Directory /workspace/14.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/14.gpio_intr_with_filter_rand_intr_event.2829990771
Short name T575
Test name
Test status
Simulation time 49555763 ps
CPU time 1.89 seconds
Started Jul 01 10:46:36 AM PDT 24
Finished Jul 01 10:46:42 AM PDT 24
Peak memory 198700 kb
Host smart-937e2f79-5aff-43fe-965c-bdae61985a2d
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2829990771 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 14.gpio_intr_with_filter_rand_intr_event.2829990771
Directory /workspace/14.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/14.gpio_rand_intr_trigger.532679193
Short name T552
Test name
Test status
Simulation time 109113990 ps
CPU time 3.06 seconds
Started Jul 01 10:46:38 AM PDT 24
Finished Jul 01 10:46:46 AM PDT 24
Peak memory 198740 kb
Host smart-06240e4a-15eb-46ea-b316-f5bd4421527b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=532679193 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_rand_intr_trigger.
532679193
Directory /workspace/14.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/14.gpio_random_dout_din.2870247219
Short name T235
Test name
Test status
Simulation time 123734725 ps
CPU time 1.25 seconds
Started Jul 01 10:46:34 AM PDT 24
Finished Jul 01 10:46:38 AM PDT 24
Peak memory 197552 kb
Host smart-4789fd0f-4a9c-4595-a302-86f9971f782d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2870247219 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_random_dout_din.2870247219
Directory /workspace/14.gpio_random_dout_din/latest

Test location /workspace/coverage/default/14.gpio_random_dout_din_no_pullup_pulldown.69700435
Short name T432
Test name
Test status
Simulation time 108735335 ps
CPU time 1.07 seconds
Started Jul 01 10:46:24 AM PDT 24
Finished Jul 01 10:46:25 AM PDT 24
Peak memory 196660 kb
Host smart-980384ef-4b59-4328-bc45-b9095db328e2
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69700435 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_random_dout_din_no_pullup_
pulldown.69700435
Directory /workspace/14.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/14.gpio_random_long_reg_writes_reg_reads.3489312009
Short name T634
Test name
Test status
Simulation time 531399726 ps
CPU time 5.98 seconds
Started Jul 01 10:46:33 AM PDT 24
Finished Jul 01 10:46:40 AM PDT 24
Peak memory 198540 kb
Host smart-72835990-6562-43e0-ae93-ea399a1ce526
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3489312009 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_ra
ndom_long_reg_writes_reg_reads.3489312009
Directory /workspace/14.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/14.gpio_smoke.1160883743
Short name T203
Test name
Test status
Simulation time 36119376 ps
CPU time 0.95 seconds
Started Jul 01 10:46:35 AM PDT 24
Finished Jul 01 10:46:41 AM PDT 24
Peak memory 197636 kb
Host smart-2e358dbd-ca17-4bcd-861f-79326828e253
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1160883743 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_smoke.1160883743
Directory /workspace/14.gpio_smoke/latest

Test location /workspace/coverage/default/14.gpio_smoke_no_pullup_pulldown.2058657173
Short name T141
Test name
Test status
Simulation time 278046798 ps
CPU time 1.39 seconds
Started Jul 01 10:46:50 AM PDT 24
Finished Jul 01 10:46:52 AM PDT 24
Peak memory 197472 kb
Host smart-1d3da969-e7fe-474e-bdc2-b5dda1ab0eb3
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2058657173 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_smoke_no_pullup_pulldown.2058657173
Directory /workspace/14.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/14.gpio_stress_all.1964591018
Short name T240
Test name
Test status
Simulation time 3080917646 ps
CPU time 35.86 seconds
Started Jul 01 10:46:39 AM PDT 24
Finished Jul 01 10:47:19 AM PDT 24
Peak memory 198796 kb
Host smart-898b4e77-f1e1-4e3d-b7ea-7977969dcf3f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1964591018 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.
gpio_stress_all.1964591018
Directory /workspace/14.gpio_stress_all/latest

Test location /workspace/coverage/default/15.gpio_alert_test.3714143714
Short name T440
Test name
Test status
Simulation time 24931696 ps
CPU time 0.58 seconds
Started Jul 01 10:47:12 AM PDT 24
Finished Jul 01 10:47:14 AM PDT 24
Peak memory 194588 kb
Host smart-1534cb97-bf2f-4c9f-a335-1a3dab9c6dbe
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3714143714 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_alert_test.3714143714
Directory /workspace/15.gpio_alert_test/latest

Test location /workspace/coverage/default/15.gpio_dout_din_regs_random_rw.323832172
Short name T580
Test name
Test status
Simulation time 23918630 ps
CPU time 0.66 seconds
Started Jul 01 10:46:34 AM PDT 24
Finished Jul 01 10:46:40 AM PDT 24
Peak memory 194732 kb
Host smart-5996a682-206c-47c6-b12f-c5fb62b5e6db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=323832172 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_dout_din_regs_random_rw.323832172
Directory /workspace/15.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/15.gpio_filter_stress.674203398
Short name T570
Test name
Test status
Simulation time 961440348 ps
CPU time 26.6 seconds
Started Jul 01 10:46:39 AM PDT 24
Finished Jul 01 10:47:10 AM PDT 24
Peak memory 196912 kb
Host smart-9a5110be-b293-4b3e-b438-b2bfca61931e
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=674203398 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_filter_stres
s.674203398
Directory /workspace/15.gpio_filter_stress/latest

Test location /workspace/coverage/default/15.gpio_full_random.3530782662
Short name T443
Test name
Test status
Simulation time 635110018 ps
CPU time 0.88 seconds
Started Jul 01 10:46:34 AM PDT 24
Finished Jul 01 10:46:38 AM PDT 24
Peak memory 196700 kb
Host smart-f79dc5cd-aff7-4c4d-9088-a6c5859f0b62
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3530782662 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_full_random.3530782662
Directory /workspace/15.gpio_full_random/latest

Test location /workspace/coverage/default/15.gpio_intr_rand_pgm.1722678313
Short name T437
Test name
Test status
Simulation time 177777205 ps
CPU time 0.97 seconds
Started Jul 01 10:46:30 AM PDT 24
Finished Jul 01 10:46:32 AM PDT 24
Peak memory 197308 kb
Host smart-9e832160-ad8a-40e0-9a3b-7ba300095068
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1722678313 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_intr_rand_pgm.1722678313
Directory /workspace/15.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/15.gpio_intr_with_filter_rand_intr_event.2247193355
Short name T372
Test name
Test status
Simulation time 253683501 ps
CPU time 2.72 seconds
Started Jul 01 10:46:34 AM PDT 24
Finished Jul 01 10:46:41 AM PDT 24
Peak memory 198688 kb
Host smart-6e83cc10-3228-44bb-95de-5f84ffa4d2c0
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2247193355 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 15.gpio_intr_with_filter_rand_intr_event.2247193355
Directory /workspace/15.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/15.gpio_rand_intr_trigger.1440729868
Short name T501
Test name
Test status
Simulation time 314770534 ps
CPU time 2.96 seconds
Started Jul 01 10:46:36 AM PDT 24
Finished Jul 01 10:46:46 AM PDT 24
Peak memory 197692 kb
Host smart-7bb657a4-0562-4930-9b06-736d4fa15573
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1440729868 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_rand_intr_trigger
.1440729868
Directory /workspace/15.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/15.gpio_random_dout_din.423868473
Short name T237
Test name
Test status
Simulation time 95246209 ps
CPU time 0.83 seconds
Started Jul 01 10:46:56 AM PDT 24
Finished Jul 01 10:47:01 AM PDT 24
Peak memory 196084 kb
Host smart-6d59d502-e4fd-46fb-be91-34919b83c2f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=423868473 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_random_dout_din.423868473
Directory /workspace/15.gpio_random_dout_din/latest

Test location /workspace/coverage/default/15.gpio_random_dout_din_no_pullup_pulldown.3613901193
Short name T125
Test name
Test status
Simulation time 105939880 ps
CPU time 0.68 seconds
Started Jul 01 10:46:59 AM PDT 24
Finished Jul 01 10:47:01 AM PDT 24
Peak memory 194824 kb
Host smart-576c3d35-344c-4dc1-8cde-e8b8cbfe18cb
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3613901193 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_random_dout_din_no_pullu
p_pulldown.3613901193
Directory /workspace/15.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/15.gpio_random_long_reg_writes_reg_reads.711036391
Short name T662
Test name
Test status
Simulation time 386181307 ps
CPU time 4.52 seconds
Started Jul 01 10:46:44 AM PDT 24
Finished Jul 01 10:46:50 AM PDT 24
Peak memory 198640 kb
Host smart-746a1518-6832-4827-9c9b-b1b48878626f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=711036391 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_ran
dom_long_reg_writes_reg_reads.711036391
Directory /workspace/15.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/15.gpio_smoke.375659101
Short name T353
Test name
Test status
Simulation time 22181174 ps
CPU time 0.71 seconds
Started Jul 01 10:46:40 AM PDT 24
Finished Jul 01 10:46:44 AM PDT 24
Peak memory 194812 kb
Host smart-0cd732a6-a043-4a7c-bf45-96dca7dde8dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=375659101 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_smoke.375659101
Directory /workspace/15.gpio_smoke/latest

Test location /workspace/coverage/default/15.gpio_smoke_no_pullup_pulldown.4253384550
Short name T508
Test name
Test status
Simulation time 195217215 ps
CPU time 1.23 seconds
Started Jul 01 10:46:34 AM PDT 24
Finished Jul 01 10:46:40 AM PDT 24
Peak memory 197016 kb
Host smart-bea19249-f507-43f2-832f-b2a4a4ce9dac
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4253384550 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_smoke_no_pullup_pulldown.4253384550
Directory /workspace/15.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/15.gpio_stress_all.4031761050
Short name T5
Test name
Test status
Simulation time 7605746203 ps
CPU time 78.24 seconds
Started Jul 01 10:46:46 AM PDT 24
Finished Jul 01 10:48:06 AM PDT 24
Peak memory 198764 kb
Host smart-af401734-8370-4887-95da-ce1bcc1a725a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4031761050 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.
gpio_stress_all.4031761050
Directory /workspace/15.gpio_stress_all/latest

Test location /workspace/coverage/default/16.gpio_alert_test.1930026947
Short name T619
Test name
Test status
Simulation time 31486213 ps
CPU time 0.54 seconds
Started Jul 01 10:46:33 AM PDT 24
Finished Jul 01 10:46:37 AM PDT 24
Peak memory 194604 kb
Host smart-4f61495b-d752-421b-96d9-05d7a5fc591b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1930026947 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_alert_test.1930026947
Directory /workspace/16.gpio_alert_test/latest

Test location /workspace/coverage/default/16.gpio_dout_din_regs_random_rw.3026493962
Short name T66
Test name
Test status
Simulation time 48566195 ps
CPU time 0.62 seconds
Started Jul 01 10:46:55 AM PDT 24
Finished Jul 01 10:47:02 AM PDT 24
Peak memory 195336 kb
Host smart-0d893e1c-489f-4823-8b84-9ce7dff8166d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3026493962 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_dout_din_regs_random_rw.3026493962
Directory /workspace/16.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/16.gpio_filter_stress.91471922
Short name T467
Test name
Test status
Simulation time 1607247507 ps
CPU time 14.12 seconds
Started Jul 01 10:46:51 AM PDT 24
Finished Jul 01 10:47:07 AM PDT 24
Peak memory 196216 kb
Host smart-5a706324-a294-4879-942f-776935b11ba5
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91471922 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter_
stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_filter_stress
.91471922
Directory /workspace/16.gpio_filter_stress/latest

Test location /workspace/coverage/default/16.gpio_full_random.1960137606
Short name T169
Test name
Test status
Simulation time 189751413 ps
CPU time 0.88 seconds
Started Jul 01 10:46:40 AM PDT 24
Finished Jul 01 10:46:44 AM PDT 24
Peak memory 197612 kb
Host smart-81a6ae04-c62e-4235-bdf1-5783208d356b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1960137606 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_full_random.1960137606
Directory /workspace/16.gpio_full_random/latest

Test location /workspace/coverage/default/16.gpio_intr_rand_pgm.837220640
Short name T674
Test name
Test status
Simulation time 89707343 ps
CPU time 1.33 seconds
Started Jul 01 10:46:45 AM PDT 24
Finished Jul 01 10:46:47 AM PDT 24
Peak memory 197824 kb
Host smart-9c6eced1-aa72-4fe1-846b-499485c203ca
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=837220640 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_intr_rand_pgm.837220640
Directory /workspace/16.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/16.gpio_rand_intr_trigger.1317094907
Short name T382
Test name
Test status
Simulation time 287284087 ps
CPU time 1.06 seconds
Started Jul 01 10:46:33 AM PDT 24
Finished Jul 01 10:46:36 AM PDT 24
Peak memory 196216 kb
Host smart-a4aef6b3-2ebd-4ade-bc7b-c617702b3b3e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1317094907 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_rand_intr_trigger
.1317094907
Directory /workspace/16.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/16.gpio_random_dout_din.3921651173
Short name T248
Test name
Test status
Simulation time 84629943 ps
CPU time 0.92 seconds
Started Jul 01 10:46:34 AM PDT 24
Finished Jul 01 10:46:39 AM PDT 24
Peak memory 196596 kb
Host smart-67c3dcfe-a5ed-4bfa-9aa6-3d3f75beaae2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3921651173 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_random_dout_din.3921651173
Directory /workspace/16.gpio_random_dout_din/latest

Test location /workspace/coverage/default/16.gpio_random_dout_din_no_pullup_pulldown.3037357913
Short name T333
Test name
Test status
Simulation time 27108934 ps
CPU time 1.12 seconds
Started Jul 01 10:46:55 AM PDT 24
Finished Jul 01 10:47:01 AM PDT 24
Peak memory 196620 kb
Host smart-d449750a-82d3-4793-a20c-86f87d2617b5
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3037357913 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_random_dout_din_no_pullu
p_pulldown.3037357913
Directory /workspace/16.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/16.gpio_random_long_reg_writes_reg_reads.1579304222
Short name T410
Test name
Test status
Simulation time 437222542 ps
CPU time 5.72 seconds
Started Jul 01 10:46:34 AM PDT 24
Finished Jul 01 10:46:43 AM PDT 24
Peak memory 198624 kb
Host smart-247d4eea-b015-4435-9a18-95304bb9b2df
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1579304222 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_ra
ndom_long_reg_writes_reg_reads.1579304222
Directory /workspace/16.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/16.gpio_smoke.2759364980
Short name T573
Test name
Test status
Simulation time 152801638 ps
CPU time 1.23 seconds
Started Jul 01 10:47:05 AM PDT 24
Finished Jul 01 10:47:08 AM PDT 24
Peak memory 197500 kb
Host smart-9c2033eb-483b-4e00-b22c-63576b1feec0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2759364980 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_smoke.2759364980
Directory /workspace/16.gpio_smoke/latest

Test location /workspace/coverage/default/16.gpio_smoke_no_pullup_pulldown.3424912400
Short name T285
Test name
Test status
Simulation time 74006059 ps
CPU time 1.17 seconds
Started Jul 01 10:46:52 AM PDT 24
Finished Jul 01 10:46:54 AM PDT 24
Peak memory 198628 kb
Host smart-acf6fe4d-7de5-4150-80bf-990761a30075
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3424912400 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_smoke_no_pullup_pulldown.3424912400
Directory /workspace/16.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/16.gpio_stress_all.1970751593
Short name T561
Test name
Test status
Simulation time 3587193592 ps
CPU time 92.99 seconds
Started Jul 01 10:47:11 AM PDT 24
Finished Jul 01 10:48:46 AM PDT 24
Peak memory 198780 kb
Host smart-66d5c70d-631d-4189-b106-9d6b795e62ef
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1970751593 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.
gpio_stress_all.1970751593
Directory /workspace/16.gpio_stress_all/latest

Test location /workspace/coverage/default/17.gpio_alert_test.1585732231
Short name T55
Test name
Test status
Simulation time 15098534 ps
CPU time 0.56 seconds
Started Jul 01 10:46:40 AM PDT 24
Finished Jul 01 10:46:44 AM PDT 24
Peak memory 194796 kb
Host smart-39dd6eb4-d46f-4654-8253-9a5658af88f6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1585732231 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_alert_test.1585732231
Directory /workspace/17.gpio_alert_test/latest

Test location /workspace/coverage/default/17.gpio_dout_din_regs_random_rw.499357167
Short name T25
Test name
Test status
Simulation time 57346683 ps
CPU time 0.75 seconds
Started Jul 01 10:46:49 AM PDT 24
Finished Jul 01 10:46:50 AM PDT 24
Peak memory 195408 kb
Host smart-ff10a481-418b-45b0-873b-0e54c426be97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=499357167 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_dout_din_regs_random_rw.499357167
Directory /workspace/17.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/17.gpio_filter_stress.1708242802
Short name T491
Test name
Test status
Simulation time 1148197127 ps
CPU time 10.01 seconds
Started Jul 01 10:46:51 AM PDT 24
Finished Jul 01 10:47:02 AM PDT 24
Peak memory 198552 kb
Host smart-33a39128-c795-4800-8c70-beeaf625bb91
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1708242802 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_filter_stre
ss.1708242802
Directory /workspace/17.gpio_filter_stress/latest

Test location /workspace/coverage/default/17.gpio_full_random.1019809975
Short name T395
Test name
Test status
Simulation time 81939684 ps
CPU time 1.05 seconds
Started Jul 01 10:47:06 AM PDT 24
Finished Jul 01 10:47:09 AM PDT 24
Peak memory 197308 kb
Host smart-3f99c9dc-6dc5-4059-bbd4-591f99d1df39
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1019809975 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_full_random.1019809975
Directory /workspace/17.gpio_full_random/latest

Test location /workspace/coverage/default/17.gpio_intr_rand_pgm.1854684115
Short name T650
Test name
Test status
Simulation time 63102768 ps
CPU time 1.04 seconds
Started Jul 01 10:47:03 AM PDT 24
Finished Jul 01 10:47:04 AM PDT 24
Peak memory 196452 kb
Host smart-a5be38cd-7492-41ff-95b2-716e41672fa3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1854684115 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_intr_rand_pgm.1854684115
Directory /workspace/17.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/17.gpio_intr_with_filter_rand_intr_event.2846060264
Short name T177
Test name
Test status
Simulation time 70304303 ps
CPU time 2.42 seconds
Started Jul 01 10:46:46 AM PDT 24
Finished Jul 01 10:46:49 AM PDT 24
Peak memory 197228 kb
Host smart-c40d4e7f-ac2a-4ab9-b362-3cbb8ec0901e
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2846060264 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 17.gpio_intr_with_filter_rand_intr_event.2846060264
Directory /workspace/17.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/17.gpio_rand_intr_trigger.3734928667
Short name T356
Test name
Test status
Simulation time 1184844031 ps
CPU time 2 seconds
Started Jul 01 10:47:15 AM PDT 24
Finished Jul 01 10:47:18 AM PDT 24
Peak memory 196832 kb
Host smart-3b9a458d-6004-40ab-bfa5-1c7e597b184a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3734928667 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_rand_intr_trigger
.3734928667
Directory /workspace/17.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/17.gpio_random_dout_din.921971541
Short name T628
Test name
Test status
Simulation time 399218893 ps
CPU time 0.92 seconds
Started Jul 01 10:46:37 AM PDT 24
Finished Jul 01 10:46:43 AM PDT 24
Peak memory 196732 kb
Host smart-234908b2-bed9-40a0-b2db-b5f8aa2bfb39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=921971541 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_random_dout_din.921971541
Directory /workspace/17.gpio_random_dout_din/latest

Test location /workspace/coverage/default/17.gpio_random_dout_din_no_pullup_pulldown.3211147894
Short name T600
Test name
Test status
Simulation time 61529164 ps
CPU time 0.65 seconds
Started Jul 01 10:46:34 AM PDT 24
Finished Jul 01 10:46:40 AM PDT 24
Peak memory 195076 kb
Host smart-d212277b-5487-489e-9c09-78847681897e
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3211147894 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_random_dout_din_no_pullu
p_pulldown.3211147894
Directory /workspace/17.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/17.gpio_random_long_reg_writes_reg_reads.2624691747
Short name T652
Test name
Test status
Simulation time 413684612 ps
CPU time 4.41 seconds
Started Jul 01 10:46:54 AM PDT 24
Finished Jul 01 10:46:59 AM PDT 24
Peak memory 198608 kb
Host smart-89181452-670a-4b40-b9ae-5de1977100b1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2624691747 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_ra
ndom_long_reg_writes_reg_reads.2624691747
Directory /workspace/17.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/17.gpio_smoke.65063309
Short name T337
Test name
Test status
Simulation time 126575197 ps
CPU time 0.99 seconds
Started Jul 01 10:46:33 AM PDT 24
Finished Jul 01 10:46:37 AM PDT 24
Peak memory 196640 kb
Host smart-2ccbc53e-2e28-47c7-ad22-db97c8c61d80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=65063309 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_smoke.65063309
Directory /workspace/17.gpio_smoke/latest

Test location /workspace/coverage/default/17.gpio_smoke_no_pullup_pulldown.2338174074
Short name T195
Test name
Test status
Simulation time 81777981 ps
CPU time 0.69 seconds
Started Jul 01 10:46:48 AM PDT 24
Finished Jul 01 10:46:50 AM PDT 24
Peak memory 194828 kb
Host smart-2f5ba3f1-df03-4d8c-8c7f-e01e9c7aaa60
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2338174074 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_smoke_no_pullup_pulldown.2338174074
Directory /workspace/17.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/17.gpio_stress_all.4038736882
Short name T6
Test name
Test status
Simulation time 59720470835 ps
CPU time 193.59 seconds
Started Jul 01 10:46:42 AM PDT 24
Finished Jul 01 10:49:58 AM PDT 24
Peak memory 198836 kb
Host smart-68f8a79e-2ad6-4ce5-86ef-f8ef5e1bf9ba
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4038736882 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.
gpio_stress_all.4038736882
Directory /workspace/17.gpio_stress_all/latest

Test location /workspace/coverage/default/17.gpio_stress_all_with_rand_reset.2687445549
Short name T699
Test name
Test status
Simulation time 38753987040 ps
CPU time 863.75 seconds
Started Jul 01 10:46:27 AM PDT 24
Finished Jul 01 11:00:51 AM PDT 24
Peak memory 198840 kb
Host smart-7229933c-85f2-43c4-9575-5c3cbc789d84
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2687445549 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_stress_all_with_rand_reset.2687445549
Directory /workspace/17.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.gpio_alert_test.1255150375
Short name T387
Test name
Test status
Simulation time 61919056 ps
CPU time 0.56 seconds
Started Jul 01 10:46:58 AM PDT 24
Finished Jul 01 10:47:00 AM PDT 24
Peak memory 194536 kb
Host smart-ab72a4a6-69b0-4483-aa3e-cf83577ead45
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1255150375 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_alert_test.1255150375
Directory /workspace/18.gpio_alert_test/latest

Test location /workspace/coverage/default/18.gpio_dout_din_regs_random_rw.2853839735
Short name T183
Test name
Test status
Simulation time 24605002 ps
CPU time 0.68 seconds
Started Jul 01 10:46:55 AM PDT 24
Finished Jul 01 10:46:57 AM PDT 24
Peak memory 194720 kb
Host smart-3e0b93df-9ce2-4253-9f40-1b7d3ac151d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2853839735 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_dout_din_regs_random_rw.2853839735
Directory /workspace/18.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/18.gpio_filter_stress.2915402777
Short name T638
Test name
Test status
Simulation time 959570241 ps
CPU time 16.32 seconds
Started Jul 01 10:46:28 AM PDT 24
Finished Jul 01 10:46:45 AM PDT 24
Peak memory 196188 kb
Host smart-b21aa0ee-c507-419e-8e3f-5802c36e06fb
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2915402777 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_filter_stre
ss.2915402777
Directory /workspace/18.gpio_filter_stress/latest

Test location /workspace/coverage/default/18.gpio_full_random.4225697353
Short name T312
Test name
Test status
Simulation time 49961415 ps
CPU time 0.83 seconds
Started Jul 01 10:47:14 AM PDT 24
Finished Jul 01 10:47:16 AM PDT 24
Peak memory 197140 kb
Host smart-b911a2a6-3b9b-4cff-b123-1001588f2d64
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4225697353 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_full_random.4225697353
Directory /workspace/18.gpio_full_random/latest

Test location /workspace/coverage/default/18.gpio_intr_rand_pgm.1935128967
Short name T330
Test name
Test status
Simulation time 105662556 ps
CPU time 1.3 seconds
Started Jul 01 10:46:25 AM PDT 24
Finished Jul 01 10:46:26 AM PDT 24
Peak memory 196440 kb
Host smart-64ba8c84-c614-4745-b776-c7d181692415
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1935128967 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_intr_rand_pgm.1935128967
Directory /workspace/18.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/18.gpio_intr_with_filter_rand_intr_event.539950180
Short name T213
Test name
Test status
Simulation time 74829427 ps
CPU time 2.98 seconds
Started Jul 01 10:46:33 AM PDT 24
Finished Jul 01 10:46:38 AM PDT 24
Peak memory 198668 kb
Host smart-0fc46fad-c953-4b33-9888-2e7d70f4dc92
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=539950180 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 18.gpio_intr_with_filter_rand_intr_event.539950180
Directory /workspace/18.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/18.gpio_rand_intr_trigger.3011470824
Short name T359
Test name
Test status
Simulation time 224481354 ps
CPU time 3.46 seconds
Started Jul 01 10:46:45 AM PDT 24
Finished Jul 01 10:46:49 AM PDT 24
Peak memory 198716 kb
Host smart-8fb234cc-9d0e-4f00-980c-400f96f0c2e7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3011470824 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_rand_intr_trigger
.3011470824
Directory /workspace/18.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/18.gpio_random_dout_din.3099596604
Short name T589
Test name
Test status
Simulation time 97515204 ps
CPU time 1.05 seconds
Started Jul 01 10:46:35 AM PDT 24
Finished Jul 01 10:46:43 AM PDT 24
Peak memory 196624 kb
Host smart-6a9d4778-c357-40f3-b7d7-2e29a7b1fdc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3099596604 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_random_dout_din.3099596604
Directory /workspace/18.gpio_random_dout_din/latest

Test location /workspace/coverage/default/18.gpio_random_dout_din_no_pullup_pulldown.1155741944
Short name T358
Test name
Test status
Simulation time 53541237 ps
CPU time 1.11 seconds
Started Jul 01 10:46:40 AM PDT 24
Finished Jul 01 10:46:44 AM PDT 24
Peak memory 196680 kb
Host smart-e56350c7-1566-41fa-b6a4-6d222474fda0
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1155741944 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_random_dout_din_no_pullu
p_pulldown.1155741944
Directory /workspace/18.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/18.gpio_random_long_reg_writes_reg_reads.2005263187
Short name T280
Test name
Test status
Simulation time 2433278761 ps
CPU time 3.9 seconds
Started Jul 01 10:46:36 AM PDT 24
Finished Jul 01 10:46:44 AM PDT 24
Peak memory 198564 kb
Host smart-66903e86-3dcc-48cb-be76-128e0f3890c5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2005263187 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_ra
ndom_long_reg_writes_reg_reads.2005263187
Directory /workspace/18.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/18.gpio_smoke.433409054
Short name T509
Test name
Test status
Simulation time 129115477 ps
CPU time 1.12 seconds
Started Jul 01 10:46:38 AM PDT 24
Finished Jul 01 10:46:44 AM PDT 24
Peak memory 196520 kb
Host smart-98656cd3-eb2f-488d-8db1-4fc2cf400d5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=433409054 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_smoke.433409054
Directory /workspace/18.gpio_smoke/latest

Test location /workspace/coverage/default/18.gpio_smoke_no_pullup_pulldown.93288205
Short name T424
Test name
Test status
Simulation time 43268087 ps
CPU time 1.21 seconds
Started Jul 01 10:46:39 AM PDT 24
Finished Jul 01 10:46:44 AM PDT 24
Peak memory 196468 kb
Host smart-06a93155-f635-4b9b-8d1c-8ee692551b32
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93288205 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_smoke_no_pullup_pulldown.93288205
Directory /workspace/18.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/18.gpio_stress_all.2069549497
Short name T299
Test name
Test status
Simulation time 1511759349 ps
CPU time 22.32 seconds
Started Jul 01 10:46:32 AM PDT 24
Finished Jul 01 10:46:55 AM PDT 24
Peak memory 198656 kb
Host smart-12e37ac6-185b-433b-8452-d9836ede0118
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2069549497 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.
gpio_stress_all.2069549497
Directory /workspace/18.gpio_stress_all/latest

Test location /workspace/coverage/default/18.gpio_stress_all_with_rand_reset.2169180894
Short name T355
Test name
Test status
Simulation time 111704084641 ps
CPU time 1014.39 seconds
Started Jul 01 10:46:37 AM PDT 24
Finished Jul 01 11:03:36 AM PDT 24
Peak memory 198876 kb
Host smart-8b8f04c5-0a0a-4ae6-9afc-304793fc96ad
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2169180894 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_stress_all_with_rand_reset.2169180894
Directory /workspace/18.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.gpio_alert_test.4143768366
Short name T700
Test name
Test status
Simulation time 19633421 ps
CPU time 0.59 seconds
Started Jul 01 10:46:44 AM PDT 24
Finished Jul 01 10:46:46 AM PDT 24
Peak memory 195324 kb
Host smart-26758bec-30d3-4a0c-9763-aff2e0c55c84
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4143768366 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_alert_test.4143768366
Directory /workspace/19.gpio_alert_test/latest

Test location /workspace/coverage/default/19.gpio_dout_din_regs_random_rw.3626737749
Short name T656
Test name
Test status
Simulation time 95441909 ps
CPU time 0.75 seconds
Started Jul 01 10:46:37 AM PDT 24
Finished Jul 01 10:46:42 AM PDT 24
Peak memory 195696 kb
Host smart-adc91b15-8487-46bb-b89a-82818690e5d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3626737749 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_dout_din_regs_random_rw.3626737749
Directory /workspace/19.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/19.gpio_filter_stress.1276246730
Short name T670
Test name
Test status
Simulation time 1349809971 ps
CPU time 16.51 seconds
Started Jul 01 10:46:34 AM PDT 24
Finished Jul 01 10:46:55 AM PDT 24
Peak memory 197640 kb
Host smart-83095deb-f26f-4aab-8e2f-5a33a69a9db4
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1276246730 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_filter_stre
ss.1276246730
Directory /workspace/19.gpio_filter_stress/latest

Test location /workspace/coverage/default/19.gpio_full_random.3937386278
Short name T343
Test name
Test status
Simulation time 22882059 ps
CPU time 0.65 seconds
Started Jul 01 10:46:59 AM PDT 24
Finished Jul 01 10:47:01 AM PDT 24
Peak memory 195888 kb
Host smart-4b19b5ee-dbb2-46be-a115-9d3f2b84c412
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3937386278 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_full_random.3937386278
Directory /workspace/19.gpio_full_random/latest

Test location /workspace/coverage/default/19.gpio_intr_rand_pgm.1932921635
Short name T574
Test name
Test status
Simulation time 53717265 ps
CPU time 0.89 seconds
Started Jul 01 10:46:41 AM PDT 24
Finished Jul 01 10:46:45 AM PDT 24
Peak memory 198116 kb
Host smart-d303c3c1-f956-4e4c-8107-0f91443f1ff7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1932921635 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_intr_rand_pgm.1932921635
Directory /workspace/19.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/19.gpio_intr_with_filter_rand_intr_event.4136642223
Short name T236
Test name
Test status
Simulation time 629427922 ps
CPU time 1.85 seconds
Started Jul 01 10:46:55 AM PDT 24
Finished Jul 01 10:46:58 AM PDT 24
Peak memory 198552 kb
Host smart-99c9fba0-cf4c-4b33-94a5-b4c41c2d27de
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4136642223 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 19.gpio_intr_with_filter_rand_intr_event.4136642223
Directory /workspace/19.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/19.gpio_rand_intr_trigger.927565091
Short name T616
Test name
Test status
Simulation time 269396908 ps
CPU time 2.52 seconds
Started Jul 01 10:47:00 AM PDT 24
Finished Jul 01 10:47:04 AM PDT 24
Peak memory 197664 kb
Host smart-506543d6-ab1a-48d0-8698-d12e5fef4f81
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=927565091 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_rand_intr_trigger.
927565091
Directory /workspace/19.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/19.gpio_random_dout_din.3747070706
Short name T473
Test name
Test status
Simulation time 346165193 ps
CPU time 1.12 seconds
Started Jul 01 10:47:11 AM PDT 24
Finished Jul 01 10:47:14 AM PDT 24
Peak memory 197260 kb
Host smart-5c597b77-202c-4a9f-a655-981ebbf8fe67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3747070706 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_random_dout_din.3747070706
Directory /workspace/19.gpio_random_dout_din/latest

Test location /workspace/coverage/default/19.gpio_random_dout_din_no_pullup_pulldown.2497253152
Short name T267
Test name
Test status
Simulation time 106388794 ps
CPU time 1.01 seconds
Started Jul 01 10:47:04 AM PDT 24
Finished Jul 01 10:47:06 AM PDT 24
Peak memory 197216 kb
Host smart-a7b55cdb-e979-4b8e-afc2-78720e841418
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2497253152 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_random_dout_din_no_pullu
p_pulldown.2497253152
Directory /workspace/19.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/19.gpio_random_long_reg_writes_reg_reads.3231521758
Short name T298
Test name
Test status
Simulation time 161636676 ps
CPU time 2.03 seconds
Started Jul 01 10:46:49 AM PDT 24
Finished Jul 01 10:46:52 AM PDT 24
Peak memory 198620 kb
Host smart-8b065bde-65da-4d9a-8107-44d8e51d2bae
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3231521758 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_ra
ndom_long_reg_writes_reg_reads.3231521758
Directory /workspace/19.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/19.gpio_smoke.1671300960
Short name T607
Test name
Test status
Simulation time 132159755 ps
CPU time 1.34 seconds
Started Jul 01 10:46:57 AM PDT 24
Finished Jul 01 10:46:59 AM PDT 24
Peak memory 197376 kb
Host smart-56fbebd5-c774-4f95-931a-874b6d376f69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1671300960 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_smoke.1671300960
Directory /workspace/19.gpio_smoke/latest

Test location /workspace/coverage/default/19.gpio_smoke_no_pullup_pulldown.2698261528
Short name T121
Test name
Test status
Simulation time 196939426 ps
CPU time 1.27 seconds
Started Jul 01 10:46:38 AM PDT 24
Finished Jul 01 10:46:43 AM PDT 24
Peak memory 198624 kb
Host smart-94137d68-abc1-42b0-962c-4a80385911c6
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2698261528 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_smoke_no_pullup_pulldown.2698261528
Directory /workspace/19.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/19.gpio_stress_all.2478465490
Short name T8
Test name
Test status
Simulation time 18860405116 ps
CPU time 75.41 seconds
Started Jul 01 10:46:49 AM PDT 24
Finished Jul 01 10:48:06 AM PDT 24
Peak memory 198796 kb
Host smart-b2442490-cc1a-464b-8df8-94ac2e7b6fa4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2478465490 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.
gpio_stress_all.2478465490
Directory /workspace/19.gpio_stress_all/latest

Test location /workspace/coverage/default/2.gpio_alert_test.3652724634
Short name T256
Test name
Test status
Simulation time 36794246 ps
CPU time 0.6 seconds
Started Jul 01 10:46:11 AM PDT 24
Finished Jul 01 10:46:13 AM PDT 24
Peak memory 195340 kb
Host smart-ca15c576-28ae-4a8c-934d-23bed3f5e381
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3652724634 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_alert_test.3652724634
Directory /workspace/2.gpio_alert_test/latest

Test location /workspace/coverage/default/2.gpio_dout_din_regs_random_rw.3405354783
Short name T554
Test name
Test status
Simulation time 17400244 ps
CPU time 0.64 seconds
Started Jul 01 10:46:02 AM PDT 24
Finished Jul 01 10:46:03 AM PDT 24
Peak memory 195388 kb
Host smart-31a5fb7e-5eb8-410e-ae2d-5f221cb775f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3405354783 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_dout_din_regs_random_rw.3405354783
Directory /workspace/2.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/2.gpio_filter_stress.635693350
Short name T602
Test name
Test status
Simulation time 165832953 ps
CPU time 4.14 seconds
Started Jul 01 10:46:30 AM PDT 24
Finished Jul 01 10:46:35 AM PDT 24
Peak memory 196452 kb
Host smart-bc2b9dad-80b7-43fe-ba18-201978258c68
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=635693350 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_filter_stress
.635693350
Directory /workspace/2.gpio_filter_stress/latest

Test location /workspace/coverage/default/2.gpio_full_random.2591429843
Short name T268
Test name
Test status
Simulation time 298634491 ps
CPU time 0.95 seconds
Started Jul 01 10:46:12 AM PDT 24
Finished Jul 01 10:46:15 AM PDT 24
Peak memory 197264 kb
Host smart-5cacb40a-19c0-441b-a881-eff705d7d935
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2591429843 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_full_random.2591429843
Directory /workspace/2.gpio_full_random/latest

Test location /workspace/coverage/default/2.gpio_intr_rand_pgm.4090873419
Short name T120
Test name
Test status
Simulation time 79124425 ps
CPU time 1.46 seconds
Started Jul 01 10:46:00 AM PDT 24
Finished Jul 01 10:46:01 AM PDT 24
Peak memory 198676 kb
Host smart-432dc042-065f-4fa7-ac6e-f57c12001708
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4090873419 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_intr_rand_pgm.4090873419
Directory /workspace/2.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/2.gpio_intr_with_filter_rand_intr_event.352362690
Short name T264
Test name
Test status
Simulation time 121565510 ps
CPU time 2.48 seconds
Started Jul 01 10:46:33 AM PDT 24
Finished Jul 01 10:46:37 AM PDT 24
Peak memory 198644 kb
Host smart-9639fa30-f930-4110-8c99-195903c99981
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=352362690 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 2.gpio_intr_with_filter_rand_intr_event.352362690
Directory /workspace/2.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/2.gpio_rand_intr_trigger.1062481020
Short name T184
Test name
Test status
Simulation time 230150841 ps
CPU time 1.38 seconds
Started Jul 01 10:46:03 AM PDT 24
Finished Jul 01 10:46:05 AM PDT 24
Peak memory 196844 kb
Host smart-4bfe4666-0433-42de-846e-73bc51b80802
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1062481020 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_rand_intr_trigger.
1062481020
Directory /workspace/2.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/2.gpio_random_dout_din.2561454391
Short name T525
Test name
Test status
Simulation time 22709780 ps
CPU time 0.69 seconds
Started Jul 01 10:46:33 AM PDT 24
Finished Jul 01 10:46:34 AM PDT 24
Peak memory 195908 kb
Host smart-7ccc7b04-b5ad-4061-9680-44919280a533
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2561454391 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_random_dout_din.2561454391
Directory /workspace/2.gpio_random_dout_din/latest

Test location /workspace/coverage/default/2.gpio_random_dout_din_no_pullup_pulldown.1707880513
Short name T496
Test name
Test status
Simulation time 197888792 ps
CPU time 0.66 seconds
Started Jul 01 10:46:11 AM PDT 24
Finished Jul 01 10:46:13 AM PDT 24
Peak memory 194924 kb
Host smart-3c1820a8-0492-472a-9e09-dd45ba049605
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1707880513 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_random_dout_din_no_pullup
_pulldown.1707880513
Directory /workspace/2.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/2.gpio_random_long_reg_writes_reg_reads.938731474
Short name T255
Test name
Test status
Simulation time 434305271 ps
CPU time 5.09 seconds
Started Jul 01 10:46:34 AM PDT 24
Finished Jul 01 10:46:42 AM PDT 24
Peak memory 198552 kb
Host smart-74279c8e-b618-472d-b4c8-6259567dc834
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=938731474 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_rand
om_long_reg_writes_reg_reads.938731474
Directory /workspace/2.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/2.gpio_sec_cm.3359615648
Short name T34
Test name
Test status
Simulation time 44336325 ps
CPU time 0.82 seconds
Started Jul 01 10:46:07 AM PDT 24
Finished Jul 01 10:46:09 AM PDT 24
Peak memory 214188 kb
Host smart-be5d76f9-c801-4f89-950c-10a092e88ff8
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3359615648 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_sec_cm.3359615648
Directory /workspace/2.gpio_sec_cm/latest

Test location /workspace/coverage/default/2.gpio_smoke.356016744
Short name T302
Test name
Test status
Simulation time 413566579 ps
CPU time 1.14 seconds
Started Jul 01 10:46:01 AM PDT 24
Finished Jul 01 10:46:03 AM PDT 24
Peak memory 197032 kb
Host smart-85b5694e-8f18-436e-84e3-05fbef2c3a81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=356016744 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_smoke.356016744
Directory /workspace/2.gpio_smoke/latest

Test location /workspace/coverage/default/2.gpio_smoke_no_pullup_pulldown.2617577030
Short name T390
Test name
Test status
Simulation time 186129864 ps
CPU time 1.33 seconds
Started Jul 01 10:46:03 AM PDT 24
Finished Jul 01 10:46:06 AM PDT 24
Peak memory 197412 kb
Host smart-7a2adccc-bcb8-4dca-b357-b6a6ec176060
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2617577030 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_smoke_no_pullup_pulldown.2617577030
Directory /workspace/2.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/2.gpio_stress_all.1222970393
Short name T291
Test name
Test status
Simulation time 4958579993 ps
CPU time 54.75 seconds
Started Jul 01 10:46:09 AM PDT 24
Finished Jul 01 10:47:05 AM PDT 24
Peak memory 198756 kb
Host smart-5e3eb3db-612b-4103-ae31-a3b64f96f236
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1222970393 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.g
pio_stress_all.1222970393
Directory /workspace/2.gpio_stress_all/latest

Test location /workspace/coverage/default/20.gpio_alert_test.3756353715
Short name T512
Test name
Test status
Simulation time 19596910 ps
CPU time 0.58 seconds
Started Jul 01 10:47:12 AM PDT 24
Finished Jul 01 10:47:14 AM PDT 24
Peak memory 194720 kb
Host smart-fa174c71-e087-443e-88e0-384725cb0da3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3756353715 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_alert_test.3756353715
Directory /workspace/20.gpio_alert_test/latest

Test location /workspace/coverage/default/20.gpio_dout_din_regs_random_rw.755576453
Short name T303
Test name
Test status
Simulation time 70212658 ps
CPU time 0.74 seconds
Started Jul 01 10:46:39 AM PDT 24
Finished Jul 01 10:46:43 AM PDT 24
Peak memory 195940 kb
Host smart-25a66f8f-9d27-4ab6-92f4-2982512e9367
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=755576453 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_dout_din_regs_random_rw.755576453
Directory /workspace/20.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/20.gpio_filter_stress.938732335
Short name T401
Test name
Test status
Simulation time 1800805383 ps
CPU time 16.21 seconds
Started Jul 01 10:46:44 AM PDT 24
Finished Jul 01 10:47:02 AM PDT 24
Peak memory 197468 kb
Host smart-11b143c2-4663-4d76-82a2-f51388574b20
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=938732335 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_filter_stres
s.938732335
Directory /workspace/20.gpio_filter_stress/latest

Test location /workspace/coverage/default/20.gpio_full_random.1188844724
Short name T701
Test name
Test status
Simulation time 21749872 ps
CPU time 0.65 seconds
Started Jul 01 10:46:41 AM PDT 24
Finished Jul 01 10:46:45 AM PDT 24
Peak memory 194856 kb
Host smart-f7ac284b-0ba7-403e-95dd-56d4c8699ee6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1188844724 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_full_random.1188844724
Directory /workspace/20.gpio_full_random/latest

Test location /workspace/coverage/default/20.gpio_intr_rand_pgm.1132846126
Short name T300
Test name
Test status
Simulation time 39577514 ps
CPU time 1.03 seconds
Started Jul 01 10:46:44 AM PDT 24
Finished Jul 01 10:46:47 AM PDT 24
Peak memory 196348 kb
Host smart-4fcb73da-9217-402c-ac71-13a3c0e3ee90
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1132846126 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_intr_rand_pgm.1132846126
Directory /workspace/20.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/20.gpio_intr_with_filter_rand_intr_event.3723313155
Short name T161
Test name
Test status
Simulation time 288374938 ps
CPU time 2.68 seconds
Started Jul 01 10:46:52 AM PDT 24
Finished Jul 01 10:46:56 AM PDT 24
Peak memory 198656 kb
Host smart-613cac7e-31fa-4a9e-b08e-9f2250ce9f86
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3723313155 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 20.gpio_intr_with_filter_rand_intr_event.3723313155
Directory /workspace/20.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/20.gpio_rand_intr_trigger.2500918368
Short name T578
Test name
Test status
Simulation time 143500793 ps
CPU time 2.61 seconds
Started Jul 01 10:46:37 AM PDT 24
Finished Jul 01 10:46:44 AM PDT 24
Peak memory 197872 kb
Host smart-8a0a7082-b81b-4854-beb7-84727aa88c32
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2500918368 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_rand_intr_trigger
.2500918368
Directory /workspace/20.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/20.gpio_random_dout_din.1358011624
Short name T441
Test name
Test status
Simulation time 41965174 ps
CPU time 0.73 seconds
Started Jul 01 10:46:44 AM PDT 24
Finished Jul 01 10:46:46 AM PDT 24
Peak memory 195868 kb
Host smart-03cb64c2-e54a-462f-922d-2355750f0788
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1358011624 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_random_dout_din.1358011624
Directory /workspace/20.gpio_random_dout_din/latest

Test location /workspace/coverage/default/20.gpio_random_dout_din_no_pullup_pulldown.1439226878
Short name T12
Test name
Test status
Simulation time 177480915 ps
CPU time 1.08 seconds
Started Jul 01 10:46:43 AM PDT 24
Finished Jul 01 10:46:46 AM PDT 24
Peak memory 197304 kb
Host smart-e494f9fd-7b6e-46b0-9f44-fa047d69e0bf
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1439226878 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_random_dout_din_no_pullu
p_pulldown.1439226878
Directory /workspace/20.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/20.gpio_random_long_reg_writes_reg_reads.967063733
Short name T106
Test name
Test status
Simulation time 100084170 ps
CPU time 1.92 seconds
Started Jul 01 10:46:49 AM PDT 24
Finished Jul 01 10:46:52 AM PDT 24
Peak memory 198520 kb
Host smart-a36dd67e-366f-43fe-ae50-93426c5b80a1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=967063733 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_ran
dom_long_reg_writes_reg_reads.967063733
Directory /workspace/20.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/20.gpio_smoke.3394142132
Short name T679
Test name
Test status
Simulation time 246024166 ps
CPU time 1.26 seconds
Started Jul 01 10:47:08 AM PDT 24
Finished Jul 01 10:47:10 AM PDT 24
Peak memory 197448 kb
Host smart-b2a150ab-b3fa-49fa-bbb1-a57c80b72cc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3394142132 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_smoke.3394142132
Directory /workspace/20.gpio_smoke/latest

Test location /workspace/coverage/default/20.gpio_smoke_no_pullup_pulldown.3768659495
Short name T448
Test name
Test status
Simulation time 46489868 ps
CPU time 1.28 seconds
Started Jul 01 10:47:10 AM PDT 24
Finished Jul 01 10:47:12 AM PDT 24
Peak memory 196140 kb
Host smart-65951bb0-22ed-47cf-93fa-7a686f2d45f8
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3768659495 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_smoke_no_pullup_pulldown.3768659495
Directory /workspace/20.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/20.gpio_stress_all.1467417902
Short name T150
Test name
Test status
Simulation time 16286832008 ps
CPU time 95.75 seconds
Started Jul 01 10:47:08 AM PDT 24
Finished Jul 01 10:48:45 AM PDT 24
Peak memory 198796 kb
Host smart-8d201ac0-b2c3-4fb1-ba5f-7d8e4d08bf97
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1467417902 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.
gpio_stress_all.1467417902
Directory /workspace/20.gpio_stress_all/latest

Test location /workspace/coverage/default/21.gpio_alert_test.2844185673
Short name T38
Test name
Test status
Simulation time 13387146 ps
CPU time 0.56 seconds
Started Jul 01 10:46:49 AM PDT 24
Finished Jul 01 10:46:51 AM PDT 24
Peak memory 194632 kb
Host smart-8015b478-9400-4028-9d73-d657424e5931
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2844185673 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_alert_test.2844185673
Directory /workspace/21.gpio_alert_test/latest

Test location /workspace/coverage/default/21.gpio_dout_din_regs_random_rw.2296035955
Short name T596
Test name
Test status
Simulation time 14155673 ps
CPU time 0.64 seconds
Started Jul 01 10:46:54 AM PDT 24
Finished Jul 01 10:46:56 AM PDT 24
Peak memory 195408 kb
Host smart-cab6c183-e6ac-481d-9e23-9ee5bdd5f240
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2296035955 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_dout_din_regs_random_rw.2296035955
Directory /workspace/21.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/21.gpio_filter_stress.713039450
Short name T146
Test name
Test status
Simulation time 143775293 ps
CPU time 5 seconds
Started Jul 01 10:46:57 AM PDT 24
Finished Jul 01 10:47:03 AM PDT 24
Peak memory 196344 kb
Host smart-5dce28e1-3008-4d41-9246-6155f1620a42
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=713039450 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_filter_stres
s.713039450
Directory /workspace/21.gpio_filter_stress/latest

Test location /workspace/coverage/default/21.gpio_full_random.4278213586
Short name T386
Test name
Test status
Simulation time 169021676 ps
CPU time 0.85 seconds
Started Jul 01 10:46:59 AM PDT 24
Finished Jul 01 10:47:01 AM PDT 24
Peak memory 196376 kb
Host smart-6de790e9-f639-431f-94bf-2c4c41d20d06
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4278213586 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_full_random.4278213586
Directory /workspace/21.gpio_full_random/latest

Test location /workspace/coverage/default/21.gpio_intr_rand_pgm.4170293834
Short name T369
Test name
Test status
Simulation time 33878772 ps
CPU time 0.87 seconds
Started Jul 01 10:47:04 AM PDT 24
Finished Jul 01 10:47:07 AM PDT 24
Peak memory 197384 kb
Host smart-7e6983d2-03df-4ca4-9d3d-0452c0f83ff3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4170293834 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_intr_rand_pgm.4170293834
Directory /workspace/21.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/21.gpio_intr_with_filter_rand_intr_event.1555739044
Short name T417
Test name
Test status
Simulation time 313050020 ps
CPU time 2.98 seconds
Started Jul 01 10:47:02 AM PDT 24
Finished Jul 01 10:47:06 AM PDT 24
Peak memory 198728 kb
Host smart-ad28914a-945d-4a1c-a412-e02d81dff2a5
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1555739044 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 21.gpio_intr_with_filter_rand_intr_event.1555739044
Directory /workspace/21.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/21.gpio_rand_intr_trigger.2949423016
Short name T695
Test name
Test status
Simulation time 125876113 ps
CPU time 2.12 seconds
Started Jul 01 10:46:54 AM PDT 24
Finished Jul 01 10:46:57 AM PDT 24
Peak memory 198588 kb
Host smart-1c4aa0e7-8cf5-4d09-8f88-07bd213f4c13
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2949423016 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_rand_intr_trigger
.2949423016
Directory /workspace/21.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/21.gpio_random_dout_din.2963147805
Short name T503
Test name
Test status
Simulation time 99929158 ps
CPU time 1.26 seconds
Started Jul 01 10:46:54 AM PDT 24
Finished Jul 01 10:46:57 AM PDT 24
Peak memory 197720 kb
Host smart-e7e3af56-8589-4066-b347-2127e3e1da9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2963147805 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_random_dout_din.2963147805
Directory /workspace/21.gpio_random_dout_din/latest

Test location /workspace/coverage/default/21.gpio_random_dout_din_no_pullup_pulldown.3818937165
Short name T564
Test name
Test status
Simulation time 64999412 ps
CPU time 1.15 seconds
Started Jul 01 10:46:47 AM PDT 24
Finished Jul 01 10:46:49 AM PDT 24
Peak memory 197748 kb
Host smart-9aa51b22-4b70-4be9-82b6-ad08adc3eeb0
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3818937165 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_random_dout_din_no_pullu
p_pulldown.3818937165
Directory /workspace/21.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/21.gpio_smoke.2723800350
Short name T537
Test name
Test status
Simulation time 87925013 ps
CPU time 1.29 seconds
Started Jul 01 10:47:06 AM PDT 24
Finished Jul 01 10:47:09 AM PDT 24
Peak memory 198700 kb
Host smart-3185956c-e2f4-40da-8879-46330c70b44e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2723800350 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_smoke.2723800350
Directory /workspace/21.gpio_smoke/latest

Test location /workspace/coverage/default/21.gpio_smoke_no_pullup_pulldown.2379715694
Short name T360
Test name
Test status
Simulation time 279026308 ps
CPU time 1.29 seconds
Started Jul 01 10:46:37 AM PDT 24
Finished Jul 01 10:46:43 AM PDT 24
Peak memory 197504 kb
Host smart-ffaabbad-8f20-42d3-864b-be2d61206b7b
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2379715694 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_smoke_no_pullup_pulldown.2379715694
Directory /workspace/21.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/21.gpio_stress_all.4073553472
Short name T110
Test name
Test status
Simulation time 4147082481 ps
CPU time 96.91 seconds
Started Jul 01 10:46:50 AM PDT 24
Finished Jul 01 10:48:37 AM PDT 24
Peak memory 198760 kb
Host smart-593b67cd-404a-4a13-9567-8cea1fedf0b6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4073553472 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.
gpio_stress_all.4073553472
Directory /workspace/21.gpio_stress_all/latest

Test location /workspace/coverage/default/21.gpio_stress_all_with_rand_reset.1101283452
Short name T65
Test name
Test status
Simulation time 205749153891 ps
CPU time 536.23 seconds
Started Jul 01 10:46:59 AM PDT 24
Finished Jul 01 10:55:57 AM PDT 24
Peak memory 207084 kb
Host smart-0a60041d-0df2-4e92-9fea-f1c62d10fee6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1101283452 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_stress_all_with_rand_reset.1101283452
Directory /workspace/21.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.gpio_alert_test.869236625
Short name T547
Test name
Test status
Simulation time 39388875 ps
CPU time 0.58 seconds
Started Jul 01 10:46:54 AM PDT 24
Finished Jul 01 10:46:55 AM PDT 24
Peak memory 194648 kb
Host smart-c6ddfb24-14e8-4fa7-ad8c-c4c7c3ebac2c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=869236625 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_alert_test.869236625
Directory /workspace/22.gpio_alert_test/latest

Test location /workspace/coverage/default/22.gpio_dout_din_regs_random_rw.2779075736
Short name T531
Test name
Test status
Simulation time 93373808 ps
CPU time 0.71 seconds
Started Jul 01 10:46:39 AM PDT 24
Finished Jul 01 10:46:43 AM PDT 24
Peak memory 195820 kb
Host smart-1d731f7c-f87b-42a0-8a8b-021a855e1fa6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2779075736 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_dout_din_regs_random_rw.2779075736
Directory /workspace/22.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/22.gpio_filter_stress.1200983576
Short name T53
Test name
Test status
Simulation time 1204077725 ps
CPU time 10.57 seconds
Started Jul 01 10:47:15 AM PDT 24
Finished Jul 01 10:47:27 AM PDT 24
Peak memory 198680 kb
Host smart-22dccd55-2fe5-456f-9415-3a3083dde78f
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1200983576 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_filter_stre
ss.1200983576
Directory /workspace/22.gpio_filter_stress/latest

Test location /workspace/coverage/default/22.gpio_full_random.1817456013
Short name T380
Test name
Test status
Simulation time 205130788 ps
CPU time 0.83 seconds
Started Jul 01 10:46:38 AM PDT 24
Finished Jul 01 10:46:43 AM PDT 24
Peak memory 197416 kb
Host smart-2c282380-2420-4121-a32c-c112c98ce9e0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1817456013 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_full_random.1817456013
Directory /workspace/22.gpio_full_random/latest

Test location /workspace/coverage/default/22.gpio_intr_rand_pgm.2767787897
Short name T687
Test name
Test status
Simulation time 358076343 ps
CPU time 1.28 seconds
Started Jul 01 10:46:49 AM PDT 24
Finished Jul 01 10:46:51 AM PDT 24
Peak memory 196508 kb
Host smart-8f711493-70ef-4c91-9e34-c3caf3740d2b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2767787897 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_intr_rand_pgm.2767787897
Directory /workspace/22.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/22.gpio_intr_with_filter_rand_intr_event.2214604767
Short name T135
Test name
Test status
Simulation time 356499042 ps
CPU time 3.57 seconds
Started Jul 01 10:46:36 AM PDT 24
Finished Jul 01 10:46:44 AM PDT 24
Peak memory 198620 kb
Host smart-e8376b3d-68a1-40b6-8594-d9735158f126
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2214604767 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 22.gpio_intr_with_filter_rand_intr_event.2214604767
Directory /workspace/22.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/22.gpio_rand_intr_trigger.646078503
Short name T282
Test name
Test status
Simulation time 239104514 ps
CPU time 2.11 seconds
Started Jul 01 10:46:40 AM PDT 24
Finished Jul 01 10:46:45 AM PDT 24
Peak memory 198752 kb
Host smart-13420f46-3856-4058-b231-16bea0445172
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=646078503 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_rand_intr_trigger.
646078503
Directory /workspace/22.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/22.gpio_random_dout_din.3954422063
Short name T309
Test name
Test status
Simulation time 558653367 ps
CPU time 0.95 seconds
Started Jul 01 10:46:43 AM PDT 24
Finished Jul 01 10:46:46 AM PDT 24
Peak memory 196668 kb
Host smart-3b770ca7-44c3-4102-b936-7d1631f31732
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3954422063 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_random_dout_din.3954422063
Directory /workspace/22.gpio_random_dout_din/latest

Test location /workspace/coverage/default/22.gpio_random_dout_din_no_pullup_pulldown.2059461880
Short name T631
Test name
Test status
Simulation time 241690045 ps
CPU time 1.43 seconds
Started Jul 01 10:46:46 AM PDT 24
Finished Jul 01 10:46:48 AM PDT 24
Peak memory 197760 kb
Host smart-d7e95f11-95d5-45d6-99a0-8349280c65d0
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2059461880 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_random_dout_din_no_pullu
p_pulldown.2059461880
Directory /workspace/22.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/22.gpio_random_long_reg_writes_reg_reads.2112826784
Short name T197
Test name
Test status
Simulation time 776086441 ps
CPU time 3.22 seconds
Started Jul 01 10:47:17 AM PDT 24
Finished Jul 01 10:47:21 AM PDT 24
Peak memory 198700 kb
Host smart-e3f81808-c4cf-4b89-8f18-314223c6358e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2112826784 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_ra
ndom_long_reg_writes_reg_reads.2112826784
Directory /workspace/22.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/22.gpio_smoke.962348123
Short name T164
Test name
Test status
Simulation time 116979089 ps
CPU time 0.9 seconds
Started Jul 01 10:46:47 AM PDT 24
Finished Jul 01 10:46:48 AM PDT 24
Peak memory 197880 kb
Host smart-3c17dcae-51eb-432c-b3a6-63bed7d472d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=962348123 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_smoke.962348123
Directory /workspace/22.gpio_smoke/latest

Test location /workspace/coverage/default/22.gpio_smoke_no_pullup_pulldown.4153345714
Short name T680
Test name
Test status
Simulation time 72502696 ps
CPU time 1.27 seconds
Started Jul 01 10:46:35 AM PDT 24
Finished Jul 01 10:46:40 AM PDT 24
Peak memory 197476 kb
Host smart-4a9511f7-cfe2-44e2-9044-a7c8ec0ba3e2
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4153345714 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_smoke_no_pullup_pulldown.4153345714
Directory /workspace/22.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/22.gpio_stress_all.4018019568
Short name T366
Test name
Test status
Simulation time 4964439532 ps
CPU time 76.71 seconds
Started Jul 01 10:46:51 AM PDT 24
Finished Jul 01 10:48:09 AM PDT 24
Peak memory 198688 kb
Host smart-d5e74904-b0b3-4a1b-a7d1-c84601114287
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4018019568 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.
gpio_stress_all.4018019568
Directory /workspace/22.gpio_stress_all/latest

Test location /workspace/coverage/default/23.gpio_alert_test.2990933019
Short name T127
Test name
Test status
Simulation time 28736769 ps
CPU time 0.56 seconds
Started Jul 01 10:46:51 AM PDT 24
Finished Jul 01 10:46:53 AM PDT 24
Peak memory 195336 kb
Host smart-2e44e0f7-7c2f-4412-b663-d587fd40f182
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2990933019 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_alert_test.2990933019
Directory /workspace/23.gpio_alert_test/latest

Test location /workspace/coverage/default/23.gpio_dout_din_regs_random_rw.4233626068
Short name T364
Test name
Test status
Simulation time 145194435 ps
CPU time 0.83 seconds
Started Jul 01 10:46:54 AM PDT 24
Finished Jul 01 10:46:57 AM PDT 24
Peak memory 196528 kb
Host smart-52148d36-cd6a-43c2-bed0-584931b592f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4233626068 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_dout_din_regs_random_rw.4233626068
Directory /workspace/23.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/23.gpio_filter_stress.358819718
Short name T665
Test name
Test status
Simulation time 171991393 ps
CPU time 8.69 seconds
Started Jul 01 10:46:51 AM PDT 24
Finished Jul 01 10:47:00 AM PDT 24
Peak memory 197556 kb
Host smart-ead20d8f-7844-47ee-95f2-dacfc692aec9
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=358819718 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_filter_stres
s.358819718
Directory /workspace/23.gpio_filter_stress/latest

Test location /workspace/coverage/default/23.gpio_full_random.3001438722
Short name T16
Test name
Test status
Simulation time 256384643 ps
CPU time 0.82 seconds
Started Jul 01 10:46:55 AM PDT 24
Finished Jul 01 10:46:57 AM PDT 24
Peak memory 196612 kb
Host smart-441096df-668f-4c15-9b7a-00effe4d484d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3001438722 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_full_random.3001438722
Directory /workspace/23.gpio_full_random/latest

Test location /workspace/coverage/default/23.gpio_intr_rand_pgm.3513783918
Short name T498
Test name
Test status
Simulation time 36414710 ps
CPU time 0.85 seconds
Started Jul 01 10:46:48 AM PDT 24
Finished Jul 01 10:46:50 AM PDT 24
Peak memory 196848 kb
Host smart-4c127057-1159-403d-a105-98164b906cf4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3513783918 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_intr_rand_pgm.3513783918
Directory /workspace/23.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/23.gpio_intr_with_filter_rand_intr_event.3788272725
Short name T399
Test name
Test status
Simulation time 150071470 ps
CPU time 1.67 seconds
Started Jul 01 10:47:12 AM PDT 24
Finished Jul 01 10:47:15 AM PDT 24
Peak memory 198760 kb
Host smart-f506fcba-7ede-40a0-8662-c48f754b1f73
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3788272725 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 23.gpio_intr_with_filter_rand_intr_event.3788272725
Directory /workspace/23.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/23.gpio_rand_intr_trigger.461078384
Short name T153
Test name
Test status
Simulation time 78356985 ps
CPU time 2.16 seconds
Started Jul 01 10:47:10 AM PDT 24
Finished Jul 01 10:47:12 AM PDT 24
Peak memory 198536 kb
Host smart-cc4b5179-de34-4003-988f-0cbf9ad71793
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=461078384 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_rand_intr_trigger.
461078384
Directory /workspace/23.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/23.gpio_random_dout_din.1768971917
Short name T435
Test name
Test status
Simulation time 205694096 ps
CPU time 1.15 seconds
Started Jul 01 10:46:45 AM PDT 24
Finished Jul 01 10:46:47 AM PDT 24
Peak memory 196708 kb
Host smart-93e9b687-b016-4078-86f7-b1c951140937
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1768971917 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_random_dout_din.1768971917
Directory /workspace/23.gpio_random_dout_din/latest

Test location /workspace/coverage/default/23.gpio_random_dout_din_no_pullup_pulldown.1445579491
Short name T622
Test name
Test status
Simulation time 20147195 ps
CPU time 0.7 seconds
Started Jul 01 10:46:46 AM PDT 24
Finished Jul 01 10:46:48 AM PDT 24
Peak memory 195012 kb
Host smart-e49a2306-67dd-4382-b776-da04546f1fe4
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1445579491 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_random_dout_din_no_pullu
p_pulldown.1445579491
Directory /workspace/23.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/23.gpio_random_long_reg_writes_reg_reads.533757250
Short name T396
Test name
Test status
Simulation time 324115198 ps
CPU time 5.21 seconds
Started Jul 01 10:46:56 AM PDT 24
Finished Jul 01 10:47:02 AM PDT 24
Peak memory 198584 kb
Host smart-4ad90f2d-4e77-4856-a6d5-345f877a4bc7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=533757250 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_ran
dom_long_reg_writes_reg_reads.533757250
Directory /workspace/23.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/23.gpio_smoke.1166112895
Short name T492
Test name
Test status
Simulation time 83468491 ps
CPU time 1.25 seconds
Started Jul 01 10:47:05 AM PDT 24
Finished Jul 01 10:47:08 AM PDT 24
Peak memory 198552 kb
Host smart-651c5bd3-77dd-48e6-9c5d-ee7eec6acf8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1166112895 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_smoke.1166112895
Directory /workspace/23.gpio_smoke/latest

Test location /workspace/coverage/default/23.gpio_smoke_no_pullup_pulldown.1837408490
Short name T226
Test name
Test status
Simulation time 59138813 ps
CPU time 1.09 seconds
Started Jul 01 10:46:46 AM PDT 24
Finished Jul 01 10:46:48 AM PDT 24
Peak memory 196292 kb
Host smart-16331e0f-4ddd-4d0f-b5c5-bb64cc2d7911
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1837408490 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_smoke_no_pullup_pulldown.1837408490
Directory /workspace/23.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/23.gpio_stress_all.3973073437
Short name T704
Test name
Test status
Simulation time 8546039583 ps
CPU time 116.01 seconds
Started Jul 01 10:47:22 AM PDT 24
Finished Jul 01 10:49:19 AM PDT 24
Peak memory 198792 kb
Host smart-6e754bdc-0fa4-4978-b9a5-43631ace0f7b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3973073437 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.
gpio_stress_all.3973073437
Directory /workspace/23.gpio_stress_all/latest

Test location /workspace/coverage/default/23.gpio_stress_all_with_rand_reset.1029690287
Short name T559
Test name
Test status
Simulation time 35802932782 ps
CPU time 930.69 seconds
Started Jul 01 10:46:47 AM PDT 24
Finished Jul 01 11:02:19 AM PDT 24
Peak memory 198904 kb
Host smart-3f0d08d0-9105-46b0-8762-1d8b5512eaf1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1029690287 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_stress_all_with_rand_reset.1029690287
Directory /workspace/23.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.gpio_alert_test.3755147129
Short name T123
Test name
Test status
Simulation time 14341540 ps
CPU time 0.59 seconds
Started Jul 01 10:47:05 AM PDT 24
Finished Jul 01 10:47:07 AM PDT 24
Peak memory 195320 kb
Host smart-93a96ff2-cef8-4464-98c6-6a699255bbcf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3755147129 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_alert_test.3755147129
Directory /workspace/24.gpio_alert_test/latest

Test location /workspace/coverage/default/24.gpio_dout_din_regs_random_rw.3932392114
Short name T201
Test name
Test status
Simulation time 40602261 ps
CPU time 0.86 seconds
Started Jul 01 10:47:15 AM PDT 24
Finished Jul 01 10:47:17 AM PDT 24
Peak memory 195780 kb
Host smart-5643f217-7897-4e49-a373-5fb50814da46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3932392114 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_dout_din_regs_random_rw.3932392114
Directory /workspace/24.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/24.gpio_filter_stress.2394001218
Short name T633
Test name
Test status
Simulation time 300165602 ps
CPU time 10.44 seconds
Started Jul 01 10:46:55 AM PDT 24
Finished Jul 01 10:47:07 AM PDT 24
Peak memory 197092 kb
Host smart-b3199061-8674-408b-9aa9-79d4153bf7c3
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2394001218 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_filter_stre
ss.2394001218
Directory /workspace/24.gpio_filter_stress/latest

Test location /workspace/coverage/default/24.gpio_full_random.2348776317
Short name T180
Test name
Test status
Simulation time 133013421 ps
CPU time 0.63 seconds
Started Jul 01 10:46:47 AM PDT 24
Finished Jul 01 10:46:48 AM PDT 24
Peak memory 195064 kb
Host smart-f16edddd-7ee3-42ef-ad59-d1e44be3ed85
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2348776317 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_full_random.2348776317
Directory /workspace/24.gpio_full_random/latest

Test location /workspace/coverage/default/24.gpio_intr_rand_pgm.4232233302
Short name T205
Test name
Test status
Simulation time 79228031 ps
CPU time 1.37 seconds
Started Jul 01 10:46:54 AM PDT 24
Finished Jul 01 10:46:57 AM PDT 24
Peak memory 197620 kb
Host smart-9fd849ae-41f2-4adf-bdac-35ece3883f71
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4232233302 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_intr_rand_pgm.4232233302
Directory /workspace/24.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/24.gpio_intr_with_filter_rand_intr_event.709895675
Short name T132
Test name
Test status
Simulation time 143735925 ps
CPU time 2.71 seconds
Started Jul 01 10:46:55 AM PDT 24
Finished Jul 01 10:46:59 AM PDT 24
Peak memory 198664 kb
Host smart-24ccc8ef-b88a-4041-9a69-b8b3d8f6ff4a
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=709895675 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 24.gpio_intr_with_filter_rand_intr_event.709895675
Directory /workspace/24.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/24.gpio_rand_intr_trigger.970952276
Short name T71
Test name
Test status
Simulation time 82828642 ps
CPU time 2.3 seconds
Started Jul 01 10:46:58 AM PDT 24
Finished Jul 01 10:47:01 AM PDT 24
Peak memory 197324 kb
Host smart-6b9adc98-23c6-4d73-90ec-55e3520123e8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=970952276 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_rand_intr_trigger.
970952276
Directory /workspace/24.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/24.gpio_random_dout_din.1885454796
Short name T530
Test name
Test status
Simulation time 188877604 ps
CPU time 1.18 seconds
Started Jul 01 10:46:59 AM PDT 24
Finished Jul 01 10:47:02 AM PDT 24
Peak memory 196600 kb
Host smart-0eccd922-955c-4920-9dcb-6fed9c9210ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1885454796 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_random_dout_din.1885454796
Directory /workspace/24.gpio_random_dout_din/latest

Test location /workspace/coverage/default/24.gpio_random_dout_din_no_pullup_pulldown.3720437191
Short name T660
Test name
Test status
Simulation time 217237395 ps
CPU time 1.28 seconds
Started Jul 01 10:47:08 AM PDT 24
Finished Jul 01 10:47:11 AM PDT 24
Peak memory 197584 kb
Host smart-731c5de2-09f6-416e-9a0f-a6418450ea45
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3720437191 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_random_dout_din_no_pullu
p_pulldown.3720437191
Directory /workspace/24.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/24.gpio_random_long_reg_writes_reg_reads.3721028449
Short name T520
Test name
Test status
Simulation time 2994960610 ps
CPU time 5.45 seconds
Started Jul 01 10:47:04 AM PDT 24
Finished Jul 01 10:47:12 AM PDT 24
Peak memory 198716 kb
Host smart-900a3f70-934e-40c2-a64e-ef64ed631aa1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3721028449 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_ra
ndom_long_reg_writes_reg_reads.3721028449
Directory /workspace/24.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/24.gpio_smoke.2304928160
Short name T257
Test name
Test status
Simulation time 194096153 ps
CPU time 1.17 seconds
Started Jul 01 10:47:05 AM PDT 24
Finished Jul 01 10:47:08 AM PDT 24
Peak memory 196516 kb
Host smart-b43f2143-ec87-4bd9-87c4-0ade0df09b57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2304928160 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_smoke.2304928160
Directory /workspace/24.gpio_smoke/latest

Test location /workspace/coverage/default/24.gpio_smoke_no_pullup_pulldown.1926515719
Short name T666
Test name
Test status
Simulation time 28258209 ps
CPU time 0.82 seconds
Started Jul 01 10:46:49 AM PDT 24
Finished Jul 01 10:46:51 AM PDT 24
Peak memory 195724 kb
Host smart-1f0cfa10-2c3d-4714-8903-dd5c67502264
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1926515719 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_smoke_no_pullup_pulldown.1926515719
Directory /workspace/24.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/24.gpio_stress_all.1230181947
Short name T190
Test name
Test status
Simulation time 54498095639 ps
CPU time 186.78 seconds
Started Jul 01 10:47:11 AM PDT 24
Finished Jul 01 10:50:20 AM PDT 24
Peak memory 198784 kb
Host smart-5d593c27-58b5-4e0c-bf5b-97b9f71f99a9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1230181947 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.
gpio_stress_all.1230181947
Directory /workspace/24.gpio_stress_all/latest

Test location /workspace/coverage/default/24.gpio_stress_all_with_rand_reset.1220883151
Short name T59
Test name
Test status
Simulation time 13557570253 ps
CPU time 396.09 seconds
Started Jul 01 10:46:55 AM PDT 24
Finished Jul 01 10:53:33 AM PDT 24
Peak memory 198856 kb
Host smart-725d3a8d-935f-4e8d-8f36-97f559d9aa8b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1220883151 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_stress_all_with_rand_reset.1220883151
Directory /workspace/24.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.gpio_alert_test.3372473616
Short name T556
Test name
Test status
Simulation time 24051124 ps
CPU time 0.56 seconds
Started Jul 01 10:47:04 AM PDT 24
Finished Jul 01 10:47:06 AM PDT 24
Peak memory 194604 kb
Host smart-6ac73701-3b42-4a69-bcca-fac6ca00c498
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3372473616 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_alert_test.3372473616
Directory /workspace/25.gpio_alert_test/latest

Test location /workspace/coverage/default/25.gpio_dout_din_regs_random_rw.183311546
Short name T249
Test name
Test status
Simulation time 281152500 ps
CPU time 0.8 seconds
Started Jul 01 10:46:54 AM PDT 24
Finished Jul 01 10:46:57 AM PDT 24
Peak memory 195964 kb
Host smart-df93226a-1b87-4fd9-bd22-1fa2cb1564f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=183311546 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_dout_din_regs_random_rw.183311546
Directory /workspace/25.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/25.gpio_filter_stress.4082842309
Short name T524
Test name
Test status
Simulation time 5316283449 ps
CPU time 25.18 seconds
Started Jul 01 10:46:56 AM PDT 24
Finished Jul 01 10:47:22 AM PDT 24
Peak memory 197520 kb
Host smart-87c057ec-8903-4ffa-a095-b2ac92782db9
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4082842309 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_filter_stre
ss.4082842309
Directory /workspace/25.gpio_filter_stress/latest

Test location /workspace/coverage/default/25.gpio_full_random.1920224578
Short name T10
Test name
Test status
Simulation time 71085173 ps
CPU time 0.94 seconds
Started Jul 01 10:46:50 AM PDT 24
Finished Jul 01 10:46:52 AM PDT 24
Peak memory 196684 kb
Host smart-314b7f06-72cb-467d-8520-867cff722081
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1920224578 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_full_random.1920224578
Directory /workspace/25.gpio_full_random/latest

Test location /workspace/coverage/default/25.gpio_intr_rand_pgm.4130516635
Short name T188
Test name
Test status
Simulation time 193942279 ps
CPU time 1.25 seconds
Started Jul 01 10:47:01 AM PDT 24
Finished Jul 01 10:47:04 AM PDT 24
Peak memory 196380 kb
Host smart-4111036e-5c22-4fa1-965a-d9a2ac83a8ef
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4130516635 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_intr_rand_pgm.4130516635
Directory /workspace/25.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/25.gpio_intr_with_filter_rand_intr_event.187265497
Short name T69
Test name
Test status
Simulation time 113130526 ps
CPU time 1.27 seconds
Started Jul 01 10:46:59 AM PDT 24
Finished Jul 01 10:47:02 AM PDT 24
Peak memory 197292 kb
Host smart-1594da4a-bd2c-4440-9508-3e8e6322794b
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=187265497 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 25.gpio_intr_with_filter_rand_intr_event.187265497
Directory /workspace/25.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/25.gpio_rand_intr_trigger.786112274
Short name T225
Test name
Test status
Simulation time 105885651 ps
CPU time 1.99 seconds
Started Jul 01 10:47:03 AM PDT 24
Finished Jul 01 10:47:06 AM PDT 24
Peak memory 196440 kb
Host smart-3ce9022f-ed38-427b-a39c-c9937e776945
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=786112274 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_rand_intr_trigger.
786112274
Directory /workspace/25.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/25.gpio_random_dout_din.3491666724
Short name T321
Test name
Test status
Simulation time 104908908 ps
CPU time 0.9 seconds
Started Jul 01 10:46:53 AM PDT 24
Finished Jul 01 10:46:55 AM PDT 24
Peak memory 197220 kb
Host smart-d8a7dd70-39b7-4904-90c6-c468cdc161bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3491666724 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_random_dout_din.3491666724
Directory /workspace/25.gpio_random_dout_din/latest

Test location /workspace/coverage/default/25.gpio_random_dout_din_no_pullup_pulldown.862267035
Short name T624
Test name
Test status
Simulation time 43659785 ps
CPU time 1 seconds
Started Jul 01 10:46:51 AM PDT 24
Finished Jul 01 10:46:53 AM PDT 24
Peak memory 196688 kb
Host smart-91cadb77-f3e7-45c5-9fe6-00330f48eafd
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=862267035 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_random_dout_din_no_pullup
_pulldown.862267035
Directory /workspace/25.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/25.gpio_random_long_reg_writes_reg_reads.817589462
Short name T23
Test name
Test status
Simulation time 1450881228 ps
CPU time 5.01 seconds
Started Jul 01 10:46:56 AM PDT 24
Finished Jul 01 10:47:02 AM PDT 24
Peak memory 198600 kb
Host smart-94a9e750-8ed1-4465-9cff-027f0d63b381
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=817589462 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_ran
dom_long_reg_writes_reg_reads.817589462
Directory /workspace/25.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/25.gpio_smoke.2418823488
Short name T131
Test name
Test status
Simulation time 52088296 ps
CPU time 1.12 seconds
Started Jul 01 10:46:53 AM PDT 24
Finished Jul 01 10:46:55 AM PDT 24
Peak memory 196412 kb
Host smart-3314a38b-4c4a-4fb9-afc3-9235f3ab858c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2418823488 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_smoke.2418823488
Directory /workspace/25.gpio_smoke/latest

Test location /workspace/coverage/default/25.gpio_smoke_no_pullup_pulldown.1768545902
Short name T199
Test name
Test status
Simulation time 272414414 ps
CPU time 1.1 seconds
Started Jul 01 10:46:58 AM PDT 24
Finished Jul 01 10:47:00 AM PDT 24
Peak memory 196096 kb
Host smart-a7aaaabb-b112-4860-9c46-a1f5e4f0cdc0
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1768545902 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_smoke_no_pullup_pulldown.1768545902
Directory /workspace/25.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/25.gpio_stress_all.3811639270
Short name T429
Test name
Test status
Simulation time 39688538545 ps
CPU time 129.05 seconds
Started Jul 01 10:46:53 AM PDT 24
Finished Jul 01 10:49:03 AM PDT 24
Peak memory 198724 kb
Host smart-10388bd7-c7cd-415f-90dc-b818e785b7c0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3811639270 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.
gpio_stress_all.3811639270
Directory /workspace/25.gpio_stress_all/latest

Test location /workspace/coverage/default/25.gpio_stress_all_with_rand_reset.3291448572
Short name T61
Test name
Test status
Simulation time 83340922543 ps
CPU time 971.59 seconds
Started Jul 01 10:46:49 AM PDT 24
Finished Jul 01 11:03:02 AM PDT 24
Peak memory 198892 kb
Host smart-d2c73063-8456-45a0-91ee-20fd375c3ae4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3291448572 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_stress_all_with_rand_reset.3291448572
Directory /workspace/25.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.gpio_alert_test.3075595813
Short name T221
Test name
Test status
Simulation time 26474640 ps
CPU time 0.59 seconds
Started Jul 01 10:46:48 AM PDT 24
Finished Jul 01 10:46:49 AM PDT 24
Peak memory 195360 kb
Host smart-32ebf8b1-d8b1-4fe1-88aa-0183da7f5d28
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3075595813 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_alert_test.3075595813
Directory /workspace/26.gpio_alert_test/latest

Test location /workspace/coverage/default/26.gpio_dout_din_regs_random_rw.2146793177
Short name T354
Test name
Test status
Simulation time 165780457 ps
CPU time 0.89 seconds
Started Jul 01 10:46:53 AM PDT 24
Finished Jul 01 10:46:55 AM PDT 24
Peak memory 197124 kb
Host smart-9f0386d2-488d-4030-a9c0-fc6fb2c3d299
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2146793177 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_dout_din_regs_random_rw.2146793177
Directory /workspace/26.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/26.gpio_filter_stress.1164796281
Short name T191
Test name
Test status
Simulation time 9678471318 ps
CPU time 25.3 seconds
Started Jul 01 10:46:47 AM PDT 24
Finished Jul 01 10:47:13 AM PDT 24
Peak memory 198764 kb
Host smart-29015731-a68d-4905-8e28-541693934fab
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1164796281 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_filter_stre
ss.1164796281
Directory /workspace/26.gpio_filter_stress/latest

Test location /workspace/coverage/default/26.gpio_full_random.4265496311
Short name T307
Test name
Test status
Simulation time 221550302 ps
CPU time 0.93 seconds
Started Jul 01 10:47:04 AM PDT 24
Finished Jul 01 10:47:07 AM PDT 24
Peak memory 198292 kb
Host smart-d0efb6cd-397c-4152-b23b-ea251e5d6234
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4265496311 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_full_random.4265496311
Directory /workspace/26.gpio_full_random/latest

Test location /workspace/coverage/default/26.gpio_intr_rand_pgm.310482213
Short name T669
Test name
Test status
Simulation time 16691917 ps
CPU time 0.65 seconds
Started Jul 01 10:47:04 AM PDT 24
Finished Jul 01 10:47:06 AM PDT 24
Peak memory 194940 kb
Host smart-32a39628-9638-4c7a-a213-6c5ebb0752fd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=310482213 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_intr_rand_pgm.310482213
Directory /workspace/26.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/26.gpio_intr_with_filter_rand_intr_event.978942951
Short name T676
Test name
Test status
Simulation time 55610961 ps
CPU time 1.25 seconds
Started Jul 01 10:47:03 AM PDT 24
Finished Jul 01 10:47:06 AM PDT 24
Peak memory 198716 kb
Host smart-870f7628-b6f1-42b4-bf38-b959bde395e7
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=978942951 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 26.gpio_intr_with_filter_rand_intr_event.978942951
Directory /workspace/26.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/26.gpio_rand_intr_trigger.3371449973
Short name T324
Test name
Test status
Simulation time 179391073 ps
CPU time 2.2 seconds
Started Jul 01 10:46:48 AM PDT 24
Finished Jul 01 10:46:51 AM PDT 24
Peak memory 198720 kb
Host smart-ee066991-e0ef-4441-94ba-0189c18d0215
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3371449973 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_rand_intr_trigger
.3371449973
Directory /workspace/26.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/26.gpio_random_dout_din.791023248
Short name T189
Test name
Test status
Simulation time 20787904 ps
CPU time 0.77 seconds
Started Jul 01 10:47:00 AM PDT 24
Finished Jul 01 10:47:02 AM PDT 24
Peak memory 195748 kb
Host smart-fc04bd5e-409b-448f-8321-cdb1c8cf58ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=791023248 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_random_dout_din.791023248
Directory /workspace/26.gpio_random_dout_din/latest

Test location /workspace/coverage/default/26.gpio_random_dout_din_no_pullup_pulldown.1821745602
Short name T645
Test name
Test status
Simulation time 36448874 ps
CPU time 1.3 seconds
Started Jul 01 10:46:49 AM PDT 24
Finished Jul 01 10:46:51 AM PDT 24
Peak memory 197752 kb
Host smart-87c6d5ef-4555-4db9-a141-c544ba9a0cd8
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1821745602 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_random_dout_din_no_pullu
p_pulldown.1821745602
Directory /workspace/26.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/26.gpio_random_long_reg_writes_reg_reads.63109734
Short name T316
Test name
Test status
Simulation time 70349754 ps
CPU time 2.96 seconds
Started Jul 01 10:46:58 AM PDT 24
Finished Jul 01 10:47:02 AM PDT 24
Peak memory 198564 kb
Host smart-a245dc21-6d96-4275-a438-0ad15d75add0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63109734 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_w
rites_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_rand
om_long_reg_writes_reg_reads.63109734
Directory /workspace/26.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/26.gpio_smoke.2681346401
Short name T400
Test name
Test status
Simulation time 36647533 ps
CPU time 1.2 seconds
Started Jul 01 10:46:57 AM PDT 24
Finished Jul 01 10:46:59 AM PDT 24
Peak memory 197392 kb
Host smart-07c00bcf-60ef-4529-b8cb-f84e942f89da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2681346401 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_smoke.2681346401
Directory /workspace/26.gpio_smoke/latest

Test location /workspace/coverage/default/26.gpio_smoke_no_pullup_pulldown.2079331730
Short name T511
Test name
Test status
Simulation time 91369560 ps
CPU time 1.52 seconds
Started Jul 01 10:46:51 AM PDT 24
Finished Jul 01 10:46:53 AM PDT 24
Peak memory 196176 kb
Host smart-32428429-ecf8-405e-899e-38b8c220da40
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2079331730 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_smoke_no_pullup_pulldown.2079331730
Directory /workspace/26.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/26.gpio_stress_all.352199289
Short name T471
Test name
Test status
Simulation time 15612968619 ps
CPU time 182.26 seconds
Started Jul 01 10:46:57 AM PDT 24
Finished Jul 01 10:50:00 AM PDT 24
Peak memory 198764 kb
Host smart-0f4e15a2-ea77-4af5-8c69-49a352a08772
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=352199289 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.g
pio_stress_all.352199289
Directory /workspace/26.gpio_stress_all/latest

Test location /workspace/coverage/default/26.gpio_stress_all_with_rand_reset.669021011
Short name T661
Test name
Test status
Simulation time 45063711589 ps
CPU time 1101.49 seconds
Started Jul 01 10:46:59 AM PDT 24
Finished Jul 01 11:05:23 AM PDT 24
Peak memory 198920 kb
Host smart-17cc90a9-c809-476f-b3fc-61cc02c1883d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=669021011 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_stress_all_with_rand_reset.669021011
Directory /workspace/26.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.gpio_alert_test.1873374692
Short name T566
Test name
Test status
Simulation time 38093138 ps
CPU time 0.59 seconds
Started Jul 01 10:46:52 AM PDT 24
Finished Jul 01 10:46:54 AM PDT 24
Peak memory 194656 kb
Host smart-2e32fae1-393c-4efd-a63c-56922c259f8f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1873374692 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_alert_test.1873374692
Directory /workspace/27.gpio_alert_test/latest

Test location /workspace/coverage/default/27.gpio_dout_din_regs_random_rw.3132881442
Short name T588
Test name
Test status
Simulation time 53129404 ps
CPU time 0.97 seconds
Started Jul 01 10:47:10 AM PDT 24
Finished Jul 01 10:47:11 AM PDT 24
Peak memory 196620 kb
Host smart-1d6d38bc-42bd-4595-be57-972b5cc7c64a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3132881442 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_dout_din_regs_random_rw.3132881442
Directory /workspace/27.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/27.gpio_filter_stress.2499433541
Short name T642
Test name
Test status
Simulation time 692548264 ps
CPU time 23.41 seconds
Started Jul 01 10:47:04 AM PDT 24
Finished Jul 01 10:47:29 AM PDT 24
Peak memory 197612 kb
Host smart-3e0b7417-e7c1-4b35-b57e-289a59bc3530
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2499433541 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_filter_stre
ss.2499433541
Directory /workspace/27.gpio_filter_stress/latest

Test location /workspace/coverage/default/27.gpio_full_random.3957518257
Short name T147
Test name
Test status
Simulation time 191882483 ps
CPU time 0.78 seconds
Started Jul 01 10:47:04 AM PDT 24
Finished Jul 01 10:47:07 AM PDT 24
Peak memory 197232 kb
Host smart-4f87cb9f-24d8-4539-bf8e-de93e6f9d626
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3957518257 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_full_random.3957518257
Directory /workspace/27.gpio_full_random/latest

Test location /workspace/coverage/default/27.gpio_intr_rand_pgm.985575020
Short name T269
Test name
Test status
Simulation time 43471877 ps
CPU time 1.23 seconds
Started Jul 01 10:47:11 AM PDT 24
Finished Jul 01 10:47:12 AM PDT 24
Peak memory 196836 kb
Host smart-3a060e3f-ddf5-4209-93a9-67e836e5c80d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=985575020 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_intr_rand_pgm.985575020
Directory /workspace/27.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/27.gpio_intr_with_filter_rand_intr_event.3009665076
Short name T482
Test name
Test status
Simulation time 65236472 ps
CPU time 2.47 seconds
Started Jul 01 10:46:55 AM PDT 24
Finished Jul 01 10:46:59 AM PDT 24
Peak memory 198736 kb
Host smart-5da23d49-8c46-4c5c-bda6-a794daf808c8
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3009665076 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 27.gpio_intr_with_filter_rand_intr_event.3009665076
Directory /workspace/27.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/27.gpio_rand_intr_trigger.1034352180
Short name T668
Test name
Test status
Simulation time 188386319 ps
CPU time 3.09 seconds
Started Jul 01 10:46:56 AM PDT 24
Finished Jul 01 10:47:00 AM PDT 24
Peak memory 198696 kb
Host smart-5b20ce34-14f5-44aa-b683-5bb60e1235f2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1034352180 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_rand_intr_trigger
.1034352180
Directory /workspace/27.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/27.gpio_random_dout_din.614211329
Short name T349
Test name
Test status
Simulation time 120294053 ps
CPU time 1.24 seconds
Started Jul 01 10:46:57 AM PDT 24
Finished Jul 01 10:46:59 AM PDT 24
Peak memory 196524 kb
Host smart-61aa53cb-d422-4c9f-bebb-2c265cb59396
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=614211329 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_random_dout_din.614211329
Directory /workspace/27.gpio_random_dout_din/latest

Test location /workspace/coverage/default/27.gpio_random_dout_din_no_pullup_pulldown.261324942
Short name T261
Test name
Test status
Simulation time 36520381 ps
CPU time 0.92 seconds
Started Jul 01 10:46:52 AM PDT 24
Finished Jul 01 10:46:55 AM PDT 24
Peak memory 196700 kb
Host smart-7574c7b6-fbdc-4a72-9be8-71265518a11a
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=261324942 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_random_dout_din_no_pullup
_pulldown.261324942
Directory /workspace/27.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/27.gpio_random_long_reg_writes_reg_reads.715941766
Short name T715
Test name
Test status
Simulation time 743123066 ps
CPU time 1.63 seconds
Started Jul 01 10:46:48 AM PDT 24
Finished Jul 01 10:46:50 AM PDT 24
Peak memory 198644 kb
Host smart-84d96d38-02e8-4a61-9792-285953f97394
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=715941766 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_ran
dom_long_reg_writes_reg_reads.715941766
Directory /workspace/27.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/27.gpio_smoke.2868970412
Short name T411
Test name
Test status
Simulation time 47949908 ps
CPU time 1.2 seconds
Started Jul 01 10:47:20 AM PDT 24
Finished Jul 01 10:47:22 AM PDT 24
Peak memory 197824 kb
Host smart-6446ebb3-4cd1-46ae-b2b9-966558772c80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2868970412 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_smoke.2868970412
Directory /workspace/27.gpio_smoke/latest

Test location /workspace/coverage/default/27.gpio_smoke_no_pullup_pulldown.482491172
Short name T610
Test name
Test status
Simulation time 200470722 ps
CPU time 1.47 seconds
Started Jul 01 10:46:51 AM PDT 24
Finished Jul 01 10:46:53 AM PDT 24
Peak memory 198680 kb
Host smart-ada362bf-9825-48e5-9b47-ca9abed3add3
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=482491172 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_smoke_no_pullup_pulldown.482491172
Directory /workspace/27.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/27.gpio_stress_all.2932929887
Short name T283
Test name
Test status
Simulation time 40945342916 ps
CPU time 119.85 seconds
Started Jul 01 10:47:00 AM PDT 24
Finished Jul 01 10:49:01 AM PDT 24
Peak memory 198784 kb
Host smart-29383e5a-354c-431e-a509-0f92849a4888
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2932929887 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.
gpio_stress_all.2932929887
Directory /workspace/27.gpio_stress_all/latest

Test location /workspace/coverage/default/27.gpio_stress_all_with_rand_reset.1176687201
Short name T314
Test name
Test status
Simulation time 99413171619 ps
CPU time 709.11 seconds
Started Jul 01 10:47:08 AM PDT 24
Finished Jul 01 10:58:58 AM PDT 24
Peak memory 198888 kb
Host smart-729b971a-14df-4a39-97a4-d5881c0fff95
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1176687201 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_stress_all_with_rand_reset.1176687201
Directory /workspace/27.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.gpio_alert_test.4195296421
Short name T145
Test name
Test status
Simulation time 48644436 ps
CPU time 0.58 seconds
Started Jul 01 10:46:59 AM PDT 24
Finished Jul 01 10:47:02 AM PDT 24
Peak memory 195320 kb
Host smart-743367f6-2759-453c-981a-e509500feef0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4195296421 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_alert_test.4195296421
Directory /workspace/28.gpio_alert_test/latest

Test location /workspace/coverage/default/28.gpio_dout_din_regs_random_rw.618009882
Short name T623
Test name
Test status
Simulation time 89990824 ps
CPU time 0.73 seconds
Started Jul 01 10:46:52 AM PDT 24
Finished Jul 01 10:46:54 AM PDT 24
Peak memory 196652 kb
Host smart-acd7d335-daa1-48f5-b049-02593149b54b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=618009882 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_dout_din_regs_random_rw.618009882
Directory /workspace/28.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/28.gpio_filter_stress.2545680368
Short name T553
Test name
Test status
Simulation time 1737326525 ps
CPU time 23.6 seconds
Started Jul 01 10:47:04 AM PDT 24
Finished Jul 01 10:47:29 AM PDT 24
Peak memory 198616 kb
Host smart-a6b1d990-9449-4108-9c4b-be6f1057170e
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2545680368 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_filter_stre
ss.2545680368
Directory /workspace/28.gpio_filter_stress/latest

Test location /workspace/coverage/default/28.gpio_full_random.1296394759
Short name T371
Test name
Test status
Simulation time 86586741 ps
CPU time 0.96 seconds
Started Jul 01 10:46:53 AM PDT 24
Finished Jul 01 10:46:55 AM PDT 24
Peak memory 197776 kb
Host smart-0cb7d719-d3b6-47de-9022-aef4eb5bd396
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1296394759 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_full_random.1296394759
Directory /workspace/28.gpio_full_random/latest

Test location /workspace/coverage/default/28.gpio_intr_rand_pgm.3143381329
Short name T215
Test name
Test status
Simulation time 182827546 ps
CPU time 1.27 seconds
Started Jul 01 10:47:05 AM PDT 24
Finished Jul 01 10:47:08 AM PDT 24
Peak memory 197832 kb
Host smart-cb7372ac-594b-4ac9-9de4-740911abfab4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3143381329 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_intr_rand_pgm.3143381329
Directory /workspace/28.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/28.gpio_intr_with_filter_rand_intr_event.394725967
Short name T234
Test name
Test status
Simulation time 74392644 ps
CPU time 2.8 seconds
Started Jul 01 10:47:00 AM PDT 24
Finished Jul 01 10:47:04 AM PDT 24
Peak memory 198692 kb
Host smart-2e9529fe-5232-4205-8c57-7e10a3cdced3
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=394725967 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 28.gpio_intr_with_filter_rand_intr_event.394725967
Directory /workspace/28.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/28.gpio_rand_intr_trigger.1337895748
Short name T507
Test name
Test status
Simulation time 140823562 ps
CPU time 3.1 seconds
Started Jul 01 10:47:07 AM PDT 24
Finished Jul 01 10:47:11 AM PDT 24
Peak memory 198608 kb
Host smart-34f4a651-6420-45ff-8298-8dbd0e0e21a2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1337895748 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_rand_intr_trigger
.1337895748
Directory /workspace/28.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/28.gpio_random_dout_din.4129183424
Short name T421
Test name
Test status
Simulation time 59083779 ps
CPU time 0.92 seconds
Started Jul 01 10:47:00 AM PDT 24
Finished Jul 01 10:47:02 AM PDT 24
Peak memory 196680 kb
Host smart-7c4f083c-ff50-42ba-b2fd-77f8350ba428
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4129183424 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_random_dout_din.4129183424
Directory /workspace/28.gpio_random_dout_din/latest

Test location /workspace/coverage/default/28.gpio_random_dout_din_no_pullup_pulldown.1945600396
Short name T138
Test name
Test status
Simulation time 91502928 ps
CPU time 0.93 seconds
Started Jul 01 10:47:23 AM PDT 24
Finished Jul 01 10:47:25 AM PDT 24
Peak memory 197432 kb
Host smart-b5d2ebf2-1c71-48aa-8fc9-2dfb573cd546
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1945600396 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_random_dout_din_no_pullu
p_pulldown.1945600396
Directory /workspace/28.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/28.gpio_random_long_reg_writes_reg_reads.3482763092
Short name T539
Test name
Test status
Simulation time 92047826 ps
CPU time 2.54 seconds
Started Jul 01 10:46:59 AM PDT 24
Finished Jul 01 10:47:03 AM PDT 24
Peak memory 198588 kb
Host smart-4233f66a-c28f-441e-9ee1-b66dbaead10b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3482763092 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_ra
ndom_long_reg_writes_reg_reads.3482763092
Directory /workspace/28.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/28.gpio_smoke.1407196763
Short name T500
Test name
Test status
Simulation time 39663640 ps
CPU time 1.09 seconds
Started Jul 01 10:46:52 AM PDT 24
Finished Jul 01 10:46:54 AM PDT 24
Peak memory 196204 kb
Host smart-64a10e46-76ec-4b30-8647-6a72bdf9ee09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1407196763 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_smoke.1407196763
Directory /workspace/28.gpio_smoke/latest

Test location /workspace/coverage/default/28.gpio_smoke_no_pullup_pulldown.328524008
Short name T621
Test name
Test status
Simulation time 286420116 ps
CPU time 0.77 seconds
Started Jul 01 10:47:06 AM PDT 24
Finished Jul 01 10:47:08 AM PDT 24
Peak memory 195816 kb
Host smart-cce6ff26-88d4-4471-8682-060bf0e3d132
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=328524008 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_smoke_no_pullup_pulldown.328524008
Directory /workspace/28.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/28.gpio_stress_all.1836259762
Short name T419
Test name
Test status
Simulation time 30762200803 ps
CPU time 167.72 seconds
Started Jul 01 10:47:01 AM PDT 24
Finished Jul 01 10:49:50 AM PDT 24
Peak memory 198844 kb
Host smart-88fb81d6-0b86-49ff-8835-640a802c2d5e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1836259762 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.
gpio_stress_all.1836259762
Directory /workspace/28.gpio_stress_all/latest

Test location /workspace/coverage/default/29.gpio_alert_test.1626366129
Short name T227
Test name
Test status
Simulation time 20685798 ps
CPU time 0.55 seconds
Started Jul 01 10:47:13 AM PDT 24
Finished Jul 01 10:47:15 AM PDT 24
Peak memory 194640 kb
Host smart-93152979-247b-4268-b8f6-5e1f882be381
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1626366129 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_alert_test.1626366129
Directory /workspace/29.gpio_alert_test/latest

Test location /workspace/coverage/default/29.gpio_dout_din_regs_random_rw.3110261800
Short name T318
Test name
Test status
Simulation time 23131920 ps
CPU time 0.64 seconds
Started Jul 01 10:46:53 AM PDT 24
Finished Jul 01 10:46:55 AM PDT 24
Peak memory 195368 kb
Host smart-314eecc5-2c48-4fdc-bee4-b15940abd45a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3110261800 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_dout_din_regs_random_rw.3110261800
Directory /workspace/29.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/29.gpio_filter_stress.2575970577
Short name T657
Test name
Test status
Simulation time 167734311 ps
CPU time 5.97 seconds
Started Jul 01 10:46:48 AM PDT 24
Finished Jul 01 10:46:55 AM PDT 24
Peak memory 197324 kb
Host smart-2d56c7cf-3a51-4039-a026-b180c2371474
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2575970577 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_filter_stre
ss.2575970577
Directory /workspace/29.gpio_filter_stress/latest

Test location /workspace/coverage/default/29.gpio_full_random.1335287556
Short name T454
Test name
Test status
Simulation time 288896101 ps
CPU time 0.97 seconds
Started Jul 01 10:46:57 AM PDT 24
Finished Jul 01 10:46:59 AM PDT 24
Peak memory 198416 kb
Host smart-75a0cc26-57ee-4705-9cef-f3764af751e3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1335287556 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_full_random.1335287556
Directory /workspace/29.gpio_full_random/latest

Test location /workspace/coverage/default/29.gpio_intr_rand_pgm.113951210
Short name T444
Test name
Test status
Simulation time 50093469 ps
CPU time 1.24 seconds
Started Jul 01 10:46:57 AM PDT 24
Finished Jul 01 10:46:59 AM PDT 24
Peak memory 197652 kb
Host smart-18a3e956-2b13-4fe5-86fc-ad754a3a8026
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=113951210 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_intr_rand_pgm.113951210
Directory /workspace/29.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/29.gpio_intr_with_filter_rand_intr_event.2002575002
Short name T172
Test name
Test status
Simulation time 353714387 ps
CPU time 3.66 seconds
Started Jul 01 10:47:05 AM PDT 24
Finished Jul 01 10:47:11 AM PDT 24
Peak memory 198648 kb
Host smart-bf13d868-a5e9-4cd4-96b3-103106d600a1
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2002575002 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 29.gpio_intr_with_filter_rand_intr_event.2002575002
Directory /workspace/29.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/29.gpio_rand_intr_trigger.2949624739
Short name T456
Test name
Test status
Simulation time 138468471 ps
CPU time 1.48 seconds
Started Jul 01 10:47:04 AM PDT 24
Finished Jul 01 10:47:07 AM PDT 24
Peak memory 196848 kb
Host smart-79492121-c487-475d-82a9-09a31623bb90
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2949624739 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_rand_intr_trigger
.2949624739
Directory /workspace/29.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/29.gpio_random_dout_din.401066703
Short name T331
Test name
Test status
Simulation time 191118119 ps
CPU time 0.83 seconds
Started Jul 01 10:46:50 AM PDT 24
Finished Jul 01 10:46:52 AM PDT 24
Peak memory 197212 kb
Host smart-9595f67f-481b-427c-9ce9-e2892fb91c50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=401066703 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_random_dout_din.401066703
Directory /workspace/29.gpio_random_dout_din/latest

Test location /workspace/coverage/default/29.gpio_random_dout_din_no_pullup_pulldown.1850194037
Short name T345
Test name
Test status
Simulation time 46564522 ps
CPU time 1.07 seconds
Started Jul 01 10:47:00 AM PDT 24
Finished Jul 01 10:47:03 AM PDT 24
Peak memory 197108 kb
Host smart-df535acf-cc58-4137-92f6-3a37ab317468
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1850194037 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_random_dout_din_no_pullu
p_pulldown.1850194037
Directory /workspace/29.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/29.gpio_random_long_reg_writes_reg_reads.4194751445
Short name T450
Test name
Test status
Simulation time 1957437126 ps
CPU time 6.03 seconds
Started Jul 01 10:46:58 AM PDT 24
Finished Jul 01 10:47:05 AM PDT 24
Peak memory 198676 kb
Host smart-74be0c9c-1d77-4167-9da5-3e06c736abe8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4194751445 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_ra
ndom_long_reg_writes_reg_reads.4194751445
Directory /workspace/29.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/29.gpio_smoke.3400996657
Short name T447
Test name
Test status
Simulation time 239963244 ps
CPU time 1.35 seconds
Started Jul 01 10:46:52 AM PDT 24
Finished Jul 01 10:46:55 AM PDT 24
Peak memory 198676 kb
Host smart-cf101aed-ca9e-42a8-a0eb-121ed89ce727
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3400996657 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_smoke.3400996657
Directory /workspace/29.gpio_smoke/latest

Test location /workspace/coverage/default/29.gpio_smoke_no_pullup_pulldown.1194781225
Short name T361
Test name
Test status
Simulation time 556697627 ps
CPU time 1.01 seconds
Started Jul 01 10:46:52 AM PDT 24
Finished Jul 01 10:46:55 AM PDT 24
Peak memory 197200 kb
Host smart-168ddd02-4433-4f21-bcef-78e0c19cae20
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1194781225 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_smoke_no_pullup_pulldown.1194781225
Directory /workspace/29.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/29.gpio_stress_all.4193045729
Short name T245
Test name
Test status
Simulation time 7500062627 ps
CPU time 194.73 seconds
Started Jul 01 10:46:57 AM PDT 24
Finished Jul 01 10:50:13 AM PDT 24
Peak memory 198756 kb
Host smart-3932d541-c941-483c-89b2-6b39286feda3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4193045729 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.
gpio_stress_all.4193045729
Directory /workspace/29.gpio_stress_all/latest

Test location /workspace/coverage/default/3.gpio_alert_test.2044997600
Short name T279
Test name
Test status
Simulation time 28306717 ps
CPU time 0.56 seconds
Started Jul 01 10:46:34 AM PDT 24
Finished Jul 01 10:46:38 AM PDT 24
Peak memory 195340 kb
Host smart-117a934f-9edc-4993-a02d-2e5378c80204
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2044997600 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_alert_test.2044997600
Directory /workspace/3.gpio_alert_test/latest

Test location /workspace/coverage/default/3.gpio_dout_din_regs_random_rw.3227034690
Short name T516
Test name
Test status
Simulation time 145839656 ps
CPU time 0.78 seconds
Started Jul 01 10:46:41 AM PDT 24
Finished Jul 01 10:46:45 AM PDT 24
Peak memory 195900 kb
Host smart-9dc94dcd-b89a-4cfb-8aa3-0af26189a0ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3227034690 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_dout_din_regs_random_rw.3227034690
Directory /workspace/3.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/3.gpio_filter_stress.3307282239
Short name T247
Test name
Test status
Simulation time 968784144 ps
CPU time 8.25 seconds
Started Jul 01 10:46:12 AM PDT 24
Finished Jul 01 10:46:21 AM PDT 24
Peak memory 198660 kb
Host smart-c71663e7-41d6-4617-bb6f-eb886e1998af
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3307282239 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_filter_stres
s.3307282239
Directory /workspace/3.gpio_filter_stress/latest

Test location /workspace/coverage/default/3.gpio_full_random.2930050772
Short name T288
Test name
Test status
Simulation time 241507628 ps
CPU time 0.93 seconds
Started Jul 01 10:46:31 AM PDT 24
Finished Jul 01 10:46:35 AM PDT 24
Peak memory 198548 kb
Host smart-b8b6015b-0d15-4386-b98d-7adef25f8c5c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2930050772 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_full_random.2930050772
Directory /workspace/3.gpio_full_random/latest

Test location /workspace/coverage/default/3.gpio_intr_rand_pgm.2924272880
Short name T692
Test name
Test status
Simulation time 52742632 ps
CPU time 0.77 seconds
Started Jul 01 10:46:10 AM PDT 24
Finished Jul 01 10:46:11 AM PDT 24
Peak memory 196076 kb
Host smart-9d3c39f8-d533-4af9-ac97-2c721dae925e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2924272880 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_intr_rand_pgm.2924272880
Directory /workspace/3.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/3.gpio_intr_with_filter_rand_intr_event.3326868479
Short name T436
Test name
Test status
Simulation time 151419045 ps
CPU time 3.03 seconds
Started Jul 01 10:46:35 AM PDT 24
Finished Jul 01 10:46:51 AM PDT 24
Peak memory 198652 kb
Host smart-e256c3e4-c3d4-4ca5-8021-9a61e15c6ef6
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3326868479 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 3.gpio_intr_with_filter_rand_intr_event.3326868479
Directory /workspace/3.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/3.gpio_rand_intr_trigger.3882518758
Short name T416
Test name
Test status
Simulation time 471544340 ps
CPU time 2.71 seconds
Started Jul 01 10:46:11 AM PDT 24
Finished Jul 01 10:46:15 AM PDT 24
Peak memory 197844 kb
Host smart-e4cb1a65-bed4-41f2-83b1-2a4241973954
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3882518758 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_rand_intr_trigger.
3882518758
Directory /workspace/3.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/3.gpio_random_dout_din.4132185953
Short name T352
Test name
Test status
Simulation time 52070154 ps
CPU time 1.06 seconds
Started Jul 01 10:46:34 AM PDT 24
Finished Jul 01 10:46:38 AM PDT 24
Peak memory 197372 kb
Host smart-35c586a9-f9fe-47fc-92b0-03eb18147bbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4132185953 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_random_dout_din.4132185953
Directory /workspace/3.gpio_random_dout_din/latest

Test location /workspace/coverage/default/3.gpio_random_dout_din_no_pullup_pulldown.1924006349
Short name T426
Test name
Test status
Simulation time 45083560 ps
CPU time 0.99 seconds
Started Jul 01 10:46:13 AM PDT 24
Finished Jul 01 10:46:15 AM PDT 24
Peak memory 196524 kb
Host smart-ca7dc206-b96f-4ab9-8a4a-253d0e368543
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1924006349 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_random_dout_din_no_pullup
_pulldown.1924006349
Directory /workspace/3.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/3.gpio_random_long_reg_writes_reg_reads.3618317804
Short name T56
Test name
Test status
Simulation time 896037528 ps
CPU time 3.52 seconds
Started Jul 01 10:46:09 AM PDT 24
Finished Jul 01 10:46:13 AM PDT 24
Peak memory 198476 kb
Host smart-41ac7c3c-f4b4-45c4-a15a-369ce24d1474
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3618317804 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_ran
dom_long_reg_writes_reg_reads.3618317804
Directory /workspace/3.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/3.gpio_sec_cm.1668193607
Short name T50
Test name
Test status
Simulation time 423667589 ps
CPU time 0.96 seconds
Started Jul 01 10:46:36 AM PDT 24
Finished Jul 01 10:46:42 AM PDT 24
Peak memory 215252 kb
Host smart-d56c87d7-252c-4ba1-9e8c-6afcb616e1d0
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1668193607 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_sec_cm.1668193607
Directory /workspace/3.gpio_sec_cm/latest

Test location /workspace/coverage/default/3.gpio_smoke.2415658237
Short name T632
Test name
Test status
Simulation time 58293457 ps
CPU time 0.99 seconds
Started Jul 01 10:46:30 AM PDT 24
Finished Jul 01 10:46:31 AM PDT 24
Peak memory 197400 kb
Host smart-8a0988e1-b226-4a1b-94ef-56dc17176585
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2415658237 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_smoke.2415658237
Directory /workspace/3.gpio_smoke/latest

Test location /workspace/coverage/default/3.gpio_smoke_no_pullup_pulldown.1591795253
Short name T383
Test name
Test status
Simulation time 234164361 ps
CPU time 1.19 seconds
Started Jul 01 10:46:35 AM PDT 24
Finished Jul 01 10:46:41 AM PDT 24
Peak memory 197280 kb
Host smart-8241bc29-9189-4c6a-8573-a2bf2a7c8ef7
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1591795253 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_smoke_no_pullup_pulldown.1591795253
Directory /workspace/3.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/3.gpio_stress_all.2553400311
Short name T515
Test name
Test status
Simulation time 21135052756 ps
CPU time 72.38 seconds
Started Jul 01 10:46:33 AM PDT 24
Finished Jul 01 10:47:47 AM PDT 24
Peak memory 198792 kb
Host smart-2ed37b32-809b-4bfe-9b08-98bd5f446c98
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2553400311 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.g
pio_stress_all.2553400311
Directory /workspace/3.gpio_stress_all/latest

Test location /workspace/coverage/default/30.gpio_alert_test.3225344971
Short name T375
Test name
Test status
Simulation time 21701687 ps
CPU time 0.6 seconds
Started Jul 01 10:47:01 AM PDT 24
Finished Jul 01 10:47:03 AM PDT 24
Peak memory 195364 kb
Host smart-0aa5df37-6b48-4a3b-aa56-8395c418cb64
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3225344971 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_alert_test.3225344971
Directory /workspace/30.gpio_alert_test/latest

Test location /workspace/coverage/default/30.gpio_dout_din_regs_random_rw.927440756
Short name T185
Test name
Test status
Simulation time 276274555 ps
CPU time 0.84 seconds
Started Jul 01 10:47:15 AM PDT 24
Finished Jul 01 10:47:17 AM PDT 24
Peak memory 196052 kb
Host smart-8603b0bd-65aa-4c0a-aba8-0b4c97847f19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=927440756 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_dout_din_regs_random_rw.927440756
Directory /workspace/30.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/30.gpio_filter_stress.3538518814
Short name T238
Test name
Test status
Simulation time 1144025006 ps
CPU time 29.72 seconds
Started Jul 01 10:47:07 AM PDT 24
Finished Jul 01 10:47:38 AM PDT 24
Peak memory 197380 kb
Host smart-d8e374e1-24fe-4cc5-b47c-6edacc3e7343
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3538518814 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_filter_stre
ss.3538518814
Directory /workspace/30.gpio_filter_stress/latest

Test location /workspace/coverage/default/30.gpio_full_random.1158913839
Short name T231
Test name
Test status
Simulation time 63084909 ps
CPU time 0.83 seconds
Started Jul 01 10:47:14 AM PDT 24
Finished Jul 01 10:47:16 AM PDT 24
Peak memory 196684 kb
Host smart-5242bc3a-1c70-4849-978b-0b92efc9cfaa
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1158913839 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_full_random.1158913839
Directory /workspace/30.gpio_full_random/latest

Test location /workspace/coverage/default/30.gpio_intr_rand_pgm.2968773619
Short name T625
Test name
Test status
Simulation time 65870424 ps
CPU time 1.28 seconds
Started Jul 01 10:46:59 AM PDT 24
Finished Jul 01 10:47:02 AM PDT 24
Peak memory 197620 kb
Host smart-39275856-099a-4240-a29e-e43b21b53f4d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2968773619 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_intr_rand_pgm.2968773619
Directory /workspace/30.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/30.gpio_intr_with_filter_rand_intr_event.3425524296
Short name T533
Test name
Test status
Simulation time 549636365 ps
CPU time 3.43 seconds
Started Jul 01 10:46:58 AM PDT 24
Finished Jul 01 10:47:02 AM PDT 24
Peak memory 198792 kb
Host smart-61446376-05c5-4bfa-80c3-24e04b227837
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3425524296 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 30.gpio_intr_with_filter_rand_intr_event.3425524296
Directory /workspace/30.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/30.gpio_rand_intr_trigger.2711560853
Short name T118
Test name
Test status
Simulation time 161546132 ps
CPU time 3 seconds
Started Jul 01 10:47:04 AM PDT 24
Finished Jul 01 10:47:09 AM PDT 24
Peak memory 196384 kb
Host smart-4175fab9-2c82-4344-8592-20909b08bd95
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2711560853 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_rand_intr_trigger
.2711560853
Directory /workspace/30.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/30.gpio_random_dout_din.3393857386
Short name T140
Test name
Test status
Simulation time 117499588 ps
CPU time 1.16 seconds
Started Jul 01 10:47:09 AM PDT 24
Finished Jul 01 10:47:11 AM PDT 24
Peak memory 197592 kb
Host smart-2cb729d7-57a0-47c0-827b-8e0c99c27ae7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3393857386 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_random_dout_din.3393857386
Directory /workspace/30.gpio_random_dout_din/latest

Test location /workspace/coverage/default/30.gpio_random_dout_din_no_pullup_pulldown.4223594831
Short name T262
Test name
Test status
Simulation time 35274526 ps
CPU time 1.25 seconds
Started Jul 01 10:46:59 AM PDT 24
Finished Jul 01 10:47:01 AM PDT 24
Peak memory 196528 kb
Host smart-51d324e1-38af-4750-9e21-e38e525ac399
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4223594831 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_random_dout_din_no_pullu
p_pulldown.4223594831
Directory /workspace/30.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/30.gpio_random_long_reg_writes_reg_reads.2094150509
Short name T265
Test name
Test status
Simulation time 68678413 ps
CPU time 1.43 seconds
Started Jul 01 10:47:13 AM PDT 24
Finished Jul 01 10:47:16 AM PDT 24
Peak memory 198656 kb
Host smart-0b72a046-30d2-4256-a351-6c99d6b568c4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2094150509 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_ra
ndom_long_reg_writes_reg_reads.2094150509
Directory /workspace/30.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/30.gpio_smoke.4010880547
Short name T590
Test name
Test status
Simulation time 213693223 ps
CPU time 1.07 seconds
Started Jul 01 10:47:26 AM PDT 24
Finished Jul 01 10:47:28 AM PDT 24
Peak memory 196824 kb
Host smart-861c0087-1a94-424a-8cc0-63a9501053f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4010880547 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_smoke.4010880547
Directory /workspace/30.gpio_smoke/latest

Test location /workspace/coverage/default/30.gpio_smoke_no_pullup_pulldown.506710409
Short name T550
Test name
Test status
Simulation time 25079138 ps
CPU time 0.91 seconds
Started Jul 01 10:46:54 AM PDT 24
Finished Jul 01 10:46:56 AM PDT 24
Peak memory 196980 kb
Host smart-14105b2c-55e7-45e7-9776-e4ea1ff63528
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=506710409 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_smoke_no_pullup_pulldown.506710409
Directory /workspace/30.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/30.gpio_stress_all.2546407496
Short name T684
Test name
Test status
Simulation time 8533161540 ps
CPU time 100.99 seconds
Started Jul 01 10:47:24 AM PDT 24
Finished Jul 01 10:49:06 AM PDT 24
Peak memory 198764 kb
Host smart-810b1a4c-4f08-4ba9-b112-309ded520b0f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2546407496 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.
gpio_stress_all.2546407496
Directory /workspace/30.gpio_stress_all/latest

Test location /workspace/coverage/default/30.gpio_stress_all_with_rand_reset.2739299250
Short name T681
Test name
Test status
Simulation time 110128371036 ps
CPU time 1434.47 seconds
Started Jul 01 10:47:03 AM PDT 24
Finished Jul 01 11:10:59 AM PDT 24
Peak memory 199004 kb
Host smart-5535fb1c-cc32-4022-985c-9f6d9a633e57
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2739299250 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_stress_all_with_rand_reset.2739299250
Directory /workspace/30.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.gpio_alert_test.160106291
Short name T168
Test name
Test status
Simulation time 14324570 ps
CPU time 0.65 seconds
Started Jul 01 10:47:18 AM PDT 24
Finished Jul 01 10:47:19 AM PDT 24
Peak memory 194864 kb
Host smart-6418b339-eae6-439e-97fe-fc0cee0c9825
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=160106291 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_alert_test.160106291
Directory /workspace/31.gpio_alert_test/latest

Test location /workspace/coverage/default/31.gpio_dout_din_regs_random_rw.3056943256
Short name T154
Test name
Test status
Simulation time 19195115 ps
CPU time 0.68 seconds
Started Jul 01 10:47:02 AM PDT 24
Finished Jul 01 10:47:04 AM PDT 24
Peak memory 194544 kb
Host smart-f29d79f8-ad0f-440e-a78e-6df3f5f32067
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3056943256 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_dout_din_regs_random_rw.3056943256
Directory /workspace/31.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/31.gpio_filter_stress.1442663233
Short name T149
Test name
Test status
Simulation time 436289688 ps
CPU time 13.15 seconds
Started Jul 01 10:46:58 AM PDT 24
Finished Jul 01 10:47:13 AM PDT 24
Peak memory 197576 kb
Host smart-380a8914-35fb-48a3-8e86-08cb3f76a431
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1442663233 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_filter_stre
ss.1442663233
Directory /workspace/31.gpio_filter_stress/latest

Test location /workspace/coverage/default/31.gpio_full_random.3151278812
Short name T54
Test name
Test status
Simulation time 58938058 ps
CPU time 0.66 seconds
Started Jul 01 10:47:19 AM PDT 24
Finished Jul 01 10:47:20 AM PDT 24
Peak memory 195972 kb
Host smart-1f85e20d-996f-46a6-9469-a3d447fbb3aa
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3151278812 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_full_random.3151278812
Directory /workspace/31.gpio_full_random/latest

Test location /workspace/coverage/default/31.gpio_intr_rand_pgm.4092673370
Short name T122
Test name
Test status
Simulation time 181403152 ps
CPU time 0.87 seconds
Started Jul 01 10:47:04 AM PDT 24
Finished Jul 01 10:47:08 AM PDT 24
Peak memory 197024 kb
Host smart-0d496d8e-0581-4dae-be06-06a1e7d8d9f7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4092673370 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_intr_rand_pgm.4092673370
Directory /workspace/31.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/31.gpio_intr_with_filter_rand_intr_event.3503693208
Short name T107
Test name
Test status
Simulation time 90278409 ps
CPU time 3 seconds
Started Jul 01 10:47:04 AM PDT 24
Finished Jul 01 10:47:09 AM PDT 24
Peak memory 196824 kb
Host smart-323b5b5a-ae13-4c72-8012-ad720b8749d2
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3503693208 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 31.gpio_intr_with_filter_rand_intr_event.3503693208
Directory /workspace/31.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/31.gpio_rand_intr_trigger.1151915077
Short name T326
Test name
Test status
Simulation time 428751820 ps
CPU time 3.21 seconds
Started Jul 01 10:47:01 AM PDT 24
Finished Jul 01 10:47:06 AM PDT 24
Peak memory 197628 kb
Host smart-8bd6f83e-4b45-406f-b8f9-b1861e0280a0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1151915077 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_rand_intr_trigger
.1151915077
Directory /workspace/31.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/31.gpio_random_dout_din.2428885979
Short name T644
Test name
Test status
Simulation time 36720452 ps
CPU time 1 seconds
Started Jul 01 10:47:28 AM PDT 24
Finished Jul 01 10:47:32 AM PDT 24
Peak memory 196452 kb
Host smart-5807d269-8bba-43df-98d8-31ff16b87cda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2428885979 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_random_dout_din.2428885979
Directory /workspace/31.gpio_random_dout_din/latest

Test location /workspace/coverage/default/31.gpio_random_dout_din_no_pullup_pulldown.3365034170
Short name T385
Test name
Test status
Simulation time 35444473 ps
CPU time 1.41 seconds
Started Jul 01 10:47:00 AM PDT 24
Finished Jul 01 10:47:03 AM PDT 24
Peak memory 198712 kb
Host smart-695133a5-2ac9-4cd5-8552-e8fed6d43060
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3365034170 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_random_dout_din_no_pullu
p_pulldown.3365034170
Directory /workspace/31.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/31.gpio_random_long_reg_writes_reg_reads.350515424
Short name T342
Test name
Test status
Simulation time 161833459 ps
CPU time 2.51 seconds
Started Jul 01 10:46:58 AM PDT 24
Finished Jul 01 10:47:02 AM PDT 24
Peak memory 198572 kb
Host smart-fcf85d8b-c826-4df4-bd64-1570725e7667
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=350515424 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_ran
dom_long_reg_writes_reg_reads.350515424
Directory /workspace/31.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/31.gpio_smoke.1098659012
Short name T297
Test name
Test status
Simulation time 41401451 ps
CPU time 0.87 seconds
Started Jul 01 10:47:12 AM PDT 24
Finished Jul 01 10:47:15 AM PDT 24
Peak memory 196760 kb
Host smart-751a2fc6-8d49-49b3-bfaa-f856b4d2d2fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1098659012 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_smoke.1098659012
Directory /workspace/31.gpio_smoke/latest

Test location /workspace/coverage/default/31.gpio_smoke_no_pullup_pulldown.1727475127
Short name T641
Test name
Test status
Simulation time 70948213 ps
CPU time 1.39 seconds
Started Jul 01 10:47:02 AM PDT 24
Finished Jul 01 10:47:04 AM PDT 24
Peak memory 197052 kb
Host smart-6d55a597-4cea-4d4a-96e3-f338406ae52e
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1727475127 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_smoke_no_pullup_pulldown.1727475127
Directory /workspace/31.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/31.gpio_stress_all.705595796
Short name T703
Test name
Test status
Simulation time 13146845292 ps
CPU time 71.96 seconds
Started Jul 01 10:47:02 AM PDT 24
Finished Jul 01 10:48:15 AM PDT 24
Peak memory 198672 kb
Host smart-8b046883-99e9-486a-96d4-3ccf62c1d5b2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=705595796 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.g
pio_stress_all.705595796
Directory /workspace/31.gpio_stress_all/latest

Test location /workspace/coverage/default/32.gpio_alert_test.1778264068
Short name T379
Test name
Test status
Simulation time 13219871 ps
CPU time 0.58 seconds
Started Jul 01 10:47:08 AM PDT 24
Finished Jul 01 10:47:10 AM PDT 24
Peak memory 194596 kb
Host smart-1bf1bd07-4a6d-4fc1-babe-1489c6acd889
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1778264068 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_alert_test.1778264068
Directory /workspace/32.gpio_alert_test/latest

Test location /workspace/coverage/default/32.gpio_dout_din_regs_random_rw.3397505978
Short name T528
Test name
Test status
Simulation time 119171451 ps
CPU time 0.94 seconds
Started Jul 01 10:47:03 AM PDT 24
Finished Jul 01 10:47:04 AM PDT 24
Peak memory 196704 kb
Host smart-39d7b1a5-ceee-4fb8-8bef-1e98ec826225
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3397505978 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_dout_din_regs_random_rw.3397505978
Directory /workspace/32.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/32.gpio_filter_stress.1738804454
Short name T565
Test name
Test status
Simulation time 539944167 ps
CPU time 14.14 seconds
Started Jul 01 10:47:04 AM PDT 24
Finished Jul 01 10:47:20 AM PDT 24
Peak memory 198692 kb
Host smart-ff0ef3dc-27e1-4489-af0d-8f2f17d542f4
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1738804454 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_filter_stre
ss.1738804454
Directory /workspace/32.gpio_filter_stress/latest

Test location /workspace/coverage/default/32.gpio_full_random.2949858786
Short name T514
Test name
Test status
Simulation time 54424435 ps
CPU time 0.79 seconds
Started Jul 01 10:47:27 AM PDT 24
Finished Jul 01 10:47:30 AM PDT 24
Peak memory 196248 kb
Host smart-96d368f3-99f5-4477-ad8f-b17b95515cf0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2949858786 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_full_random.2949858786
Directory /workspace/32.gpio_full_random/latest

Test location /workspace/coverage/default/32.gpio_intr_rand_pgm.4045001602
Short name T694
Test name
Test status
Simulation time 70344087 ps
CPU time 1.24 seconds
Started Jul 01 10:47:02 AM PDT 24
Finished Jul 01 10:47:04 AM PDT 24
Peak memory 196452 kb
Host smart-5fdecc21-fbc5-4f15-826b-2a0f2fd2c4f1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4045001602 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_intr_rand_pgm.4045001602
Directory /workspace/32.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/32.gpio_intr_with_filter_rand_intr_event.732277594
Short name T541
Test name
Test status
Simulation time 135674598 ps
CPU time 1.63 seconds
Started Jul 01 10:47:01 AM PDT 24
Finished Jul 01 10:47:04 AM PDT 24
Peak memory 197364 kb
Host smart-17ec95ae-d927-4ced-9dda-3b1cd32da93e
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=732277594 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 32.gpio_intr_with_filter_rand_intr_event.732277594
Directory /workspace/32.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/32.gpio_rand_intr_trigger.952425460
Short name T322
Test name
Test status
Simulation time 232638089 ps
CPU time 3.72 seconds
Started Jul 01 10:47:07 AM PDT 24
Finished Jul 01 10:47:12 AM PDT 24
Peak memory 198672 kb
Host smart-b6c2174c-d714-492b-8a56-2129c0f17c2a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=952425460 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_rand_intr_trigger.
952425460
Directory /workspace/32.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/32.gpio_random_dout_din.2440562116
Short name T284
Test name
Test status
Simulation time 96877101 ps
CPU time 0.79 seconds
Started Jul 01 10:47:07 AM PDT 24
Finished Jul 01 10:47:09 AM PDT 24
Peak memory 196064 kb
Host smart-f2aebacb-731c-4b4c-81b8-2d5dc43bda28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2440562116 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_random_dout_din.2440562116
Directory /workspace/32.gpio_random_dout_din/latest

Test location /workspace/coverage/default/32.gpio_random_dout_din_no_pullup_pulldown.1899223424
Short name T357
Test name
Test status
Simulation time 58036003 ps
CPU time 0.64 seconds
Started Jul 01 10:47:02 AM PDT 24
Finished Jul 01 10:47:04 AM PDT 24
Peak memory 194876 kb
Host smart-a182b2e6-6faf-4a60-b77d-8939b1e788b1
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1899223424 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_random_dout_din_no_pullu
p_pulldown.1899223424
Directory /workspace/32.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/32.gpio_random_long_reg_writes_reg_reads.1804394062
Short name T173
Test name
Test status
Simulation time 1115717210 ps
CPU time 5.1 seconds
Started Jul 01 10:47:06 AM PDT 24
Finished Jul 01 10:47:12 AM PDT 24
Peak memory 198600 kb
Host smart-d0cc3f06-ff83-4269-988e-da167aa8cb97
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1804394062 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_ra
ndom_long_reg_writes_reg_reads.1804394062
Directory /workspace/32.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/32.gpio_smoke.128630812
Short name T178
Test name
Test status
Simulation time 89556139 ps
CPU time 0.99 seconds
Started Jul 01 10:47:27 AM PDT 24
Finished Jul 01 10:47:31 AM PDT 24
Peak memory 196196 kb
Host smart-05c8adb0-9548-4de0-9927-f6ee7200f60e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=128630812 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_smoke.128630812
Directory /workspace/32.gpio_smoke/latest

Test location /workspace/coverage/default/32.gpio_smoke_no_pullup_pulldown.3958214870
Short name T486
Test name
Test status
Simulation time 191330071 ps
CPU time 0.97 seconds
Started Jul 01 10:47:08 AM PDT 24
Finished Jul 01 10:47:10 AM PDT 24
Peak memory 197560 kb
Host smart-07653c46-2b6c-439a-9e97-6711a6a009e9
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3958214870 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_smoke_no_pullup_pulldown.3958214870
Directory /workspace/32.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/32.gpio_stress_all.878269443
Short name T373
Test name
Test status
Simulation time 64986428010 ps
CPU time 137.77 seconds
Started Jul 01 10:47:22 AM PDT 24
Finished Jul 01 10:49:41 AM PDT 24
Peak memory 198708 kb
Host smart-9041b795-5236-446a-a436-0a6b4c8a54e0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=878269443 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.g
pio_stress_all.878269443
Directory /workspace/32.gpio_stress_all/latest

Test location /workspace/coverage/default/33.gpio_alert_test.3205094458
Short name T685
Test name
Test status
Simulation time 11313986 ps
CPU time 0.59 seconds
Started Jul 01 10:47:10 AM PDT 24
Finished Jul 01 10:47:11 AM PDT 24
Peak memory 194664 kb
Host smart-cf112011-8416-4258-a439-3b790bc061b2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3205094458 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_alert_test.3205094458
Directory /workspace/33.gpio_alert_test/latest

Test location /workspace/coverage/default/33.gpio_dout_din_regs_random_rw.19064469
Short name T116
Test name
Test status
Simulation time 57918422 ps
CPU time 0.65 seconds
Started Jul 01 10:47:05 AM PDT 24
Finished Jul 01 10:47:07 AM PDT 24
Peak memory 194792 kb
Host smart-ab0f1070-1212-480e-a196-5eeb0755d65c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=19064469 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_dout_din_regs_random_rw.19064469
Directory /workspace/33.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/33.gpio_filter_stress.3877983924
Short name T334
Test name
Test status
Simulation time 1414485423 ps
CPU time 11.36 seconds
Started Jul 01 10:47:20 AM PDT 24
Finished Jul 01 10:47:43 AM PDT 24
Peak memory 196932 kb
Host smart-a03397fb-f2aa-4b09-ae1a-df45ccbc8f3e
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3877983924 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_filter_stre
ss.3877983924
Directory /workspace/33.gpio_filter_stress/latest

Test location /workspace/coverage/default/33.gpio_full_random.2108720219
Short name T465
Test name
Test status
Simulation time 121753655 ps
CPU time 1.09 seconds
Started Jul 01 10:47:05 AM PDT 24
Finished Jul 01 10:47:08 AM PDT 24
Peak memory 197148 kb
Host smart-e37e6c5e-35c0-4c19-a161-fe4ee254ded7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2108720219 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_full_random.2108720219
Directory /workspace/33.gpio_full_random/latest

Test location /workspace/coverage/default/33.gpio_intr_rand_pgm.1928148689
Short name T350
Test name
Test status
Simulation time 310668221 ps
CPU time 1.18 seconds
Started Jul 01 10:47:26 AM PDT 24
Finished Jul 01 10:47:29 AM PDT 24
Peak memory 196824 kb
Host smart-ce93a95e-028a-465e-b124-05cd0db2dba7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1928148689 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_intr_rand_pgm.1928148689
Directory /workspace/33.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/33.gpio_intr_with_filter_rand_intr_event.3827492460
Short name T102
Test name
Test status
Simulation time 62473720 ps
CPU time 2.43 seconds
Started Jul 01 10:47:04 AM PDT 24
Finished Jul 01 10:47:09 AM PDT 24
Peak memory 198672 kb
Host smart-e914ece3-9ea2-44d7-89ad-517d900dab8d
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3827492460 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 33.gpio_intr_with_filter_rand_intr_event.3827492460
Directory /workspace/33.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/33.gpio_rand_intr_trigger.2294334602
Short name T301
Test name
Test status
Simulation time 418549413 ps
CPU time 3.2 seconds
Started Jul 01 10:47:29 AM PDT 24
Finished Jul 01 10:47:36 AM PDT 24
Peak memory 197564 kb
Host smart-49db721a-b91c-4aab-a792-ec7da42d93b0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2294334602 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_rand_intr_trigger
.2294334602
Directory /workspace/33.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/33.gpio_random_dout_din.3789379604
Short name T489
Test name
Test status
Simulation time 28676034 ps
CPU time 1.04 seconds
Started Jul 01 10:47:25 AM PDT 24
Finished Jul 01 10:47:27 AM PDT 24
Peak memory 196640 kb
Host smart-eefa6fe1-d974-48ab-89e3-4d86006e08d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3789379604 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_random_dout_din.3789379604
Directory /workspace/33.gpio_random_dout_din/latest

Test location /workspace/coverage/default/33.gpio_random_dout_din_no_pullup_pulldown.3526913260
Short name T705
Test name
Test status
Simulation time 97009909 ps
CPU time 1.25 seconds
Started Jul 01 10:47:06 AM PDT 24
Finished Jul 01 10:47:09 AM PDT 24
Peak memory 197280 kb
Host smart-60fa8326-83b2-401e-933c-7da2bc0dc1c8
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3526913260 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_random_dout_din_no_pullu
p_pulldown.3526913260
Directory /workspace/33.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/33.gpio_random_long_reg_writes_reg_reads.2235731091
Short name T7
Test name
Test status
Simulation time 770927721 ps
CPU time 2.57 seconds
Started Jul 01 10:47:11 AM PDT 24
Finished Jul 01 10:47:16 AM PDT 24
Peak memory 198540 kb
Host smart-48ac4008-5cea-4290-83d7-c94806c689d9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2235731091 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_ra
ndom_long_reg_writes_reg_reads.2235731091
Directory /workspace/33.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/33.gpio_smoke.1849969630
Short name T560
Test name
Test status
Simulation time 259342883 ps
CPU time 1.28 seconds
Started Jul 01 10:47:03 AM PDT 24
Finished Jul 01 10:47:05 AM PDT 24
Peak memory 196620 kb
Host smart-a5eaf766-efb2-4d23-a0c2-df9539b8460d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1849969630 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_smoke.1849969630
Directory /workspace/33.gpio_smoke/latest

Test location /workspace/coverage/default/33.gpio_smoke_no_pullup_pulldown.4025076461
Short name T690
Test name
Test status
Simulation time 1105854282 ps
CPU time 1.13 seconds
Started Jul 01 10:47:18 AM PDT 24
Finished Jul 01 10:47:20 AM PDT 24
Peak memory 196404 kb
Host smart-cedf9042-1179-4a9f-a954-8180f48439b1
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4025076461 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_smoke_no_pullup_pulldown.4025076461
Directory /workspace/33.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/33.gpio_stress_all.4164698039
Short name T627
Test name
Test status
Simulation time 53612894498 ps
CPU time 191.27 seconds
Started Jul 01 10:47:05 AM PDT 24
Finished Jul 01 10:50:18 AM PDT 24
Peak memory 198776 kb
Host smart-c87b24e7-3bcf-4f69-8df2-f4ef1f39dcc8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4164698039 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.
gpio_stress_all.4164698039
Directory /workspace/33.gpio_stress_all/latest

Test location /workspace/coverage/default/33.gpio_stress_all_with_rand_reset.3960091564
Short name T480
Test name
Test status
Simulation time 327521675538 ps
CPU time 2390.7 seconds
Started Jul 01 10:47:06 AM PDT 24
Finished Jul 01 11:26:59 AM PDT 24
Peak memory 198856 kb
Host smart-bb727e34-08ef-45cf-b078-c343540c23ed
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3960091564 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_stress_all_with_rand_reset.3960091564
Directory /workspace/33.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.gpio_alert_test.2515534464
Short name T304
Test name
Test status
Simulation time 16512819 ps
CPU time 0.58 seconds
Started Jul 01 10:47:07 AM PDT 24
Finished Jul 01 10:47:09 AM PDT 24
Peak memory 195400 kb
Host smart-117e9465-c3f6-49bc-8165-957f2aff5353
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2515534464 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_alert_test.2515534464
Directory /workspace/34.gpio_alert_test/latest

Test location /workspace/coverage/default/34.gpio_dout_din_regs_random_rw.2306218172
Short name T442
Test name
Test status
Simulation time 93616060 ps
CPU time 0.86 seconds
Started Jul 01 10:47:22 AM PDT 24
Finished Jul 01 10:47:24 AM PDT 24
Peak memory 196840 kb
Host smart-874ffe4f-5951-47b3-a45d-51c26802112f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2306218172 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_dout_din_regs_random_rw.2306218172
Directory /workspace/34.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/34.gpio_filter_stress.510808155
Short name T179
Test name
Test status
Simulation time 1468113224 ps
CPU time 16.65 seconds
Started Jul 01 10:47:05 AM PDT 24
Finished Jul 01 10:47:24 AM PDT 24
Peak memory 197580 kb
Host smart-cdc66ea5-7835-4590-a918-7d91637f8b3b
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=510808155 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_filter_stres
s.510808155
Directory /workspace/34.gpio_filter_stress/latest

Test location /workspace/coverage/default/34.gpio_full_random.2460083148
Short name T545
Test name
Test status
Simulation time 280926907 ps
CPU time 1.07 seconds
Started Jul 01 10:47:05 AM PDT 24
Finished Jul 01 10:47:09 AM PDT 24
Peak memory 197112 kb
Host smart-9e924a0e-2173-4258-8db3-00e31448b424
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2460083148 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_full_random.2460083148
Directory /workspace/34.gpio_full_random/latest

Test location /workspace/coverage/default/34.gpio_intr_rand_pgm.3801671726
Short name T130
Test name
Test status
Simulation time 120421337 ps
CPU time 1.09 seconds
Started Jul 01 10:47:04 AM PDT 24
Finished Jul 01 10:47:11 AM PDT 24
Peak memory 196776 kb
Host smart-3e8f2415-c51e-43c6-9c6e-5bb43688f900
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3801671726 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_intr_rand_pgm.3801671726
Directory /workspace/34.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/34.gpio_intr_with_filter_rand_intr_event.1285592329
Short name T137
Test name
Test status
Simulation time 72671266 ps
CPU time 0.91 seconds
Started Jul 01 10:47:09 AM PDT 24
Finished Jul 01 10:47:11 AM PDT 24
Peak memory 196380 kb
Host smart-eb0cc33a-536f-430c-85dc-b54c81c6498f
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1285592329 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 34.gpio_intr_with_filter_rand_intr_event.1285592329
Directory /workspace/34.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/34.gpio_rand_intr_trigger.2414102246
Short name T259
Test name
Test status
Simulation time 59634062 ps
CPU time 1.07 seconds
Started Jul 01 10:47:26 AM PDT 24
Finished Jul 01 10:47:28 AM PDT 24
Peak memory 196220 kb
Host smart-a164b27c-37d2-41d2-8030-da3a132b7862
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2414102246 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_rand_intr_trigger
.2414102246
Directory /workspace/34.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/34.gpio_random_dout_din.290712384
Short name T223
Test name
Test status
Simulation time 76763961 ps
CPU time 1.29 seconds
Started Jul 01 10:47:32 AM PDT 24
Finished Jul 01 10:47:39 AM PDT 24
Peak memory 197672 kb
Host smart-de295569-f5a2-4992-bdf6-c0f36d50009d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=290712384 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_random_dout_din.290712384
Directory /workspace/34.gpio_random_dout_din/latest

Test location /workspace/coverage/default/34.gpio_random_dout_din_no_pullup_pulldown.2223921584
Short name T567
Test name
Test status
Simulation time 60117876 ps
CPU time 0.76 seconds
Started Jul 01 10:47:04 AM PDT 24
Finished Jul 01 10:47:06 AM PDT 24
Peak memory 196816 kb
Host smart-941790b2-ec0e-46ed-9310-cf0e680bdddb
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2223921584 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_random_dout_din_no_pullu
p_pulldown.2223921584
Directory /workspace/34.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/34.gpio_smoke.972686398
Short name T220
Test name
Test status
Simulation time 70937217 ps
CPU time 1.35 seconds
Started Jul 01 10:47:05 AM PDT 24
Finished Jul 01 10:47:08 AM PDT 24
Peak memory 197408 kb
Host smart-78f8f6cd-db8a-4279-81e6-9e63c951f7ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=972686398 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_smoke.972686398
Directory /workspace/34.gpio_smoke/latest

Test location /workspace/coverage/default/34.gpio_smoke_no_pullup_pulldown.2211844603
Short name T70
Test name
Test status
Simulation time 68178812 ps
CPU time 1.14 seconds
Started Jul 01 10:47:25 AM PDT 24
Finished Jul 01 10:47:28 AM PDT 24
Peak memory 196136 kb
Host smart-3d7f8e86-a4cd-4a08-acb1-3c2ca26fcf0b
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2211844603 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_smoke_no_pullup_pulldown.2211844603
Directory /workspace/34.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/34.gpio_stress_all.2019276295
Short name T368
Test name
Test status
Simulation time 60196701538 ps
CPU time 226.92 seconds
Started Jul 01 10:47:23 AM PDT 24
Finished Jul 01 10:51:11 AM PDT 24
Peak memory 198780 kb
Host smart-d659d9ae-439c-4102-8d49-b65533aa7e8b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2019276295 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.
gpio_stress_all.2019276295
Directory /workspace/34.gpio_stress_all/latest

Test location /workspace/coverage/default/35.gpio_alert_test.1984064568
Short name T494
Test name
Test status
Simulation time 33487209 ps
CPU time 0.59 seconds
Started Jul 01 10:47:04 AM PDT 24
Finished Jul 01 10:47:07 AM PDT 24
Peak memory 195328 kb
Host smart-2390b015-9d6f-4134-9130-448d56ec9d8c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1984064568 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_alert_test.1984064568
Directory /workspace/35.gpio_alert_test/latest

Test location /workspace/coverage/default/35.gpio_dout_din_regs_random_rw.1018088286
Short name T306
Test name
Test status
Simulation time 59767842 ps
CPU time 0.78 seconds
Started Jul 01 10:47:30 AM PDT 24
Finished Jul 01 10:47:34 AM PDT 24
Peak memory 195988 kb
Host smart-c2e0eac7-2262-46e1-b35f-518380ad9a60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1018088286 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_dout_din_regs_random_rw.1018088286
Directory /workspace/35.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/35.gpio_filter_stress.4145049154
Short name T485
Test name
Test status
Simulation time 1745367271 ps
CPU time 13.01 seconds
Started Jul 01 10:47:26 AM PDT 24
Finished Jul 01 10:47:41 AM PDT 24
Peak memory 197728 kb
Host smart-3cca7ce9-fc36-4b64-88a7-46f13e9152c8
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4145049154 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_filter_stre
ss.4145049154
Directory /workspace/35.gpio_filter_stress/latest

Test location /workspace/coverage/default/35.gpio_full_random.3142115626
Short name T392
Test name
Test status
Simulation time 304855921 ps
CPU time 1.04 seconds
Started Jul 01 10:47:30 AM PDT 24
Finished Jul 01 10:47:34 AM PDT 24
Peak memory 197300 kb
Host smart-073d5bf6-1258-490b-8f89-3210c429c988
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3142115626 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_full_random.3142115626
Directory /workspace/35.gpio_full_random/latest

Test location /workspace/coverage/default/35.gpio_intr_rand_pgm.3376601144
Short name T114
Test name
Test status
Simulation time 43806766 ps
CPU time 1.32 seconds
Started Jul 01 10:47:05 AM PDT 24
Finished Jul 01 10:47:08 AM PDT 24
Peak memory 196808 kb
Host smart-797513c6-dcdf-45d6-ae24-36b7cf0be550
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3376601144 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_intr_rand_pgm.3376601144
Directory /workspace/35.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/35.gpio_intr_with_filter_rand_intr_event.2286559129
Short name T295
Test name
Test status
Simulation time 92621018 ps
CPU time 2.04 seconds
Started Jul 01 10:47:06 AM PDT 24
Finished Jul 01 10:47:10 AM PDT 24
Peak memory 198416 kb
Host smart-33e945a2-ab0e-40da-b580-c07bf006d0ee
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2286559129 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 35.gpio_intr_with_filter_rand_intr_event.2286559129
Directory /workspace/35.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/35.gpio_rand_intr_trigger.3983790361
Short name T170
Test name
Test status
Simulation time 431729429 ps
CPU time 3.55 seconds
Started Jul 01 10:47:10 AM PDT 24
Finished Jul 01 10:47:14 AM PDT 24
Peak memory 197476 kb
Host smart-ce431b40-5705-41c4-a479-d03601c3ea71
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3983790361 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_rand_intr_trigger
.3983790361
Directory /workspace/35.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/35.gpio_random_dout_din.3488119025
Short name T339
Test name
Test status
Simulation time 34074634 ps
CPU time 1.25 seconds
Started Jul 01 10:47:23 AM PDT 24
Finished Jul 01 10:47:25 AM PDT 24
Peak memory 197560 kb
Host smart-e47769ab-f4be-4675-a8f2-53fd9dcc174e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3488119025 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_random_dout_din.3488119025
Directory /workspace/35.gpio_random_dout_din/latest

Test location /workspace/coverage/default/35.gpio_random_dout_din_no_pullup_pulldown.978328133
Short name T243
Test name
Test status
Simulation time 41450939 ps
CPU time 1.13 seconds
Started Jul 01 10:47:05 AM PDT 24
Finished Jul 01 10:47:08 AM PDT 24
Peak memory 197764 kb
Host smart-f6b0e5c7-07c4-427b-af64-dd79226ded63
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=978328133 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_random_dout_din_no_pullup
_pulldown.978328133
Directory /workspace/35.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/35.gpio_random_long_reg_writes_reg_reads.2543042347
Short name T2
Test name
Test status
Simulation time 121800439 ps
CPU time 1.8 seconds
Started Jul 01 10:47:29 AM PDT 24
Finished Jul 01 10:47:34 AM PDT 24
Peak memory 198464 kb
Host smart-6a970cbf-9312-46d9-a82a-56ea58755517
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2543042347 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_ra
ndom_long_reg_writes_reg_reads.2543042347
Directory /workspace/35.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/35.gpio_smoke.811646792
Short name T617
Test name
Test status
Simulation time 90612612 ps
CPU time 0.85 seconds
Started Jul 01 10:47:21 AM PDT 24
Finished Jul 01 10:47:22 AM PDT 24
Peak memory 195880 kb
Host smart-0572d4e1-7420-4bd9-b2cf-098290ba76ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=811646792 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_smoke.811646792
Directory /workspace/35.gpio_smoke/latest

Test location /workspace/coverage/default/35.gpio_smoke_no_pullup_pulldown.2328168170
Short name T254
Test name
Test status
Simulation time 295729355 ps
CPU time 1.46 seconds
Started Jul 01 10:47:13 AM PDT 24
Finished Jul 01 10:47:16 AM PDT 24
Peak memory 198680 kb
Host smart-511f5b74-7378-422d-94ee-3d08575bbd33
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2328168170 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_smoke_no_pullup_pulldown.2328168170
Directory /workspace/35.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/35.gpio_stress_all.1420233110
Short name T572
Test name
Test status
Simulation time 2649095742 ps
CPU time 33.47 seconds
Started Jul 01 10:47:11 AM PDT 24
Finished Jul 01 10:47:45 AM PDT 24
Peak memory 198756 kb
Host smart-6605adcc-1c64-4b4c-8b92-9b2389fbd3dc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1420233110 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.
gpio_stress_all.1420233110
Directory /workspace/35.gpio_stress_all/latest

Test location /workspace/coverage/default/36.gpio_alert_test.2567864409
Short name T527
Test name
Test status
Simulation time 27626299 ps
CPU time 0.64 seconds
Started Jul 01 10:47:10 AM PDT 24
Finished Jul 01 10:47:11 AM PDT 24
Peak memory 194792 kb
Host smart-f842a9ae-6ad8-4f6a-b151-0c277a0bce0d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2567864409 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_alert_test.2567864409
Directory /workspace/36.gpio_alert_test/latest

Test location /workspace/coverage/default/36.gpio_dout_din_regs_random_rw.3514737301
Short name T310
Test name
Test status
Simulation time 62864891 ps
CPU time 0.68 seconds
Started Jul 01 10:47:10 AM PDT 24
Finished Jul 01 10:47:11 AM PDT 24
Peak memory 194828 kb
Host smart-f3ca82e1-c518-40ba-9d14-05497adaf2d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3514737301 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_dout_din_regs_random_rw.3514737301
Directory /workspace/36.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/36.gpio_filter_stress.3985478557
Short name T207
Test name
Test status
Simulation time 621463940 ps
CPU time 17.43 seconds
Started Jul 01 10:47:29 AM PDT 24
Finished Jul 01 10:47:50 AM PDT 24
Peak memory 197476 kb
Host smart-076b5496-dbd6-452b-b164-7f86aa5ef2b9
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3985478557 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_filter_stre
ss.3985478557
Directory /workspace/36.gpio_filter_stress/latest

Test location /workspace/coverage/default/36.gpio_full_random.2740500178
Short name T487
Test name
Test status
Simulation time 91593375 ps
CPU time 1.13 seconds
Started Jul 01 10:47:16 AM PDT 24
Finished Jul 01 10:47:18 AM PDT 24
Peak memory 197016 kb
Host smart-8f24345f-7507-4b3d-93e7-1ad437a87352
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2740500178 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_full_random.2740500178
Directory /workspace/36.gpio_full_random/latest

Test location /workspace/coverage/default/36.gpio_intr_rand_pgm.2086400327
Short name T667
Test name
Test status
Simulation time 179522916 ps
CPU time 1.27 seconds
Started Jul 01 10:47:27 AM PDT 24
Finished Jul 01 10:47:30 AM PDT 24
Peak memory 196548 kb
Host smart-28172804-7f32-46b2-b307-2fd3a01ad2c3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2086400327 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_intr_rand_pgm.2086400327
Directory /workspace/36.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/36.gpio_intr_with_filter_rand_intr_event.3443716717
Short name T599
Test name
Test status
Simulation time 164048728 ps
CPU time 3.25 seconds
Started Jul 01 10:47:16 AM PDT 24
Finished Jul 01 10:47:20 AM PDT 24
Peak memory 197100 kb
Host smart-7e1f766f-901c-489e-a493-2f5e3e9ef229
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3443716717 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 36.gpio_intr_with_filter_rand_intr_event.3443716717
Directory /workspace/36.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/36.gpio_rand_intr_trigger.446948105
Short name T19
Test name
Test status
Simulation time 494855272 ps
CPU time 2.27 seconds
Started Jul 01 10:47:28 AM PDT 24
Finished Jul 01 10:47:33 AM PDT 24
Peak memory 196568 kb
Host smart-701af644-3921-4831-b876-1cc206b38d82
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=446948105 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_rand_intr_trigger.
446948105
Directory /workspace/36.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/36.gpio_random_dout_din.2554226293
Short name T252
Test name
Test status
Simulation time 38709410 ps
CPU time 0.95 seconds
Started Jul 01 10:47:26 AM PDT 24
Finished Jul 01 10:47:28 AM PDT 24
Peak memory 196492 kb
Host smart-8d0c92eb-85ad-4f52-b38b-04ee5c9e50ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2554226293 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_random_dout_din.2554226293
Directory /workspace/36.gpio_random_dout_din/latest

Test location /workspace/coverage/default/36.gpio_random_dout_din_no_pullup_pulldown.94510573
Short name T569
Test name
Test status
Simulation time 18211861 ps
CPU time 0.71 seconds
Started Jul 01 10:47:03 AM PDT 24
Finished Jul 01 10:47:05 AM PDT 24
Peak memory 196072 kb
Host smart-21f56971-4da5-492e-8ab8-5b3dac0372cd
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94510573 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_random_dout_din_no_pullup_
pulldown.94510573
Directory /workspace/36.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/36.gpio_random_long_reg_writes_reg_reads.2685604902
Short name T266
Test name
Test status
Simulation time 127173080 ps
CPU time 2.83 seconds
Started Jul 01 10:47:09 AM PDT 24
Finished Jul 01 10:47:13 AM PDT 24
Peak memory 198452 kb
Host smart-69b200c7-b744-4338-a0c2-cc7141d52ab9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2685604902 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_ra
ndom_long_reg_writes_reg_reads.2685604902
Directory /workspace/36.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/36.gpio_smoke.123547472
Short name T258
Test name
Test status
Simulation time 132879185 ps
CPU time 0.8 seconds
Started Jul 01 10:47:26 AM PDT 24
Finished Jul 01 10:47:28 AM PDT 24
Peak memory 195920 kb
Host smart-222e765d-d322-4449-9351-27f7a1425b29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=123547472 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_smoke.123547472
Directory /workspace/36.gpio_smoke/latest

Test location /workspace/coverage/default/36.gpio_smoke_no_pullup_pulldown.599428588
Short name T706
Test name
Test status
Simulation time 66202857 ps
CPU time 0.92 seconds
Started Jul 01 10:47:27 AM PDT 24
Finished Jul 01 10:47:31 AM PDT 24
Peak memory 197036 kb
Host smart-cd769814-97c8-4095-b1c3-e48bd33b65ac
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=599428588 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_smoke_no_pullup_pulldown.599428588
Directory /workspace/36.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/36.gpio_stress_all.3968961161
Short name T542
Test name
Test status
Simulation time 15284941886 ps
CPU time 202.25 seconds
Started Jul 01 10:47:29 AM PDT 24
Finished Jul 01 10:50:55 AM PDT 24
Peak memory 198804 kb
Host smart-5576662e-0278-4c71-8191-1d439c8da3fc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3968961161 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.
gpio_stress_all.3968961161
Directory /workspace/36.gpio_stress_all/latest

Test location /workspace/coverage/default/37.gpio_alert_test.1592850453
Short name T270
Test name
Test status
Simulation time 51585745 ps
CPU time 0.55 seconds
Started Jul 01 10:47:23 AM PDT 24
Finished Jul 01 10:47:24 AM PDT 24
Peak memory 194832 kb
Host smart-85cfd6ac-8dc1-4f9a-a6df-41cbe3cda31c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1592850453 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_alert_test.1592850453
Directory /workspace/37.gpio_alert_test/latest

Test location /workspace/coverage/default/37.gpio_dout_din_regs_random_rw.4043336898
Short name T112
Test name
Test status
Simulation time 75941528 ps
CPU time 0.67 seconds
Started Jul 01 10:47:27 AM PDT 24
Finished Jul 01 10:47:30 AM PDT 24
Peak memory 194664 kb
Host smart-4abc7f4d-8490-486c-a954-9e04235d8090
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4043336898 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_dout_din_regs_random_rw.4043336898
Directory /workspace/37.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/37.gpio_filter_stress.2309329542
Short name T464
Test name
Test status
Simulation time 3257609120 ps
CPU time 21.49 seconds
Started Jul 01 10:47:23 AM PDT 24
Finished Jul 01 10:47:53 AM PDT 24
Peak memory 196528 kb
Host smart-1cd1b897-d35a-4602-be1f-82269f321460
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2309329542 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_filter_stre
ss.2309329542
Directory /workspace/37.gpio_filter_stress/latest

Test location /workspace/coverage/default/37.gpio_full_random.3020720652
Short name T551
Test name
Test status
Simulation time 450824381 ps
CPU time 1.06 seconds
Started Jul 01 10:47:23 AM PDT 24
Finished Jul 01 10:47:25 AM PDT 24
Peak memory 197012 kb
Host smart-cbff40c2-e70b-4727-9b1b-5fa5e8ac7d89
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3020720652 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_full_random.3020720652
Directory /workspace/37.gpio_full_random/latest

Test location /workspace/coverage/default/37.gpio_intr_rand_pgm.2697630600
Short name T474
Test name
Test status
Simulation time 72178615 ps
CPU time 1.07 seconds
Started Jul 01 10:47:32 AM PDT 24
Finished Jul 01 10:47:36 AM PDT 24
Peak memory 196444 kb
Host smart-ecb7daca-a24c-4f73-a843-726a281a4956
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2697630600 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_intr_rand_pgm.2697630600
Directory /workspace/37.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/37.gpio_intr_with_filter_rand_intr_event.3748810468
Short name T601
Test name
Test status
Simulation time 57456900 ps
CPU time 2.27 seconds
Started Jul 01 10:47:28 AM PDT 24
Finished Jul 01 10:47:32 AM PDT 24
Peak memory 196860 kb
Host smart-963ab689-08da-4c6e-9eb4-5457afc9a61f
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3748810468 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 37.gpio_intr_with_filter_rand_intr_event.3748810468
Directory /workspace/37.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/37.gpio_rand_intr_trigger.923915355
Short name T629
Test name
Test status
Simulation time 118225701 ps
CPU time 3.59 seconds
Started Jul 01 10:47:29 AM PDT 24
Finished Jul 01 10:47:36 AM PDT 24
Peak memory 198720 kb
Host smart-fa9e760e-022e-4415-9fa8-3d3bb02b0219
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=923915355 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_rand_intr_trigger.
923915355
Directory /workspace/37.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/37.gpio_random_dout_din.2810095627
Short name T434
Test name
Test status
Simulation time 28827746 ps
CPU time 0.76 seconds
Started Jul 01 10:47:32 AM PDT 24
Finished Jul 01 10:47:36 AM PDT 24
Peak memory 196156 kb
Host smart-c40476c9-b26d-4a9d-a3af-79866ad83410
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2810095627 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_random_dout_din.2810095627
Directory /workspace/37.gpio_random_dout_din/latest

Test location /workspace/coverage/default/37.gpio_random_dout_din_no_pullup_pulldown.4211448962
Short name T224
Test name
Test status
Simulation time 17190773 ps
CPU time 0.79 seconds
Started Jul 01 10:47:24 AM PDT 24
Finished Jul 01 10:47:26 AM PDT 24
Peak memory 196104 kb
Host smart-781a1299-d4b6-4d1e-b94a-0669b16068a4
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4211448962 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_random_dout_din_no_pullu
p_pulldown.4211448962
Directory /workspace/37.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/37.gpio_random_long_reg_writes_reg_reads.2175471677
Short name T505
Test name
Test status
Simulation time 39903721 ps
CPU time 1.01 seconds
Started Jul 01 10:47:21 AM PDT 24
Finished Jul 01 10:47:22 AM PDT 24
Peak memory 197108 kb
Host smart-863e6f04-fbee-4c5f-89a0-e71809cab1e0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2175471677 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_ra
ndom_long_reg_writes_reg_reads.2175471677
Directory /workspace/37.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/37.gpio_smoke.1765596124
Short name T582
Test name
Test status
Simulation time 132849346 ps
CPU time 0.83 seconds
Started Jul 01 10:47:25 AM PDT 24
Finished Jul 01 10:47:27 AM PDT 24
Peak memory 195912 kb
Host smart-6aebbe7f-833d-43cd-b2ce-e78c0863a6d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1765596124 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_smoke.1765596124
Directory /workspace/37.gpio_smoke/latest

Test location /workspace/coverage/default/37.gpio_smoke_no_pullup_pulldown.7254405
Short name T124
Test name
Test status
Simulation time 65943406 ps
CPU time 1.13 seconds
Started Jul 01 10:47:28 AM PDT 24
Finished Jul 01 10:47:32 AM PDT 24
Peak memory 196428 kb
Host smart-a6c021dc-d5fd-4283-8016-d2d866d3c3dc
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=7254405 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_smoke_no_pullup_pulldown.7254405
Directory /workspace/37.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/37.gpio_stress_all.1779496589
Short name T555
Test name
Test status
Simulation time 295216860156 ps
CPU time 162.71 seconds
Started Jul 01 10:47:54 AM PDT 24
Finished Jul 01 10:50:38 AM PDT 24
Peak memory 198788 kb
Host smart-2600359b-f970-4b5b-ab45-c6109643d817
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1779496589 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.
gpio_stress_all.1779496589
Directory /workspace/37.gpio_stress_all/latest

Test location /workspace/coverage/default/37.gpio_stress_all_with_rand_reset.3934623682
Short name T60
Test name
Test status
Simulation time 58529870663 ps
CPU time 465.69 seconds
Started Jul 01 10:47:23 AM PDT 24
Finished Jul 01 10:55:09 AM PDT 24
Peak memory 198884 kb
Host smart-cd4aa097-292e-4140-bd9b-cb7179eed895
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3934623682 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_stress_all_with_rand_reset.3934623682
Directory /workspace/37.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.gpio_alert_test.2642133866
Short name T532
Test name
Test status
Simulation time 24373741 ps
CPU time 0.56 seconds
Started Jul 01 10:47:23 AM PDT 24
Finished Jul 01 10:47:25 AM PDT 24
Peak memory 194120 kb
Host smart-2cf8b719-3e21-42b9-874c-26e0c2a76632
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2642133866 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_alert_test.2642133866
Directory /workspace/38.gpio_alert_test/latest

Test location /workspace/coverage/default/38.gpio_dout_din_regs_random_rw.1829199086
Short name T287
Test name
Test status
Simulation time 38838272 ps
CPU time 0.72 seconds
Started Jul 01 10:47:15 AM PDT 24
Finished Jul 01 10:47:17 AM PDT 24
Peak memory 195952 kb
Host smart-d0f7c00f-05da-49a0-ba2f-1cb2a53f366c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1829199086 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_dout_din_regs_random_rw.1829199086
Directory /workspace/38.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/38.gpio_filter_stress.1151516622
Short name T67
Test name
Test status
Simulation time 609446476 ps
CPU time 21.34 seconds
Started Jul 01 10:47:29 AM PDT 24
Finished Jul 01 10:47:53 AM PDT 24
Peak memory 197436 kb
Host smart-f7ff627a-e8ab-492d-8c46-6227be27b57e
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1151516622 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_filter_stre
ss.1151516622
Directory /workspace/38.gpio_filter_stress/latest

Test location /workspace/coverage/default/38.gpio_full_random.1606318441
Short name T406
Test name
Test status
Simulation time 71870040 ps
CPU time 0.79 seconds
Started Jul 01 10:47:30 AM PDT 24
Finished Jul 01 10:47:37 AM PDT 24
Peak memory 197196 kb
Host smart-18b7450e-09a2-41d6-8a98-6b84111d65ee
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1606318441 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_full_random.1606318441
Directory /workspace/38.gpio_full_random/latest

Test location /workspace/coverage/default/38.gpio_intr_rand_pgm.3259543402
Short name T577
Test name
Test status
Simulation time 227805859 ps
CPU time 1.11 seconds
Started Jul 01 10:47:25 AM PDT 24
Finished Jul 01 10:47:27 AM PDT 24
Peak memory 197496 kb
Host smart-bf71032d-8846-46cf-a782-7056210a22b2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3259543402 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_intr_rand_pgm.3259543402
Directory /workspace/38.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/38.gpio_intr_with_filter_rand_intr_event.1355557370
Short name T647
Test name
Test status
Simulation time 144960491 ps
CPU time 1.54 seconds
Started Jul 01 10:47:31 AM PDT 24
Finished Jul 01 10:47:36 AM PDT 24
Peak memory 197192 kb
Host smart-d8b441be-7dec-4b0a-a077-05c34f6d0ae4
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1355557370 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 38.gpio_intr_with_filter_rand_intr_event.1355557370
Directory /workspace/38.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/38.gpio_rand_intr_trigger.4241659851
Short name T341
Test name
Test status
Simulation time 464982301 ps
CPU time 1.95 seconds
Started Jul 01 10:47:17 AM PDT 24
Finished Jul 01 10:47:20 AM PDT 24
Peak memory 196752 kb
Host smart-ad7078ab-0110-4e76-a6b1-1fe504230bae
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4241659851 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_rand_intr_trigger
.4241659851
Directory /workspace/38.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/38.gpio_random_dout_din.1170682600
Short name T204
Test name
Test status
Simulation time 186396276 ps
CPU time 1 seconds
Started Jul 01 10:47:30 AM PDT 24
Finished Jul 01 10:47:35 AM PDT 24
Peak memory 196468 kb
Host smart-feefffe8-ab19-4fe7-8b07-ebfa704f1997
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1170682600 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_random_dout_din.1170682600
Directory /workspace/38.gpio_random_dout_din/latest

Test location /workspace/coverage/default/38.gpio_random_dout_din_no_pullup_pulldown.587407566
Short name T477
Test name
Test status
Simulation time 25822104 ps
CPU time 0.91 seconds
Started Jul 01 10:47:17 AM PDT 24
Finished Jul 01 10:47:18 AM PDT 24
Peak memory 196696 kb
Host smart-579f570d-b0ba-42e3-b4a1-0dd8578fa2ef
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=587407566 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_random_dout_din_no_pullup
_pulldown.587407566
Directory /workspace/38.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/38.gpio_random_long_reg_writes_reg_reads.3819398159
Short name T228
Test name
Test status
Simulation time 243184373 ps
CPU time 3.85 seconds
Started Jul 01 10:47:19 AM PDT 24
Finished Jul 01 10:47:24 AM PDT 24
Peak memory 197780 kb
Host smart-becb8900-902a-4518-bea3-7995c9569ab0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3819398159 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_ra
ndom_long_reg_writes_reg_reads.3819398159
Directory /workspace/38.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/38.gpio_smoke.992321881
Short name T408
Test name
Test status
Simulation time 92064598 ps
CPU time 0.89 seconds
Started Jul 01 10:47:43 AM PDT 24
Finished Jul 01 10:47:45 AM PDT 24
Peak memory 196196 kb
Host smart-7b581853-4903-4619-9a5f-f47432d83bd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=992321881 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_smoke.992321881
Directory /workspace/38.gpio_smoke/latest

Test location /workspace/coverage/default/38.gpio_smoke_no_pullup_pulldown.2865986067
Short name T658
Test name
Test status
Simulation time 205107024 ps
CPU time 1.48 seconds
Started Jul 01 10:47:24 AM PDT 24
Finished Jul 01 10:47:26 AM PDT 24
Peak memory 196292 kb
Host smart-f5d00be7-a792-4ff4-ba37-daf71c3cee32
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2865986067 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_smoke_no_pullup_pulldown.2865986067
Directory /workspace/38.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/38.gpio_stress_all.702048194
Short name T319
Test name
Test status
Simulation time 18835514665 ps
CPU time 114.79 seconds
Started Jul 01 10:47:15 AM PDT 24
Finished Jul 01 10:49:12 AM PDT 24
Peak memory 198752 kb
Host smart-dd473fb5-3c99-4b4b-853f-8ed5f4fe0496
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=702048194 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.g
pio_stress_all.702048194
Directory /workspace/38.gpio_stress_all/latest

Test location /workspace/coverage/default/39.gpio_alert_test.2708723768
Short name T344
Test name
Test status
Simulation time 56499169 ps
CPU time 0.57 seconds
Started Jul 01 10:47:33 AM PDT 24
Finished Jul 01 10:47:36 AM PDT 24
Peak memory 194608 kb
Host smart-b27e6e59-385f-4c4c-bf62-27e265fed9ed
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2708723768 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_alert_test.2708723768
Directory /workspace/39.gpio_alert_test/latest

Test location /workspace/coverage/default/39.gpio_dout_din_regs_random_rw.2798334516
Short name T490
Test name
Test status
Simulation time 79084288 ps
CPU time 0.96 seconds
Started Jul 01 10:47:29 AM PDT 24
Finished Jul 01 10:47:33 AM PDT 24
Peak memory 197228 kb
Host smart-057d5392-2b1a-49d6-8220-c38f9411ada9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2798334516 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_dout_din_regs_random_rw.2798334516
Directory /workspace/39.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/39.gpio_filter_stress.3579156093
Short name T181
Test name
Test status
Simulation time 1963024154 ps
CPU time 25.21 seconds
Started Jul 01 10:47:25 AM PDT 24
Finished Jul 01 10:47:51 AM PDT 24
Peak memory 197788 kb
Host smart-1367574f-46ed-4e8d-afcd-6d2db1a79ae5
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3579156093 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_filter_stre
ss.3579156093
Directory /workspace/39.gpio_filter_stress/latest

Test location /workspace/coverage/default/39.gpio_full_random.1125191970
Short name T233
Test name
Test status
Simulation time 131891793 ps
CPU time 0.78 seconds
Started Jul 01 10:47:32 AM PDT 24
Finished Jul 01 10:47:35 AM PDT 24
Peak memory 196432 kb
Host smart-f812ade2-11a4-4cdd-b9f6-8d41d0ae7aa3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1125191970 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_full_random.1125191970
Directory /workspace/39.gpio_full_random/latest

Test location /workspace/coverage/default/39.gpio_intr_rand_pgm.1498227261
Short name T655
Test name
Test status
Simulation time 32976838 ps
CPU time 0.95 seconds
Started Jul 01 10:47:25 AM PDT 24
Finished Jul 01 10:47:27 AM PDT 24
Peak memory 196420 kb
Host smart-b66f6d0d-b23b-49d7-a90d-f095067ee3aa
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1498227261 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_intr_rand_pgm.1498227261
Directory /workspace/39.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/39.gpio_intr_with_filter_rand_intr_event.1831992201
Short name T176
Test name
Test status
Simulation time 328258123 ps
CPU time 3.53 seconds
Started Jul 01 10:47:26 AM PDT 24
Finished Jul 01 10:47:32 AM PDT 24
Peak memory 198752 kb
Host smart-e856231e-8975-4571-acd6-026e4ed654b5
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1831992201 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 39.gpio_intr_with_filter_rand_intr_event.1831992201
Directory /workspace/39.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/39.gpio_rand_intr_trigger.2949306701
Short name T451
Test name
Test status
Simulation time 52788445 ps
CPU time 1.33 seconds
Started Jul 01 10:47:29 AM PDT 24
Finished Jul 01 10:47:33 AM PDT 24
Peak memory 196760 kb
Host smart-37235e69-c35f-4678-b641-c8bd391984c3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2949306701 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_rand_intr_trigger
.2949306701
Directory /workspace/39.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/39.gpio_random_dout_din.1907371899
Short name T453
Test name
Test status
Simulation time 33694452 ps
CPU time 1.13 seconds
Started Jul 01 10:47:22 AM PDT 24
Finished Jul 01 10:47:23 AM PDT 24
Peak memory 198716 kb
Host smart-6f956651-60c8-4f03-b429-c348865e1b19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1907371899 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_random_dout_din.1907371899
Directory /workspace/39.gpio_random_dout_din/latest

Test location /workspace/coverage/default/39.gpio_random_dout_din_no_pullup_pulldown.1845659875
Short name T475
Test name
Test status
Simulation time 52325639 ps
CPU time 1.06 seconds
Started Jul 01 10:47:28 AM PDT 24
Finished Jul 01 10:47:32 AM PDT 24
Peak memory 197360 kb
Host smart-8e76aca2-35b1-4f5c-9438-17eb0f036f04
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1845659875 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_random_dout_din_no_pullu
p_pulldown.1845659875
Directory /workspace/39.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/39.gpio_random_long_reg_writes_reg_reads.492784984
Short name T346
Test name
Test status
Simulation time 351094216 ps
CPU time 5.19 seconds
Started Jul 01 10:47:29 AM PDT 24
Finished Jul 01 10:47:37 AM PDT 24
Peak memory 197520 kb
Host smart-1b64f282-1b60-43c2-a447-6c4b84587fa5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=492784984 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_ran
dom_long_reg_writes_reg_reads.492784984
Directory /workspace/39.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/39.gpio_smoke.536747980
Short name T428
Test name
Test status
Simulation time 86854339 ps
CPU time 0.89 seconds
Started Jul 01 10:47:27 AM PDT 24
Finished Jul 01 10:47:31 AM PDT 24
Peak memory 197156 kb
Host smart-ac0ce6f6-3295-4d91-a0c0-e17557a83215
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=536747980 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_smoke.536747980
Directory /workspace/39.gpio_smoke/latest

Test location /workspace/coverage/default/39.gpio_smoke_no_pullup_pulldown.117708147
Short name T219
Test name
Test status
Simulation time 235938880 ps
CPU time 1.24 seconds
Started Jul 01 10:47:26 AM PDT 24
Finished Jul 01 10:47:29 AM PDT 24
Peak memory 197480 kb
Host smart-25a403f7-6c13-4e49-adcf-fa9f4bd04418
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=117708147 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_smoke_no_pullup_pulldown.117708147
Directory /workspace/39.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/39.gpio_stress_all.4264615224
Short name T521
Test name
Test status
Simulation time 34356793905 ps
CPU time 153.05 seconds
Started Jul 01 10:47:27 AM PDT 24
Finished Jul 01 10:50:03 AM PDT 24
Peak memory 198756 kb
Host smart-18f1fa8b-663c-4235-9b01-5158e0dd3753
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4264615224 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.
gpio_stress_all.4264615224
Directory /workspace/39.gpio_stress_all/latest

Test location /workspace/coverage/default/4.gpio_alert_test.1585129797
Short name T523
Test name
Test status
Simulation time 16662234 ps
CPU time 0.58 seconds
Started Jul 01 10:46:28 AM PDT 24
Finished Jul 01 10:46:29 AM PDT 24
Peak memory 194836 kb
Host smart-e8cdf818-3bad-42f9-9986-e8bfb3eeba59
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1585129797 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_alert_test.1585129797
Directory /workspace/4.gpio_alert_test/latest

Test location /workspace/coverage/default/4.gpio_dout_din_regs_random_rw.2256828077
Short name T174
Test name
Test status
Simulation time 57075845 ps
CPU time 0.62 seconds
Started Jul 01 10:46:13 AM PDT 24
Finished Jul 01 10:46:15 AM PDT 24
Peak memory 195308 kb
Host smart-653025ba-4734-4c67-9e90-e1b1f81c7e35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2256828077 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_dout_din_regs_random_rw.2256828077
Directory /workspace/4.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/4.gpio_filter_stress.1199338953
Short name T206
Test name
Test status
Simulation time 11560769435 ps
CPU time 26.99 seconds
Started Jul 01 10:46:11 AM PDT 24
Finished Jul 01 10:46:39 AM PDT 24
Peak memory 197284 kb
Host smart-55aaf2d7-bf86-4da5-9907-beaf9861c0fb
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1199338953 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_filter_stres
s.1199338953
Directory /workspace/4.gpio_filter_stress/latest

Test location /workspace/coverage/default/4.gpio_full_random.825557272
Short name T630
Test name
Test status
Simulation time 32204026 ps
CPU time 0.67 seconds
Started Jul 01 10:46:14 AM PDT 24
Finished Jul 01 10:46:15 AM PDT 24
Peak memory 195208 kb
Host smart-aae49b0d-c0b3-434a-8528-e9abfdc7c04c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=825557272 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_full_random.825557272
Directory /workspace/4.gpio_full_random/latest

Test location /workspace/coverage/default/4.gpio_intr_rand_pgm.3041498401
Short name T58
Test name
Test status
Simulation time 93692811 ps
CPU time 1.42 seconds
Started Jul 01 10:46:23 AM PDT 24
Finished Jul 01 10:46:24 AM PDT 24
Peak memory 198696 kb
Host smart-47ec6efa-bcc8-4bd8-a677-cf95d459f136
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3041498401 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_intr_rand_pgm.3041498401
Directory /workspace/4.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/4.gpio_intr_with_filter_rand_intr_event.443952581
Short name T708
Test name
Test status
Simulation time 81694965 ps
CPU time 1.69 seconds
Started Jul 01 10:46:12 AM PDT 24
Finished Jul 01 10:46:15 AM PDT 24
Peak memory 197308 kb
Host smart-550f4c39-2fc5-4b2c-8849-2b23066e70b5
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=443952581 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 4.gpio_intr_with_filter_rand_intr_event.443952581
Directory /workspace/4.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/4.gpio_rand_intr_trigger.1000867557
Short name T335
Test name
Test status
Simulation time 1419258151 ps
CPU time 2.82 seconds
Started Jul 01 10:46:37 AM PDT 24
Finished Jul 01 10:46:45 AM PDT 24
Peak memory 197792 kb
Host smart-5542327e-79b5-44e8-906c-887ce3ffe27e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1000867557 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_rand_intr_trigger.
1000867557
Directory /workspace/4.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/4.gpio_random_dout_din.3699572372
Short name T430
Test name
Test status
Simulation time 59119891 ps
CPU time 1.27 seconds
Started Jul 01 10:46:09 AM PDT 24
Finished Jul 01 10:46:11 AM PDT 24
Peak memory 197716 kb
Host smart-4b40b3e0-6145-4ff5-80a2-7213dcc5446e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3699572372 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_random_dout_din.3699572372
Directory /workspace/4.gpio_random_dout_din/latest

Test location /workspace/coverage/default/4.gpio_random_dout_din_no_pullup_pulldown.1556789225
Short name T175
Test name
Test status
Simulation time 146668789 ps
CPU time 0.98 seconds
Started Jul 01 10:46:36 AM PDT 24
Finished Jul 01 10:46:41 AM PDT 24
Peak memory 197200 kb
Host smart-43362d50-5120-4866-a5f9-67b826f948be
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1556789225 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_random_dout_din_no_pullup
_pulldown.1556789225
Directory /workspace/4.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/4.gpio_random_long_reg_writes_reg_reads.836109436
Short name T414
Test name
Test status
Simulation time 1243291617 ps
CPU time 3.78 seconds
Started Jul 01 10:46:32 AM PDT 24
Finished Jul 01 10:46:37 AM PDT 24
Peak memory 198604 kb
Host smart-c19d2098-3952-472c-883f-687ce38062c7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=836109436 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_rand
om_long_reg_writes_reg_reads.836109436
Directory /workspace/4.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/4.gpio_sec_cm.1060406809
Short name T49
Test name
Test status
Simulation time 40421292 ps
CPU time 0.81 seconds
Started Jul 01 10:46:36 AM PDT 24
Finished Jul 01 10:46:42 AM PDT 24
Peak memory 214208 kb
Host smart-f405ad20-9662-4a46-9b4b-7cbf5a1d7623
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1060406809 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_sec_cm.1060406809
Directory /workspace/4.gpio_sec_cm/latest

Test location /workspace/coverage/default/4.gpio_smoke.1794712848
Short name T449
Test name
Test status
Simulation time 263267345 ps
CPU time 1.04 seconds
Started Jul 01 10:46:30 AM PDT 24
Finished Jul 01 10:46:31 AM PDT 24
Peak memory 196224 kb
Host smart-bd295b4d-bb65-4853-b82f-c3b4f4a69ea9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1794712848 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_smoke.1794712848
Directory /workspace/4.gpio_smoke/latest

Test location /workspace/coverage/default/4.gpio_smoke_no_pullup_pulldown.3120134739
Short name T157
Test name
Test status
Simulation time 309001885 ps
CPU time 1.05 seconds
Started Jul 01 10:46:10 AM PDT 24
Finished Jul 01 10:46:11 AM PDT 24
Peak memory 196208 kb
Host smart-3786038e-5d2c-4ef8-bf02-12fcab6da8ec
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3120134739 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_smoke_no_pullup_pulldown.3120134739
Directory /workspace/4.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/4.gpio_stress_all.2474415733
Short name T9
Test name
Test status
Simulation time 9462901714 ps
CPU time 106.47 seconds
Started Jul 01 10:46:12 AM PDT 24
Finished Jul 01 10:48:00 AM PDT 24
Peak memory 198800 kb
Host smart-f7f9df2b-f840-48d1-b45a-0df00ef311d4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2474415733 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.g
pio_stress_all.2474415733
Directory /workspace/4.gpio_stress_all/latest

Test location /workspace/coverage/default/4.gpio_stress_all_with_rand_reset.1806101478
Short name T640
Test name
Test status
Simulation time 64170162238 ps
CPU time 1284.76 seconds
Started Jul 01 10:46:27 AM PDT 24
Finished Jul 01 11:07:52 AM PDT 24
Peak memory 198904 kb
Host smart-0e71be99-867d-469b-9602-0eb56ea55097
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1806101478 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_stress_all_with_rand_reset.1806101478
Directory /workspace/4.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.gpio_alert_test.2484254182
Short name T571
Test name
Test status
Simulation time 11706154 ps
CPU time 0.56 seconds
Started Jul 01 10:47:28 AM PDT 24
Finished Jul 01 10:47:32 AM PDT 24
Peak memory 194640 kb
Host smart-95c44eaa-6900-4ede-8a0b-c574c1464590
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2484254182 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_alert_test.2484254182
Directory /workspace/40.gpio_alert_test/latest

Test location /workspace/coverage/default/40.gpio_dout_din_regs_random_rw.1855099026
Short name T677
Test name
Test status
Simulation time 71932680 ps
CPU time 0.83 seconds
Started Jul 01 10:47:26 AM PDT 24
Finished Jul 01 10:47:28 AM PDT 24
Peak memory 196024 kb
Host smart-2664039f-9d28-4592-8b21-e9227ace1b8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1855099026 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_dout_din_regs_random_rw.1855099026
Directory /workspace/40.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/40.gpio_filter_stress.4056049723
Short name T68
Test name
Test status
Simulation time 1000044224 ps
CPU time 7.21 seconds
Started Jul 01 10:47:25 AM PDT 24
Finished Jul 01 10:47:34 AM PDT 24
Peak memory 197600 kb
Host smart-c0171329-3c30-4cb9-9a02-bbcf4e1197c7
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4056049723 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_filter_stre
ss.4056049723
Directory /workspace/40.gpio_filter_stress/latest

Test location /workspace/coverage/default/40.gpio_full_random.3905170422
Short name T558
Test name
Test status
Simulation time 276802355 ps
CPU time 0.94 seconds
Started Jul 01 10:47:45 AM PDT 24
Finished Jul 01 10:47:47 AM PDT 24
Peak memory 198416 kb
Host smart-d4cb1830-a3b2-49ae-9ccc-c7e2bd86b31e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3905170422 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_full_random.3905170422
Directory /workspace/40.gpio_full_random/latest

Test location /workspace/coverage/default/40.gpio_intr_rand_pgm.3663979005
Short name T394
Test name
Test status
Simulation time 450158008 ps
CPU time 1.47 seconds
Started Jul 01 10:47:50 AM PDT 24
Finished Jul 01 10:47:52 AM PDT 24
Peak memory 197820 kb
Host smart-b7d535fe-815b-4045-9d4c-930478f2cd88
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3663979005 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_intr_rand_pgm.3663979005
Directory /workspace/40.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/40.gpio_intr_with_filter_rand_intr_event.3421936986
Short name T101
Test name
Test status
Simulation time 74873613 ps
CPU time 0.9 seconds
Started Jul 01 10:47:30 AM PDT 24
Finished Jul 01 10:47:34 AM PDT 24
Peak memory 197512 kb
Host smart-e5e5daf7-dfe3-4c25-a553-9dcaecbce682
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3421936986 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 40.gpio_intr_with_filter_rand_intr_event.3421936986
Directory /workspace/40.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/40.gpio_rand_intr_trigger.2625788238
Short name T499
Test name
Test status
Simulation time 278556893 ps
CPU time 1.21 seconds
Started Jul 01 10:47:30 AM PDT 24
Finished Jul 01 10:47:35 AM PDT 24
Peak memory 197164 kb
Host smart-dc56b077-4bc6-4038-b861-f8970a478682
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2625788238 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_rand_intr_trigger
.2625788238
Directory /workspace/40.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/40.gpio_random_dout_din.2872737204
Short name T277
Test name
Test status
Simulation time 24611653 ps
CPU time 0.76 seconds
Started Jul 01 10:48:11 AM PDT 24
Finished Jul 01 10:48:13 AM PDT 24
Peak memory 196064 kb
Host smart-78c63049-0080-48b1-abad-2f912393ece5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2872737204 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_random_dout_din.2872737204
Directory /workspace/40.gpio_random_dout_din/latest

Test location /workspace/coverage/default/40.gpio_random_dout_din_no_pullup_pulldown.2187515244
Short name T646
Test name
Test status
Simulation time 41815077 ps
CPU time 1.08 seconds
Started Jul 01 10:47:27 AM PDT 24
Finished Jul 01 10:47:31 AM PDT 24
Peak memory 197396 kb
Host smart-9590bc69-81b8-43b8-bed2-90d913fac03c
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2187515244 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_random_dout_din_no_pullu
p_pulldown.2187515244
Directory /workspace/40.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/40.gpio_random_long_reg_writes_reg_reads.3727751403
Short name T388
Test name
Test status
Simulation time 32612919 ps
CPU time 1.66 seconds
Started Jul 01 10:48:06 AM PDT 24
Finished Jul 01 10:48:09 AM PDT 24
Peak memory 198636 kb
Host smart-bc5b6911-48d7-4391-913a-58fd10359e83
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3727751403 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_ra
ndom_long_reg_writes_reg_reads.3727751403
Directory /workspace/40.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/40.gpio_smoke.464370602
Short name T673
Test name
Test status
Simulation time 190429770 ps
CPU time 1.27 seconds
Started Jul 01 10:47:26 AM PDT 24
Finished Jul 01 10:47:28 AM PDT 24
Peak memory 197480 kb
Host smart-ed71c79b-1ef9-4071-9eb3-e1d7aee3b58e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=464370602 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_smoke.464370602
Directory /workspace/40.gpio_smoke/latest

Test location /workspace/coverage/default/40.gpio_smoke_no_pullup_pulldown.799636179
Short name T568
Test name
Test status
Simulation time 75490011 ps
CPU time 0.88 seconds
Started Jul 01 10:47:45 AM PDT 24
Finished Jul 01 10:47:47 AM PDT 24
Peak memory 197612 kb
Host smart-1cdabf77-add2-4184-a6d4-f698594e9df2
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=799636179 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_smoke_no_pullup_pulldown.799636179
Directory /workspace/40.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/40.gpio_stress_all.295884773
Short name T105
Test name
Test status
Simulation time 12779452732 ps
CPU time 71.61 seconds
Started Jul 01 10:47:33 AM PDT 24
Finished Jul 01 10:48:47 AM PDT 24
Peak memory 198752 kb
Host smart-41be0d43-a7af-4b2c-bf21-4afa5511c988
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=295884773 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.g
pio_stress_all.295884773
Directory /workspace/40.gpio_stress_all/latest

Test location /workspace/coverage/default/40.gpio_stress_all_with_rand_reset.3186071096
Short name T29
Test name
Test status
Simulation time 558842931523 ps
CPU time 2625.66 seconds
Started Jul 01 10:47:33 AM PDT 24
Finished Jul 01 11:31:21 AM PDT 24
Peak memory 198864 kb
Host smart-8e990735-36c0-4a97-9185-0b3958c66d31
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3186071096 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_stress_all_with_rand_reset.3186071096
Directory /workspace/40.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.gpio_alert_test.3896491863
Short name T702
Test name
Test status
Simulation time 38771269 ps
CPU time 0.56 seconds
Started Jul 01 10:47:29 AM PDT 24
Finished Jul 01 10:47:33 AM PDT 24
Peak memory 194440 kb
Host smart-65362d72-5eae-4909-81dd-fc5b82d54c7a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3896491863 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_alert_test.3896491863
Directory /workspace/41.gpio_alert_test/latest

Test location /workspace/coverage/default/41.gpio_dout_din_regs_random_rw.4113075757
Short name T538
Test name
Test status
Simulation time 104743562 ps
CPU time 0.87 seconds
Started Jul 01 10:47:25 AM PDT 24
Finished Jul 01 10:47:27 AM PDT 24
Peak memory 196980 kb
Host smart-6ee23058-130e-4376-b2ef-f15c8725619e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4113075757 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_dout_din_regs_random_rw.4113075757
Directory /workspace/41.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/41.gpio_filter_stress.536062913
Short name T134
Test name
Test status
Simulation time 2137765108 ps
CPU time 14.83 seconds
Started Jul 01 10:47:59 AM PDT 24
Finished Jul 01 10:48:15 AM PDT 24
Peak memory 197716 kb
Host smart-21b95662-ee37-4d9b-a090-52ee6f59840a
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=536062913 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_filter_stres
s.536062913
Directory /workspace/41.gpio_filter_stress/latest

Test location /workspace/coverage/default/41.gpio_full_random.3770886199
Short name T626
Test name
Test status
Simulation time 144070974 ps
CPU time 0.74 seconds
Started Jul 01 10:47:28 AM PDT 24
Finished Jul 01 10:47:32 AM PDT 24
Peak memory 195188 kb
Host smart-eaa170d7-371c-4f1e-8f91-f3f22f9fa8b6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3770886199 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_full_random.3770886199
Directory /workspace/41.gpio_full_random/latest

Test location /workspace/coverage/default/41.gpio_intr_rand_pgm.897938146
Short name T714
Test name
Test status
Simulation time 307761266 ps
CPU time 1.23 seconds
Started Jul 01 10:47:38 AM PDT 24
Finished Jul 01 10:47:40 AM PDT 24
Peak memory 197328 kb
Host smart-822a7641-139e-4bd2-9912-bed261f5ccfa
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=897938146 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_intr_rand_pgm.897938146
Directory /workspace/41.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/41.gpio_intr_with_filter_rand_intr_event.427996074
Short name T472
Test name
Test status
Simulation time 49617778 ps
CPU time 1.18 seconds
Started Jul 01 10:47:24 AM PDT 24
Finished Jul 01 10:47:25 AM PDT 24
Peak memory 197348 kb
Host smart-04e4da87-a1c9-426b-9f6d-48c731ef14cf
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=427996074 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 41.gpio_intr_with_filter_rand_intr_event.427996074
Directory /workspace/41.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/41.gpio_rand_intr_trigger.2739901949
Short name T160
Test name
Test status
Simulation time 98738058 ps
CPU time 2.9 seconds
Started Jul 01 10:47:31 AM PDT 24
Finished Jul 01 10:47:37 AM PDT 24
Peak memory 197664 kb
Host smart-6843ed92-7509-4cd9-9642-7227b033b83d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2739901949 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_rand_intr_trigger
.2739901949
Directory /workspace/41.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/41.gpio_random_dout_din.3654079591
Short name T688
Test name
Test status
Simulation time 116483551 ps
CPU time 0.64 seconds
Started Jul 01 10:47:43 AM PDT 24
Finished Jul 01 10:47:44 AM PDT 24
Peak memory 195504 kb
Host smart-dbd91b97-a75b-4e96-8647-0dc49f2a952d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3654079591 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_random_dout_din.3654079591
Directory /workspace/41.gpio_random_dout_din/latest

Test location /workspace/coverage/default/41.gpio_random_dout_din_no_pullup_pulldown.3740050271
Short name T376
Test name
Test status
Simulation time 329346091 ps
CPU time 1.15 seconds
Started Jul 01 10:47:23 AM PDT 24
Finished Jul 01 10:47:25 AM PDT 24
Peak memory 197500 kb
Host smart-47ed7088-904b-4aa1-a894-1b002150b65b
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3740050271 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_random_dout_din_no_pullu
p_pulldown.3740050271
Directory /workspace/41.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/41.gpio_random_long_reg_writes_reg_reads.1293786190
Short name T484
Test name
Test status
Simulation time 88165464 ps
CPU time 2.01 seconds
Started Jul 01 10:47:55 AM PDT 24
Finished Jul 01 10:47:58 AM PDT 24
Peak memory 198620 kb
Host smart-78e07502-f629-401d-8871-39d10b6d4eff
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1293786190 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_ra
ndom_long_reg_writes_reg_reads.1293786190
Directory /workspace/41.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/41.gpio_smoke.3143406180
Short name T579
Test name
Test status
Simulation time 84693810 ps
CPU time 1.06 seconds
Started Jul 01 10:47:36 AM PDT 24
Finished Jul 01 10:47:38 AM PDT 24
Peak memory 196488 kb
Host smart-a481f901-a712-442d-90ec-aa8f10b883a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3143406180 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_smoke.3143406180
Directory /workspace/41.gpio_smoke/latest

Test location /workspace/coverage/default/41.gpio_smoke_no_pullup_pulldown.1000074848
Short name T671
Test name
Test status
Simulation time 175257236 ps
CPU time 1.34 seconds
Started Jul 01 10:47:27 AM PDT 24
Finished Jul 01 10:47:30 AM PDT 24
Peak memory 196148 kb
Host smart-d109c2b5-2f08-449a-9cda-783180bb5f56
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1000074848 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_smoke_no_pullup_pulldown.1000074848
Directory /workspace/41.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/41.gpio_stress_all.473864790
Short name T329
Test name
Test status
Simulation time 3249582883 ps
CPU time 43.4 seconds
Started Jul 01 10:47:27 AM PDT 24
Finished Jul 01 10:48:13 AM PDT 24
Peak memory 198808 kb
Host smart-eacdb3f6-2b78-4a73-b5c7-20e1c0d7acd5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=473864790 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.g
pio_stress_all.473864790
Directory /workspace/41.gpio_stress_all/latest

Test location /workspace/coverage/default/42.gpio_alert_test.3103537021
Short name T18
Test name
Test status
Simulation time 40045371 ps
CPU time 0.53 seconds
Started Jul 01 10:47:28 AM PDT 24
Finished Jul 01 10:47:31 AM PDT 24
Peak memory 194456 kb
Host smart-05fc2c01-a438-49d6-b80f-7d0e7b77e020
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3103537021 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_alert_test.3103537021
Directory /workspace/42.gpio_alert_test/latest

Test location /workspace/coverage/default/42.gpio_dout_din_regs_random_rw.2768621810
Short name T194
Test name
Test status
Simulation time 23796529 ps
CPU time 0.77 seconds
Started Jul 01 10:47:29 AM PDT 24
Finished Jul 01 10:47:33 AM PDT 24
Peak memory 196108 kb
Host smart-0d348da9-760b-49f5-ab97-518b7816550a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2768621810 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_dout_din_regs_random_rw.2768621810
Directory /workspace/42.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/42.gpio_filter_stress.1831582562
Short name T391
Test name
Test status
Simulation time 489018641 ps
CPU time 15.95 seconds
Started Jul 01 10:47:32 AM PDT 24
Finished Jul 01 10:47:50 AM PDT 24
Peak memory 198664 kb
Host smart-70535a9d-5d41-46b1-a0d4-5a3241a74a51
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1831582562 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_filter_stre
ss.1831582562
Directory /workspace/42.gpio_filter_stress/latest

Test location /workspace/coverage/default/42.gpio_full_random.1767766721
Short name T313
Test name
Test status
Simulation time 525863005 ps
CPU time 0.97 seconds
Started Jul 01 10:47:30 AM PDT 24
Finished Jul 01 10:47:34 AM PDT 24
Peak memory 198664 kb
Host smart-5ff08374-5f08-49a8-86cd-6aa1bcb3525c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1767766721 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_full_random.1767766721
Directory /workspace/42.gpio_full_random/latest

Test location /workspace/coverage/default/42.gpio_intr_rand_pgm.3115861582
Short name T510
Test name
Test status
Simulation time 103020467 ps
CPU time 1.11 seconds
Started Jul 01 10:47:26 AM PDT 24
Finished Jul 01 10:47:29 AM PDT 24
Peak memory 196844 kb
Host smart-696e8523-5e6f-4a44-a2a7-39fe58eb7ff1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3115861582 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_intr_rand_pgm.3115861582
Directory /workspace/42.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/42.gpio_intr_with_filter_rand_intr_event.3975012720
Short name T438
Test name
Test status
Simulation time 36782322 ps
CPU time 1.47 seconds
Started Jul 01 10:47:22 AM PDT 24
Finished Jul 01 10:47:24 AM PDT 24
Peak memory 197592 kb
Host smart-9c12b4d1-cedb-478f-96a0-000dcbca479d
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3975012720 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 42.gpio_intr_with_filter_rand_intr_event.3975012720
Directory /workspace/42.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/42.gpio_rand_intr_trigger.247401469
Short name T151
Test name
Test status
Simulation time 1337946627 ps
CPU time 2.89 seconds
Started Jul 01 10:47:32 AM PDT 24
Finished Jul 01 10:47:38 AM PDT 24
Peak memory 197252 kb
Host smart-32791f96-8cd2-49eb-82dc-2462817ec26f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=247401469 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_rand_intr_trigger.
247401469
Directory /workspace/42.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/42.gpio_random_dout_din.1717972445
Short name T296
Test name
Test status
Simulation time 263929760 ps
CPU time 0.71 seconds
Started Jul 01 10:47:29 AM PDT 24
Finished Jul 01 10:47:33 AM PDT 24
Peak memory 196032 kb
Host smart-cd9abc12-ee66-4996-9c4b-c0c51bd0a2cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1717972445 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_random_dout_din.1717972445
Directory /workspace/42.gpio_random_dout_din/latest

Test location /workspace/coverage/default/42.gpio_random_dout_din_no_pullup_pulldown.1323326713
Short name T217
Test name
Test status
Simulation time 45628072 ps
CPU time 1.04 seconds
Started Jul 01 10:48:05 AM PDT 24
Finished Jul 01 10:48:06 AM PDT 24
Peak memory 196600 kb
Host smart-83f60e24-c018-414a-96ba-1f098408756c
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1323326713 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_random_dout_din_no_pullu
p_pulldown.1323326713
Directory /workspace/42.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/42.gpio_random_long_reg_writes_reg_reads.3021714894
Short name T611
Test name
Test status
Simulation time 256714608 ps
CPU time 5.67 seconds
Started Jul 01 10:47:42 AM PDT 24
Finished Jul 01 10:47:48 AM PDT 24
Peak memory 198464 kb
Host smart-3bb1716a-ed26-478b-9388-b5abe2f8d48a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3021714894 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_ra
ndom_long_reg_writes_reg_reads.3021714894
Directory /workspace/42.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/42.gpio_smoke.920774372
Short name T603
Test name
Test status
Simulation time 73145575 ps
CPU time 1.28 seconds
Started Jul 01 10:47:24 AM PDT 24
Finished Jul 01 10:47:26 AM PDT 24
Peak memory 197800 kb
Host smart-cf97cc01-ecd2-43d5-bdc5-55bd5a69a5fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=920774372 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_smoke.920774372
Directory /workspace/42.gpio_smoke/latest

Test location /workspace/coverage/default/42.gpio_smoke_no_pullup_pulldown.634727328
Short name T594
Test name
Test status
Simulation time 670980420 ps
CPU time 1.25 seconds
Started Jul 01 10:47:32 AM PDT 24
Finished Jul 01 10:47:36 AM PDT 24
Peak memory 196108 kb
Host smart-4c80212b-dacd-478c-a7d1-ae6e22c025ca
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=634727328 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_smoke_no_pullup_pulldown.634727328
Directory /workspace/42.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/42.gpio_stress_all.1423165053
Short name T481
Test name
Test status
Simulation time 2511541356 ps
CPU time 65.13 seconds
Started Jul 01 10:47:29 AM PDT 24
Finished Jul 01 10:48:38 AM PDT 24
Peak memory 198628 kb
Host smart-cac3bc41-aa4b-4afc-81f6-799cf72b866b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1423165053 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.
gpio_stress_all.1423165053
Directory /workspace/42.gpio_stress_all/latest

Test location /workspace/coverage/default/42.gpio_stress_all_with_rand_reset.2190579876
Short name T62
Test name
Test status
Simulation time 32849407717 ps
CPU time 241.28 seconds
Started Jul 01 10:47:28 AM PDT 24
Finished Jul 01 10:51:32 AM PDT 24
Peak memory 198712 kb
Host smart-7ae1473e-593d-4eca-bff9-b0da6632f5e1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2190579876 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_stress_all_with_rand_reset.2190579876
Directory /workspace/42.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.gpio_alert_test.3650378342
Short name T363
Test name
Test status
Simulation time 37131845 ps
CPU time 0.53 seconds
Started Jul 01 10:47:38 AM PDT 24
Finished Jul 01 10:47:39 AM PDT 24
Peak memory 193412 kb
Host smart-237b3c39-f133-4409-a9f2-d3b42f307294
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3650378342 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_alert_test.3650378342
Directory /workspace/43.gpio_alert_test/latest

Test location /workspace/coverage/default/43.gpio_dout_din_regs_random_rw.2807848209
Short name T275
Test name
Test status
Simulation time 35647026 ps
CPU time 0.72 seconds
Started Jul 01 10:47:31 AM PDT 24
Finished Jul 01 10:47:35 AM PDT 24
Peak memory 195828 kb
Host smart-fab1b736-7c40-4ade-b57e-c18136e4d572
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2807848209 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_dout_din_regs_random_rw.2807848209
Directory /workspace/43.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/43.gpio_filter_stress.3152109088
Short name T517
Test name
Test status
Simulation time 2349585100 ps
CPU time 11.23 seconds
Started Jul 01 10:47:27 AM PDT 24
Finished Jul 01 10:47:40 AM PDT 24
Peak memory 197496 kb
Host smart-72f432d6-41d7-492d-b60a-3de5eb68c31d
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3152109088 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_filter_stre
ss.3152109088
Directory /workspace/43.gpio_filter_stress/latest

Test location /workspace/coverage/default/43.gpio_full_random.1711701699
Short name T540
Test name
Test status
Simulation time 24063412 ps
CPU time 0.68 seconds
Started Jul 01 10:47:17 AM PDT 24
Finished Jul 01 10:47:18 AM PDT 24
Peak memory 195796 kb
Host smart-c3eb25fc-decc-4236-86e7-b0cdd41effbe
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1711701699 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_full_random.1711701699
Directory /workspace/43.gpio_full_random/latest

Test location /workspace/coverage/default/43.gpio_intr_rand_pgm.548636963
Short name T129
Test name
Test status
Simulation time 45987314 ps
CPU time 1.28 seconds
Started Jul 01 10:47:28 AM PDT 24
Finished Jul 01 10:47:32 AM PDT 24
Peak memory 197352 kb
Host smart-c3b8a63e-6993-4f9d-af12-77824f49b127
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=548636963 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_intr_rand_pgm.548636963
Directory /workspace/43.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/43.gpio_intr_with_filter_rand_intr_event.2329806013
Short name T595
Test name
Test status
Simulation time 62945028 ps
CPU time 1.28 seconds
Started Jul 01 10:47:32 AM PDT 24
Finished Jul 01 10:47:36 AM PDT 24
Peak memory 197048 kb
Host smart-7d063d9b-d126-446b-9e66-2e8f3f356eb4
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2329806013 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 43.gpio_intr_with_filter_rand_intr_event.2329806013
Directory /workspace/43.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/43.gpio_rand_intr_trigger.767370166
Short name T461
Test name
Test status
Simulation time 744198836 ps
CPU time 2.11 seconds
Started Jul 01 10:47:50 AM PDT 24
Finished Jul 01 10:47:53 AM PDT 24
Peak memory 197056 kb
Host smart-8c4c5f38-a552-4bcd-b380-bf1d19ebb7c5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=767370166 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_rand_intr_trigger.
767370166
Directory /workspace/43.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/43.gpio_random_dout_din.930823725
Short name T14
Test name
Test status
Simulation time 22016740 ps
CPU time 0.89 seconds
Started Jul 01 10:47:30 AM PDT 24
Finished Jul 01 10:47:34 AM PDT 24
Peak memory 197280 kb
Host smart-ee4831b7-4125-496d-893b-a39c7af8a2e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=930823725 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_random_dout_din.930823725
Directory /workspace/43.gpio_random_dout_din/latest

Test location /workspace/coverage/default/43.gpio_random_dout_din_no_pullup_pulldown.2782558066
Short name T696
Test name
Test status
Simulation time 628548846 ps
CPU time 1.24 seconds
Started Jul 01 10:47:37 AM PDT 24
Finished Jul 01 10:47:39 AM PDT 24
Peak memory 198704 kb
Host smart-8db709dc-37a7-43f4-b2b2-7ce40008eb06
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2782558066 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_random_dout_din_no_pullu
p_pulldown.2782558066
Directory /workspace/43.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/43.gpio_random_long_reg_writes_reg_reads.4058087249
Short name T232
Test name
Test status
Simulation time 1014072977 ps
CPU time 5.64 seconds
Started Jul 01 10:47:47 AM PDT 24
Finished Jul 01 10:47:53 AM PDT 24
Peak memory 198528 kb
Host smart-2d8e20e1-0115-447c-ae08-55f7ee2dc954
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4058087249 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_ra
ndom_long_reg_writes_reg_reads.4058087249
Directory /workspace/43.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/43.gpio_smoke.2591938195
Short name T328
Test name
Test status
Simulation time 265295461 ps
CPU time 1.19 seconds
Started Jul 01 10:47:26 AM PDT 24
Finished Jul 01 10:47:29 AM PDT 24
Peak memory 196872 kb
Host smart-580b621a-5e21-492d-8d98-b9cbe6bea546
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2591938195 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_smoke.2591938195
Directory /workspace/43.gpio_smoke/latest

Test location /workspace/coverage/default/43.gpio_smoke_no_pullup_pulldown.106059435
Short name T192
Test name
Test status
Simulation time 39415428 ps
CPU time 1.13 seconds
Started Jul 01 10:47:30 AM PDT 24
Finished Jul 01 10:47:35 AM PDT 24
Peak memory 197340 kb
Host smart-cdce39dd-4c1e-4889-8d88-f2592b162e6b
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=106059435 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_smoke_no_pullup_pulldown.106059435
Directory /workspace/43.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/43.gpio_stress_all.2626043772
Short name T143
Test name
Test status
Simulation time 11703283490 ps
CPU time 143.21 seconds
Started Jul 01 10:47:28 AM PDT 24
Finished Jul 01 10:49:59 AM PDT 24
Peak memory 198608 kb
Host smart-5806f292-750d-4830-90a3-bab33821c6cb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2626043772 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.
gpio_stress_all.2626043772
Directory /workspace/43.gpio_stress_all/latest

Test location /workspace/coverage/default/44.gpio_alert_test.1237128670
Short name T347
Test name
Test status
Simulation time 37363694 ps
CPU time 0.58 seconds
Started Jul 01 10:47:32 AM PDT 24
Finished Jul 01 10:47:35 AM PDT 24
Peak memory 194636 kb
Host smart-8120d072-cd98-474f-a6c5-54e5ceb7479b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1237128670 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_alert_test.1237128670
Directory /workspace/44.gpio_alert_test/latest

Test location /workspace/coverage/default/44.gpio_dout_din_regs_random_rw.3679305143
Short name T598
Test name
Test status
Simulation time 120538961 ps
CPU time 0.67 seconds
Started Jul 01 10:47:27 AM PDT 24
Finished Jul 01 10:47:31 AM PDT 24
Peak memory 196372 kb
Host smart-c7ac49a7-b625-4347-9719-206b93fc6db0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3679305143 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_dout_din_regs_random_rw.3679305143
Directory /workspace/44.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/44.gpio_filter_stress.240990829
Short name T216
Test name
Test status
Simulation time 268076638 ps
CPU time 4.18 seconds
Started Jul 01 10:47:38 AM PDT 24
Finished Jul 01 10:47:43 AM PDT 24
Peak memory 196060 kb
Host smart-9799b10f-bda8-426f-b6a2-314bfb4aecc2
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=240990829 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_filter_stres
s.240990829
Directory /workspace/44.gpio_filter_stress/latest

Test location /workspace/coverage/default/44.gpio_full_random.1054613760
Short name T420
Test name
Test status
Simulation time 625637097 ps
CPU time 0.99 seconds
Started Jul 01 10:47:32 AM PDT 24
Finished Jul 01 10:47:35 AM PDT 24
Peak memory 197284 kb
Host smart-87198736-60b7-48b6-9b7d-2e104ef4cdb4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1054613760 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_full_random.1054613760
Directory /workspace/44.gpio_full_random/latest

Test location /workspace/coverage/default/44.gpio_intr_rand_pgm.1432172370
Short name T403
Test name
Test status
Simulation time 43706495 ps
CPU time 1.07 seconds
Started Jul 01 10:47:31 AM PDT 24
Finished Jul 01 10:47:35 AM PDT 24
Peak memory 197288 kb
Host smart-a9d919a3-eea7-42dd-95b6-9ee62f5e8546
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1432172370 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_intr_rand_pgm.1432172370
Directory /workspace/44.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/44.gpio_intr_with_filter_rand_intr_event.2361510575
Short name T502
Test name
Test status
Simulation time 159052647 ps
CPU time 3.24 seconds
Started Jul 01 10:47:37 AM PDT 24
Finished Jul 01 10:47:46 AM PDT 24
Peak memory 198488 kb
Host smart-4bf9b3d0-2174-4523-8ff7-db9f0db66498
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2361510575 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 44.gpio_intr_with_filter_rand_intr_event.2361510575
Directory /workspace/44.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/44.gpio_rand_intr_trigger.257080754
Short name T506
Test name
Test status
Simulation time 119258813 ps
CPU time 2.1 seconds
Started Jul 01 10:47:35 AM PDT 24
Finished Jul 01 10:47:38 AM PDT 24
Peak memory 197720 kb
Host smart-0cecdcc9-dbac-4fbb-a248-9710256cf8af
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=257080754 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_rand_intr_trigger.
257080754
Directory /workspace/44.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/44.gpio_random_dout_din.1064261642
Short name T479
Test name
Test status
Simulation time 391594821 ps
CPU time 0.99 seconds
Started Jul 01 10:47:25 AM PDT 24
Finished Jul 01 10:47:27 AM PDT 24
Peak memory 197172 kb
Host smart-59ce029d-d5de-48c4-9ddb-e6dcf2b796f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1064261642 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_random_dout_din.1064261642
Directory /workspace/44.gpio_random_dout_din/latest

Test location /workspace/coverage/default/44.gpio_random_dout_din_no_pullup_pulldown.3772285585
Short name T586
Test name
Test status
Simulation time 51797462 ps
CPU time 1.22 seconds
Started Jul 01 10:47:31 AM PDT 24
Finished Jul 01 10:47:35 AM PDT 24
Peak memory 197688 kb
Host smart-e7ab00e1-4527-4dd6-9602-18a4ce9cafe3
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3772285585 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_random_dout_din_no_pullu
p_pulldown.3772285585
Directory /workspace/44.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/44.gpio_random_long_reg_writes_reg_reads.288372564
Short name T186
Test name
Test status
Simulation time 118277630 ps
CPU time 5.1 seconds
Started Jul 01 10:47:54 AM PDT 24
Finished Jul 01 10:48:00 AM PDT 24
Peak memory 198640 kb
Host smart-a7ecb7b1-51cf-4f44-8755-5b3ae6c6b820
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=288372564 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_ran
dom_long_reg_writes_reg_reads.288372564
Directory /workspace/44.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/44.gpio_smoke.4087753314
Short name T278
Test name
Test status
Simulation time 45740999 ps
CPU time 0.8 seconds
Started Jul 01 10:48:20 AM PDT 24
Finished Jul 01 10:48:22 AM PDT 24
Peak memory 195716 kb
Host smart-bdb4e407-eb2e-4c0d-84b0-eec7872fc675
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4087753314 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_smoke.4087753314
Directory /workspace/44.gpio_smoke/latest

Test location /workspace/coverage/default/44.gpio_smoke_no_pullup_pulldown.3399913719
Short name T413
Test name
Test status
Simulation time 85000058 ps
CPU time 1.27 seconds
Started Jul 01 10:47:54 AM PDT 24
Finished Jul 01 10:47:56 AM PDT 24
Peak memory 197320 kb
Host smart-92eede54-5c3a-46df-9ec3-c83190b646fb
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3399913719 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_smoke_no_pullup_pulldown.3399913719
Directory /workspace/44.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/44.gpio_stress_all.534540485
Short name T202
Test name
Test status
Simulation time 6556518050 ps
CPU time 79.68 seconds
Started Jul 01 10:47:49 AM PDT 24
Finished Jul 01 10:49:09 AM PDT 24
Peak memory 198788 kb
Host smart-7dcbda95-fbd7-4de1-8b3b-a5292e3619f7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=534540485 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.g
pio_stress_all.534540485
Directory /workspace/44.gpio_stress_all/latest

Test location /workspace/coverage/default/45.gpio_alert_test.2416439764
Short name T367
Test name
Test status
Simulation time 68750426 ps
CPU time 0.57 seconds
Started Jul 01 10:47:24 AM PDT 24
Finished Jul 01 10:47:25 AM PDT 24
Peak memory 195216 kb
Host smart-f112e15b-15f9-4be2-b4b2-1a43c411cd08
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2416439764 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_alert_test.2416439764
Directory /workspace/45.gpio_alert_test/latest

Test location /workspace/coverage/default/45.gpio_dout_din_regs_random_rw.3313981335
Short name T139
Test name
Test status
Simulation time 26061843 ps
CPU time 0.76 seconds
Started Jul 01 10:47:28 AM PDT 24
Finished Jul 01 10:47:31 AM PDT 24
Peak memory 195888 kb
Host smart-86769a51-de3b-45fd-9ec7-3ddc3170be8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3313981335 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_dout_din_regs_random_rw.3313981335
Directory /workspace/45.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/45.gpio_filter_stress.2713487405
Short name T682
Test name
Test status
Simulation time 3193601611 ps
CPU time 24.03 seconds
Started Jul 01 10:47:29 AM PDT 24
Finished Jul 01 10:47:56 AM PDT 24
Peak memory 197168 kb
Host smart-e342d284-25f3-424f-a271-3eba02440665
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2713487405 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_filter_stre
ss.2713487405
Directory /workspace/45.gpio_filter_stress/latest

Test location /workspace/coverage/default/45.gpio_full_random.3836122441
Short name T21
Test name
Test status
Simulation time 321704076 ps
CPU time 0.76 seconds
Started Jul 01 10:48:00 AM PDT 24
Finished Jul 01 10:48:02 AM PDT 24
Peak memory 197224 kb
Host smart-54a3fe97-cd04-4fb3-a470-137cc654cd36
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3836122441 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_full_random.3836122441
Directory /workspace/45.gpio_full_random/latest

Test location /workspace/coverage/default/45.gpio_intr_rand_pgm.1168785626
Short name T148
Test name
Test status
Simulation time 117287668 ps
CPU time 0.98 seconds
Started Jul 01 10:47:45 AM PDT 24
Finished Jul 01 10:47:47 AM PDT 24
Peak memory 196348 kb
Host smart-35d5b4fc-fc4a-4c08-b6c0-4fd6dfde31e0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1168785626 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_intr_rand_pgm.1168785626
Directory /workspace/45.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/45.gpio_intr_with_filter_rand_intr_event.2394228176
Short name T636
Test name
Test status
Simulation time 44343971 ps
CPU time 1.05 seconds
Started Jul 01 10:47:38 AM PDT 24
Finished Jul 01 10:47:40 AM PDT 24
Peak memory 197852 kb
Host smart-45a54686-7656-407c-902b-dd1c6f97ed99
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2394228176 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 45.gpio_intr_with_filter_rand_intr_event.2394228176
Directory /workspace/45.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/45.gpio_rand_intr_trigger.3248582627
Short name T381
Test name
Test status
Simulation time 142217729 ps
CPU time 2.08 seconds
Started Jul 01 10:47:45 AM PDT 24
Finished Jul 01 10:47:47 AM PDT 24
Peak memory 197628 kb
Host smart-3bc4be04-6589-433b-9e4f-0c67b2d96d0c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3248582627 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_rand_intr_trigger
.3248582627
Directory /workspace/45.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/45.gpio_random_dout_din.990513738
Short name T425
Test name
Test status
Simulation time 36478248 ps
CPU time 0.97 seconds
Started Jul 01 10:47:30 AM PDT 24
Finished Jul 01 10:47:34 AM PDT 24
Peak memory 197340 kb
Host smart-c0c7d30c-58bb-46db-996e-1ebd72d2465d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=990513738 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_random_dout_din.990513738
Directory /workspace/45.gpio_random_dout_din/latest

Test location /workspace/coverage/default/45.gpio_random_dout_din_no_pullup_pulldown.800658697
Short name T591
Test name
Test status
Simulation time 49107624 ps
CPU time 0.71 seconds
Started Jul 01 10:47:45 AM PDT 24
Finished Jul 01 10:47:46 AM PDT 24
Peak memory 195872 kb
Host smart-9c0b2efd-8cc0-41b3-89fe-bfe99ff82e2f
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=800658697 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_random_dout_din_no_pullup
_pulldown.800658697
Directory /workspace/45.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/45.gpio_random_long_reg_writes_reg_reads.52770929
Short name T709
Test name
Test status
Simulation time 521536947 ps
CPU time 5.68 seconds
Started Jul 01 10:47:50 AM PDT 24
Finished Jul 01 10:47:56 AM PDT 24
Peak memory 198516 kb
Host smart-3b36e91f-bbf4-4a74-b76e-ba3b3350de94
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52770929 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_w
rites_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_rand
om_long_reg_writes_reg_reads.52770929
Directory /workspace/45.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/45.gpio_smoke.1071943544
Short name T659
Test name
Test status
Simulation time 31335231 ps
CPU time 0.95 seconds
Started Jul 01 10:47:29 AM PDT 24
Finished Jul 01 10:47:33 AM PDT 24
Peak memory 196048 kb
Host smart-7e823c8b-5f86-4c4b-b479-89e45e3a1c88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1071943544 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_smoke.1071943544
Directory /workspace/45.gpio_smoke/latest

Test location /workspace/coverage/default/45.gpio_smoke_no_pullup_pulldown.3187366587
Short name T557
Test name
Test status
Simulation time 46992537 ps
CPU time 1.3 seconds
Started Jul 01 10:47:50 AM PDT 24
Finished Jul 01 10:47:52 AM PDT 24
Peak memory 197352 kb
Host smart-9a06f49d-be26-4c5d-a046-8591cebd197e
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3187366587 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_smoke_no_pullup_pulldown.3187366587
Directory /workspace/45.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/45.gpio_stress_all.2400726454
Short name T639
Test name
Test status
Simulation time 90864548095 ps
CPU time 148.06 seconds
Started Jul 01 10:47:38 AM PDT 24
Finished Jul 01 10:50:07 AM PDT 24
Peak memory 198664 kb
Host smart-28080715-1ea4-4e98-93ce-9007aa41c851
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2400726454 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.
gpio_stress_all.2400726454
Directory /workspace/45.gpio_stress_all/latest

Test location /workspace/coverage/default/46.gpio_alert_test.2016644780
Short name T315
Test name
Test status
Simulation time 23484788 ps
CPU time 0.58 seconds
Started Jul 01 10:47:30 AM PDT 24
Finished Jul 01 10:47:34 AM PDT 24
Peak memory 194844 kb
Host smart-c932379d-7b42-4869-834d-fae9498f5a3c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2016644780 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_alert_test.2016644780
Directory /workspace/46.gpio_alert_test/latest

Test location /workspace/coverage/default/46.gpio_dout_din_regs_random_rw.574077038
Short name T478
Test name
Test status
Simulation time 42426133 ps
CPU time 0.91 seconds
Started Jul 01 10:47:53 AM PDT 24
Finished Jul 01 10:47:55 AM PDT 24
Peak memory 197268 kb
Host smart-0f390f74-92ac-4436-b518-46e2a36fd082
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=574077038 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_dout_din_regs_random_rw.574077038
Directory /workspace/46.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/46.gpio_filter_stress.1281535362
Short name T156
Test name
Test status
Simulation time 1284825640 ps
CPU time 17.46 seconds
Started Jul 01 10:47:54 AM PDT 24
Finished Jul 01 10:48:13 AM PDT 24
Peak memory 197476 kb
Host smart-bf5f8ff1-527e-46b6-8294-b4fbc229aecc
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1281535362 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_filter_stre
ss.1281535362
Directory /workspace/46.gpio_filter_stress/latest

Test location /workspace/coverage/default/46.gpio_full_random.4141388329
Short name T22
Test name
Test status
Simulation time 48848484 ps
CPU time 0.74 seconds
Started Jul 01 10:47:40 AM PDT 24
Finished Jul 01 10:47:41 AM PDT 24
Peak memory 195392 kb
Host smart-5fb3cd29-84d3-495c-a3dd-3c5cf359b4be
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4141388329 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_full_random.4141388329
Directory /workspace/46.gpio_full_random/latest

Test location /workspace/coverage/default/46.gpio_intr_rand_pgm.157394806
Short name T675
Test name
Test status
Simulation time 67724596 ps
CPU time 0.83 seconds
Started Jul 01 10:47:29 AM PDT 24
Finished Jul 01 10:47:33 AM PDT 24
Peak memory 196828 kb
Host smart-0d8e7b4d-1e00-46ce-a3b2-610be8bc5e92
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=157394806 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_intr_rand_pgm.157394806
Directory /workspace/46.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/46.gpio_intr_with_filter_rand_intr_event.516992301
Short name T336
Test name
Test status
Simulation time 169517670 ps
CPU time 3.45 seconds
Started Jul 01 10:47:57 AM PDT 24
Finished Jul 01 10:48:02 AM PDT 24
Peak memory 198632 kb
Host smart-958ef49f-3643-42a0-952f-f9340b4eb5d7
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=516992301 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 46.gpio_intr_with_filter_rand_intr_event.516992301
Directory /workspace/46.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/46.gpio_rand_intr_trigger.877415572
Short name T452
Test name
Test status
Simulation time 311847761 ps
CPU time 2.41 seconds
Started Jul 01 10:47:56 AM PDT 24
Finished Jul 01 10:48:00 AM PDT 24
Peak memory 197540 kb
Host smart-d0664026-f259-410b-999d-33f0a88d04e7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=877415572 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_rand_intr_trigger.
877415572
Directory /workspace/46.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/46.gpio_random_dout_din.2472152168
Short name T415
Test name
Test status
Simulation time 31458855 ps
CPU time 1.03 seconds
Started Jul 01 10:47:56 AM PDT 24
Finished Jul 01 10:47:58 AM PDT 24
Peak memory 196496 kb
Host smart-6770787f-bed0-47d7-a485-b406ca7488cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2472152168 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_random_dout_din.2472152168
Directory /workspace/46.gpio_random_dout_din/latest

Test location /workspace/coverage/default/46.gpio_random_dout_din_no_pullup_pulldown.1452063622
Short name T327
Test name
Test status
Simulation time 24082545 ps
CPU time 0.91 seconds
Started Jul 01 10:47:38 AM PDT 24
Finished Jul 01 10:47:40 AM PDT 24
Peak memory 196616 kb
Host smart-7e3eb8d8-c579-4532-869c-aa502e599853
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1452063622 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_random_dout_din_no_pullu
p_pulldown.1452063622
Directory /workspace/46.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/46.gpio_random_long_reg_writes_reg_reads.3732362606
Short name T615
Test name
Test status
Simulation time 294768449 ps
CPU time 3.36 seconds
Started Jul 01 10:47:52 AM PDT 24
Finished Jul 01 10:48:00 AM PDT 24
Peak memory 198472 kb
Host smart-ad6990d1-ff0f-4f76-b7bc-0c0b47bd2ec4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3732362606 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_ra
ndom_long_reg_writes_reg_reads.3732362606
Directory /workspace/46.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/46.gpio_smoke.3284086143
Short name T211
Test name
Test status
Simulation time 79516152 ps
CPU time 1.03 seconds
Started Jul 01 10:47:33 AM PDT 24
Finished Jul 01 10:47:36 AM PDT 24
Peak memory 197144 kb
Host smart-66353239-3e26-41b1-a1aa-9ec4b258da55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3284086143 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_smoke.3284086143
Directory /workspace/46.gpio_smoke/latest

Test location /workspace/coverage/default/46.gpio_smoke_no_pullup_pulldown.333352092
Short name T535
Test name
Test status
Simulation time 36535920 ps
CPU time 0.8 seconds
Started Jul 01 10:47:25 AM PDT 24
Finished Jul 01 10:47:27 AM PDT 24
Peak memory 196552 kb
Host smart-9be4f83b-f629-4ed1-a458-589da3464db3
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=333352092 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_smoke_no_pullup_pulldown.333352092
Directory /workspace/46.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/46.gpio_stress_all.764864044
Short name T691
Test name
Test status
Simulation time 18929968249 ps
CPU time 131.71 seconds
Started Jul 01 10:47:35 AM PDT 24
Finished Jul 01 10:49:48 AM PDT 24
Peak memory 198772 kb
Host smart-9746260a-09b1-4c58-ac7f-fca8d1186f58
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=764864044 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.g
pio_stress_all.764864044
Directory /workspace/46.gpio_stress_all/latest

Test location /workspace/coverage/default/47.gpio_alert_test.3022412391
Short name T144
Test name
Test status
Simulation time 22016662 ps
CPU time 0.6 seconds
Started Jul 01 10:47:51 AM PDT 24
Finished Jul 01 10:47:53 AM PDT 24
Peak memory 195384 kb
Host smart-59eb710c-a15e-4904-be35-b311cd6f9c04
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3022412391 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_alert_test.3022412391
Directory /workspace/47.gpio_alert_test/latest

Test location /workspace/coverage/default/47.gpio_dout_din_regs_random_rw.3925335572
Short name T113
Test name
Test status
Simulation time 39835669 ps
CPU time 0.73 seconds
Started Jul 01 10:47:29 AM PDT 24
Finished Jul 01 10:47:34 AM PDT 24
Peak memory 195800 kb
Host smart-6ef5f8be-e5d9-42ce-b856-abce8731595b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3925335572 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_dout_din_regs_random_rw.3925335572
Directory /workspace/47.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/47.gpio_filter_stress.2143295673
Short name T165
Test name
Test status
Simulation time 289808269 ps
CPU time 14.54 seconds
Started Jul 01 10:48:08 AM PDT 24
Finished Jul 01 10:48:23 AM PDT 24
Peak memory 196216 kb
Host smart-2eda1b06-53a2-460c-8346-bd3cc8ca8f86
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2143295673 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_filter_stre
ss.2143295673
Directory /workspace/47.gpio_filter_stress/latest

Test location /workspace/coverage/default/47.gpio_full_random.1501442774
Short name T171
Test name
Test status
Simulation time 62125950 ps
CPU time 0.75 seconds
Started Jul 01 10:47:33 AM PDT 24
Finished Jul 01 10:47:36 AM PDT 24
Peak memory 196068 kb
Host smart-460db02e-3dba-4e14-95b3-44c38a4f18da
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1501442774 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_full_random.1501442774
Directory /workspace/47.gpio_full_random/latest

Test location /workspace/coverage/default/47.gpio_intr_rand_pgm.2493351173
Short name T711
Test name
Test status
Simulation time 29387681 ps
CPU time 0.88 seconds
Started Jul 01 10:47:44 AM PDT 24
Finished Jul 01 10:47:46 AM PDT 24
Peak memory 197180 kb
Host smart-44c80305-7f35-4faa-b920-e883d5a3cfd6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2493351173 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_intr_rand_pgm.2493351173
Directory /workspace/47.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/47.gpio_intr_with_filter_rand_intr_event.929910009
Short name T159
Test name
Test status
Simulation time 185171282 ps
CPU time 3.41 seconds
Started Jul 01 10:47:32 AM PDT 24
Finished Jul 01 10:47:38 AM PDT 24
Peak memory 198572 kb
Host smart-9499b42b-4e33-4e1c-908e-9f76c3a94a95
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=929910009 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 47.gpio_intr_with_filter_rand_intr_event.929910009
Directory /workspace/47.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/47.gpio_rand_intr_trigger.67703339
Short name T104
Test name
Test status
Simulation time 209626370 ps
CPU time 1.78 seconds
Started Jul 01 10:47:26 AM PDT 24
Finished Jul 01 10:47:29 AM PDT 24
Peak memory 196708 kb
Host smart-98c39880-b983-42c3-9f4e-60ac8725afac
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67703339 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigger
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_rand_intr_trigger.67703339
Directory /workspace/47.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/47.gpio_random_dout_din.3712827085
Short name T593
Test name
Test status
Simulation time 223821790 ps
CPU time 1.33 seconds
Started Jul 01 10:47:37 AM PDT 24
Finished Jul 01 10:47:39 AM PDT 24
Peak memory 197708 kb
Host smart-0cd93645-7217-4e11-9d25-2a51eacf86c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3712827085 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_random_dout_din.3712827085
Directory /workspace/47.gpio_random_dout_din/latest

Test location /workspace/coverage/default/47.gpio_random_dout_din_no_pullup_pulldown.2701963271
Short name T24
Test name
Test status
Simulation time 38505128 ps
CPU time 0.89 seconds
Started Jul 01 10:47:56 AM PDT 24
Finished Jul 01 10:47:59 AM PDT 24
Peak memory 196372 kb
Host smart-1c0401a7-391c-4279-8c5c-bfd1e3697be9
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2701963271 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_random_dout_din_no_pullu
p_pulldown.2701963271
Directory /workspace/47.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/47.gpio_random_long_reg_writes_reg_reads.2844406365
Short name T126
Test name
Test status
Simulation time 143145391 ps
CPU time 3.33 seconds
Started Jul 01 10:47:40 AM PDT 24
Finished Jul 01 10:47:43 AM PDT 24
Peak memory 198680 kb
Host smart-ef9c91a5-1154-4324-938b-16f1c61820b2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2844406365 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_ra
ndom_long_reg_writes_reg_reads.2844406365
Directory /workspace/47.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/47.gpio_smoke.1189076238
Short name T663
Test name
Test status
Simulation time 46942001 ps
CPU time 1.05 seconds
Started Jul 01 10:47:31 AM PDT 24
Finished Jul 01 10:47:35 AM PDT 24
Peak memory 197132 kb
Host smart-357f45c8-97c9-4393-8f0c-4d326b0ea9c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1189076238 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_smoke.1189076238
Directory /workspace/47.gpio_smoke/latest

Test location /workspace/coverage/default/47.gpio_smoke_no_pullup_pulldown.3779238109
Short name T583
Test name
Test status
Simulation time 226056343 ps
CPU time 1.21 seconds
Started Jul 01 10:47:38 AM PDT 24
Finished Jul 01 10:47:40 AM PDT 24
Peak memory 197232 kb
Host smart-de2eb0ad-5339-4997-a536-4a09cd0a49d2
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3779238109 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_smoke_no_pullup_pulldown.3779238109
Directory /workspace/47.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/47.gpio_stress_all.3507101467
Short name T549
Test name
Test status
Simulation time 8842471412 ps
CPU time 112.94 seconds
Started Jul 01 10:48:05 AM PDT 24
Finished Jul 01 10:49:58 AM PDT 24
Peak memory 198640 kb
Host smart-30043d1d-d9e9-404e-ba6d-45e7bf1a66ea
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3507101467 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.
gpio_stress_all.3507101467
Directory /workspace/47.gpio_stress_all/latest

Test location /workspace/coverage/default/47.gpio_stress_all_with_rand_reset.3030583221
Short name T30
Test name
Test status
Simulation time 67086587423 ps
CPU time 1463.47 seconds
Started Jul 01 10:47:32 AM PDT 24
Finished Jul 01 11:11:58 AM PDT 24
Peak memory 198904 kb
Host smart-e70315f5-bd62-42f7-a1aa-cb4431d68fa2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3030583221 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_stress_all_with_rand_reset.3030583221
Directory /workspace/47.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.gpio_alert_test.2729051503
Short name T651
Test name
Test status
Simulation time 25101740 ps
CPU time 0.59 seconds
Started Jul 01 10:47:27 AM PDT 24
Finished Jul 01 10:47:30 AM PDT 24
Peak memory 195384 kb
Host smart-19f981ae-7bea-4852-9040-1e4a53e88f13
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2729051503 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_alert_test.2729051503
Directory /workspace/48.gpio_alert_test/latest

Test location /workspace/coverage/default/48.gpio_dout_din_regs_random_rw.552515255
Short name T418
Test name
Test status
Simulation time 29625714 ps
CPU time 0.93 seconds
Started Jul 01 10:48:05 AM PDT 24
Finished Jul 01 10:48:08 AM PDT 24
Peak memory 196700 kb
Host smart-c352d1ca-edba-46d0-8cc7-a93714ade6c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=552515255 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_dout_din_regs_random_rw.552515255
Directory /workspace/48.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/48.gpio_filter_stress.550368009
Short name T320
Test name
Test status
Simulation time 2417312478 ps
CPU time 18.32 seconds
Started Jul 01 10:47:53 AM PDT 24
Finished Jul 01 10:48:13 AM PDT 24
Peak memory 198736 kb
Host smart-4b911847-b639-4871-8724-a5fc76616183
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=550368009 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_filter_stres
s.550368009
Directory /workspace/48.gpio_filter_stress/latest

Test location /workspace/coverage/default/48.gpio_full_random.4292094520
Short name T28
Test name
Test status
Simulation time 73964213 ps
CPU time 0.96 seconds
Started Jul 01 10:47:44 AM PDT 24
Finished Jul 01 10:47:46 AM PDT 24
Peak memory 197240 kb
Host smart-7589da27-0438-41ee-bd80-cbda75722246
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4292094520 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_full_random.4292094520
Directory /workspace/48.gpio_full_random/latest

Test location /workspace/coverage/default/48.gpio_intr_rand_pgm.3590689768
Short name T308
Test name
Test status
Simulation time 57303872 ps
CPU time 0.89 seconds
Started Jul 01 10:47:31 AM PDT 24
Finished Jul 01 10:47:35 AM PDT 24
Peak memory 196240 kb
Host smart-954a6c1c-d0ef-426f-bdea-16ed0acad22e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3590689768 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_intr_rand_pgm.3590689768
Directory /workspace/48.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/48.gpio_intr_with_filter_rand_intr_event.2906853186
Short name T276
Test name
Test status
Simulation time 34949534 ps
CPU time 1.37 seconds
Started Jul 01 10:47:26 AM PDT 24
Finished Jul 01 10:47:29 AM PDT 24
Peak memory 196912 kb
Host smart-a40c116f-7522-42c7-8d89-cd5395aa504c
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2906853186 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 48.gpio_intr_with_filter_rand_intr_event.2906853186
Directory /workspace/48.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/48.gpio_rand_intr_trigger.1908074982
Short name T230
Test name
Test status
Simulation time 37495649 ps
CPU time 1.29 seconds
Started Jul 01 10:47:49 AM PDT 24
Finished Jul 01 10:47:51 AM PDT 24
Peak memory 196776 kb
Host smart-fbc566de-9d5b-42a0-8258-17c6f3ddca4a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1908074982 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_rand_intr_trigger
.1908074982
Directory /workspace/48.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/48.gpio_random_dout_din.3850783297
Short name T241
Test name
Test status
Simulation time 32429999 ps
CPU time 0.8 seconds
Started Jul 01 10:47:28 AM PDT 24
Finished Jul 01 10:47:32 AM PDT 24
Peak memory 195976 kb
Host smart-a3e1b649-14bb-4bad-9747-d324a9dcd6c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3850783297 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_random_dout_din.3850783297
Directory /workspace/48.gpio_random_dout_din/latest

Test location /workspace/coverage/default/48.gpio_random_dout_din_no_pullup_pulldown.3169346836
Short name T562
Test name
Test status
Simulation time 29116531 ps
CPU time 0.7 seconds
Started Jul 01 10:47:30 AM PDT 24
Finished Jul 01 10:47:34 AM PDT 24
Peak memory 195684 kb
Host smart-94061465-d4cf-4803-9019-7060be8a53df
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3169346836 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_random_dout_din_no_pullu
p_pulldown.3169346836
Directory /workspace/48.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/48.gpio_random_long_reg_writes_reg_reads.3968728237
Short name T374
Test name
Test status
Simulation time 368575369 ps
CPU time 2.33 seconds
Started Jul 01 10:47:58 AM PDT 24
Finished Jul 01 10:48:02 AM PDT 24
Peak memory 198668 kb
Host smart-641fd37a-468c-43a7-a1cd-e7f95901c712
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3968728237 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_ra
ndom_long_reg_writes_reg_reads.3968728237
Directory /workspace/48.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/48.gpio_smoke.4023137972
Short name T103
Test name
Test status
Simulation time 193979334 ps
CPU time 1.22 seconds
Started Jul 01 10:47:25 AM PDT 24
Finished Jul 01 10:47:28 AM PDT 24
Peak memory 197076 kb
Host smart-5241a05c-e81e-485e-9d16-42662f592a19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4023137972 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_smoke.4023137972
Directory /workspace/48.gpio_smoke/latest

Test location /workspace/coverage/default/48.gpio_smoke_no_pullup_pulldown.972911966
Short name T459
Test name
Test status
Simulation time 27104741 ps
CPU time 0.91 seconds
Started Jul 01 10:47:28 AM PDT 24
Finished Jul 01 10:47:32 AM PDT 24
Peak memory 196400 kb
Host smart-30621166-2b9a-4022-b231-92d3b7e1e607
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=972911966 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_smoke_no_pullup_pulldown.972911966
Directory /workspace/48.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/48.gpio_stress_all.3029389355
Short name T3
Test name
Test status
Simulation time 5452584442 ps
CPU time 56.23 seconds
Started Jul 01 10:47:36 AM PDT 24
Finished Jul 01 10:48:33 AM PDT 24
Peak memory 198768 kb
Host smart-6ee0e551-c93c-4300-bc3d-9df33af27fe7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3029389355 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.
gpio_stress_all.3029389355
Directory /workspace/48.gpio_stress_all/latest

Test location /workspace/coverage/default/48.gpio_stress_all_with_rand_reset.3405922466
Short name T64
Test name
Test status
Simulation time 157620117210 ps
CPU time 1867.2 seconds
Started Jul 01 10:47:28 AM PDT 24
Finished Jul 01 11:18:39 AM PDT 24
Peak memory 198852 kb
Host smart-9e10bc39-22cd-4960-81c9-35034dca42df
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3405922466 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_stress_all_with_rand_reset.3405922466
Directory /workspace/48.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.gpio_alert_test.6508446
Short name T493
Test name
Test status
Simulation time 38561633 ps
CPU time 0.55 seconds
Started Jul 01 10:47:32 AM PDT 24
Finished Jul 01 10:47:35 AM PDT 24
Peak memory 195212 kb
Host smart-9721f6eb-e67c-496d-a16b-49c809fd4f69
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=6508446 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_alert_test.6508446
Directory /workspace/49.gpio_alert_test/latest

Test location /workspace/coverage/default/49.gpio_dout_din_regs_random_rw.40744556
Short name T587
Test name
Test status
Simulation time 119878645 ps
CPU time 0.74 seconds
Started Jul 01 10:47:50 AM PDT 24
Finished Jul 01 10:47:52 AM PDT 24
Peak memory 195796 kb
Host smart-a5a9f817-73b7-459f-98e1-5f6d9690c399
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=40744556 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_dout_din_regs_random_rw.40744556
Directory /workspace/49.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/49.gpio_filter_stress.3201555316
Short name T468
Test name
Test status
Simulation time 1526633793 ps
CPU time 26.98 seconds
Started Jul 01 10:47:41 AM PDT 24
Finished Jul 01 10:48:08 AM PDT 24
Peak memory 198668 kb
Host smart-d0d061c3-f8bf-4c43-b97b-31eed66d4e6e
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3201555316 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_filter_stre
ss.3201555316
Directory /workspace/49.gpio_filter_stress/latest

Test location /workspace/coverage/default/49.gpio_full_random.1973447037
Short name T613
Test name
Test status
Simulation time 60720458 ps
CPU time 0.91 seconds
Started Jul 01 10:48:06 AM PDT 24
Finished Jul 01 10:48:08 AM PDT 24
Peak memory 196756 kb
Host smart-72c48600-b76e-4633-9be8-291e40da4c0b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1973447037 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_full_random.1973447037
Directory /workspace/49.gpio_full_random/latest

Test location /workspace/coverage/default/49.gpio_intr_rand_pgm.3198107593
Short name T214
Test name
Test status
Simulation time 576232995 ps
CPU time 1.22 seconds
Started Jul 01 10:47:35 AM PDT 24
Finished Jul 01 10:47:37 AM PDT 24
Peak memory 196480 kb
Host smart-1efd71a5-67d9-47c1-82a3-acfa3ef29e3e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3198107593 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_intr_rand_pgm.3198107593
Directory /workspace/49.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/49.gpio_intr_with_filter_rand_intr_event.558633385
Short name T378
Test name
Test status
Simulation time 54710878 ps
CPU time 2.27 seconds
Started Jul 01 10:47:28 AM PDT 24
Finished Jul 01 10:47:34 AM PDT 24
Peak memory 198540 kb
Host smart-20204531-0444-4827-b623-4d0dd8cb76dd
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=558633385 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 49.gpio_intr_with_filter_rand_intr_event.558633385
Directory /workspace/49.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/49.gpio_rand_intr_trigger.2316018692
Short name T604
Test name
Test status
Simulation time 118306528 ps
CPU time 1.4 seconds
Started Jul 01 10:47:27 AM PDT 24
Finished Jul 01 10:47:31 AM PDT 24
Peak memory 196724 kb
Host smart-e61e83b3-70f1-4134-81bd-d74b91f95167
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2316018692 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_rand_intr_trigger
.2316018692
Directory /workspace/49.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/49.gpio_random_dout_din.3051123056
Short name T162
Test name
Test status
Simulation time 38422540 ps
CPU time 0.89 seconds
Started Jul 01 10:48:05 AM PDT 24
Finished Jul 01 10:48:08 AM PDT 24
Peak memory 197320 kb
Host smart-8be891e2-ce59-480b-812e-ca8e2ff9aecf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3051123056 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_random_dout_din.3051123056
Directory /workspace/49.gpio_random_dout_din/latest

Test location /workspace/coverage/default/49.gpio_random_dout_din_no_pullup_pulldown.3120627844
Short name T518
Test name
Test status
Simulation time 70308025 ps
CPU time 0.78 seconds
Started Jul 01 10:48:05 AM PDT 24
Finished Jul 01 10:48:06 AM PDT 24
Peak memory 196020 kb
Host smart-b9b4ffe5-d551-4ab6-b1a3-03aea136df70
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3120627844 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_random_dout_din_no_pullu
p_pulldown.3120627844
Directory /workspace/49.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/49.gpio_random_long_reg_writes_reg_reads.705149729
Short name T427
Test name
Test status
Simulation time 700378956 ps
CPU time 4.56 seconds
Started Jul 01 10:48:00 AM PDT 24
Finished Jul 01 10:48:06 AM PDT 24
Peak memory 198192 kb
Host smart-15a90c5b-4093-4203-a511-19386a30e0fa
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=705149729 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_ran
dom_long_reg_writes_reg_reads.705149729
Directory /workspace/49.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/49.gpio_smoke.1217125237
Short name T274
Test name
Test status
Simulation time 209633200 ps
CPU time 1.26 seconds
Started Jul 01 10:47:34 AM PDT 24
Finished Jul 01 10:47:37 AM PDT 24
Peak memory 196460 kb
Host smart-f0553433-b07a-472c-bc57-bea3883e3467
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1217125237 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_smoke.1217125237
Directory /workspace/49.gpio_smoke/latest

Test location /workspace/coverage/default/49.gpio_smoke_no_pullup_pulldown.2713376717
Short name T649
Test name
Test status
Simulation time 39774907 ps
CPU time 0.86 seconds
Started Jul 01 10:47:27 AM PDT 24
Finished Jul 01 10:47:31 AM PDT 24
Peak memory 195908 kb
Host smart-94926f45-f84a-4ffa-89ac-a9884348267d
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2713376717 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_smoke_no_pullup_pulldown.2713376717
Directory /workspace/49.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/49.gpio_stress_all.2392146351
Short name T614
Test name
Test status
Simulation time 16665475388 ps
CPU time 97.93 seconds
Started Jul 01 10:47:36 AM PDT 24
Finished Jul 01 10:49:14 AM PDT 24
Peak memory 198764 kb
Host smart-9810cf27-01b5-4f33-a739-932b5171b352
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2392146351 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.
gpio_stress_all.2392146351
Directory /workspace/49.gpio_stress_all/latest

Test location /workspace/coverage/default/5.gpio_alert_test.1720768996
Short name T323
Test name
Test status
Simulation time 33089359 ps
CPU time 0.58 seconds
Started Jul 01 10:46:13 AM PDT 24
Finished Jul 01 10:46:14 AM PDT 24
Peak memory 194616 kb
Host smart-2fd64a73-863e-4b49-ab22-c1a64786aafe
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1720768996 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_alert_test.1720768996
Directory /workspace/5.gpio_alert_test/latest

Test location /workspace/coverage/default/5.gpio_dout_din_regs_random_rw.2453319612
Short name T362
Test name
Test status
Simulation time 26075221 ps
CPU time 0.73 seconds
Started Jul 01 10:46:11 AM PDT 24
Finished Jul 01 10:46:13 AM PDT 24
Peak memory 194696 kb
Host smart-9701fdf3-ac07-488c-a779-e128e4756bf3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2453319612 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_dout_din_regs_random_rw.2453319612
Directory /workspace/5.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/5.gpio_filter_stress.4261451802
Short name T209
Test name
Test status
Simulation time 1624926593 ps
CPU time 21.69 seconds
Started Jul 01 10:46:35 AM PDT 24
Finished Jul 01 10:47:02 AM PDT 24
Peak memory 197660 kb
Host smart-013d1895-a03a-4f33-bab5-923c93fe2db7
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4261451802 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_filter_stres
s.4261451802
Directory /workspace/5.gpio_filter_stress/latest

Test location /workspace/coverage/default/5.gpio_full_random.3663263353
Short name T543
Test name
Test status
Simulation time 199147516 ps
CPU time 0.88 seconds
Started Jul 01 10:46:34 AM PDT 24
Finished Jul 01 10:46:43 AM PDT 24
Peak memory 196760 kb
Host smart-6b317078-291f-42bd-aaa8-65195d1a9acb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3663263353 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_full_random.3663263353
Directory /workspace/5.gpio_full_random/latest

Test location /workspace/coverage/default/5.gpio_intr_rand_pgm.3783179490
Short name T182
Test name
Test status
Simulation time 109152305 ps
CPU time 0.77 seconds
Started Jul 01 10:46:30 AM PDT 24
Finished Jul 01 10:46:32 AM PDT 24
Peak memory 196900 kb
Host smart-1ded81d7-3bae-4d47-9fb3-c6d256fe212d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3783179490 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_intr_rand_pgm.3783179490
Directory /workspace/5.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/5.gpio_intr_with_filter_rand_intr_event.730856725
Short name T365
Test name
Test status
Simulation time 94603660 ps
CPU time 3.78 seconds
Started Jul 01 10:46:33 AM PDT 24
Finished Jul 01 10:46:38 AM PDT 24
Peak memory 198696 kb
Host smart-4c0d182e-cd9d-41b2-a1d1-5322b69699e2
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=730856725 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 5.gpio_intr_with_filter_rand_intr_event.730856725
Directory /workspace/5.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/5.gpio_rand_intr_trigger.786243267
Short name T286
Test name
Test status
Simulation time 592696937 ps
CPU time 2.84 seconds
Started Jul 01 10:46:13 AM PDT 24
Finished Jul 01 10:46:17 AM PDT 24
Peak memory 197624 kb
Host smart-d4c6065a-5364-4812-a928-c9f19023add4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=786243267 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_rand_intr_trigger.786243267
Directory /workspace/5.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/5.gpio_random_dout_din.1925199190
Short name T109
Test name
Test status
Simulation time 14897821 ps
CPU time 0.66 seconds
Started Jul 01 10:46:09 AM PDT 24
Finished Jul 01 10:46:11 AM PDT 24
Peak memory 195744 kb
Host smart-ab0fba9c-bb9e-4700-a154-39594cf809df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1925199190 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_random_dout_din.1925199190
Directory /workspace/5.gpio_random_dout_din/latest

Test location /workspace/coverage/default/5.gpio_random_dout_din_no_pullup_pulldown.2164915206
Short name T534
Test name
Test status
Simulation time 141925899 ps
CPU time 0.94 seconds
Started Jul 01 10:46:04 AM PDT 24
Finished Jul 01 10:46:06 AM PDT 24
Peak memory 196600 kb
Host smart-ee66d9cf-96fe-46eb-b6aa-ff0c7d4ec80a
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2164915206 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_random_dout_din_no_pullup
_pulldown.2164915206
Directory /workspace/5.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/5.gpio_random_long_reg_writes_reg_reads.2581473570
Short name T1
Test name
Test status
Simulation time 1786539453 ps
CPU time 4.14 seconds
Started Jul 01 10:46:21 AM PDT 24
Finished Jul 01 10:46:25 AM PDT 24
Peak memory 198560 kb
Host smart-761166a2-d74d-4d41-85f6-a9b9cfe8330a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2581473570 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_ran
dom_long_reg_writes_reg_reads.2581473570
Directory /workspace/5.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/5.gpio_smoke.1135107708
Short name T111
Test name
Test status
Simulation time 142267281 ps
CPU time 0.76 seconds
Started Jul 01 10:46:18 AM PDT 24
Finished Jul 01 10:46:19 AM PDT 24
Peak memory 195840 kb
Host smart-f7bf6c47-4fae-477f-980d-14ce2ef64674
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1135107708 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_smoke.1135107708
Directory /workspace/5.gpio_smoke/latest

Test location /workspace/coverage/default/5.gpio_smoke_no_pullup_pulldown.3294797298
Short name T698
Test name
Test status
Simulation time 144123111 ps
CPU time 1.19 seconds
Started Jul 01 10:46:34 AM PDT 24
Finished Jul 01 10:46:40 AM PDT 24
Peak memory 196492 kb
Host smart-2ba478af-8a76-4c09-b446-c07bef39dbd5
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3294797298 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_smoke_no_pullup_pulldown.3294797298
Directory /workspace/5.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/5.gpio_stress_all.936860042
Short name T402
Test name
Test status
Simulation time 2553641616 ps
CPU time 36.78 seconds
Started Jul 01 10:46:12 AM PDT 24
Finished Jul 01 10:46:50 AM PDT 24
Peak memory 198832 kb
Host smart-84dfad92-c5fa-43a7-93b8-4dc59923bf70
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=936860042 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gp
io_stress_all.936860042
Directory /workspace/5.gpio_stress_all/latest

Test location /workspace/coverage/default/6.gpio_alert_test.3241228538
Short name T37
Test name
Test status
Simulation time 15153340 ps
CPU time 0.6 seconds
Started Jul 01 10:46:50 AM PDT 24
Finished Jul 01 10:46:51 AM PDT 24
Peak memory 195668 kb
Host smart-31e469b4-6380-4bf0-9323-c57dd1e76dda
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3241228538 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_alert_test.3241228538
Directory /workspace/6.gpio_alert_test/latest

Test location /workspace/coverage/default/6.gpio_dout_din_regs_random_rw.2380005428
Short name T325
Test name
Test status
Simulation time 42639473 ps
CPU time 0.7 seconds
Started Jul 01 10:46:34 AM PDT 24
Finished Jul 01 10:46:39 AM PDT 24
Peak memory 194620 kb
Host smart-3d5ce7d6-4ad3-49fe-aa88-1a0881f4c813
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2380005428 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_dout_din_regs_random_rw.2380005428
Directory /workspace/6.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/6.gpio_filter_stress.3691168146
Short name T526
Test name
Test status
Simulation time 3922138312 ps
CPU time 19.4 seconds
Started Jul 01 10:46:18 AM PDT 24
Finished Jul 01 10:46:38 AM PDT 24
Peak memory 197628 kb
Host smart-09265bee-0e36-43bc-b005-822e22b3b2f4
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3691168146 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_filter_stres
s.3691168146
Directory /workspace/6.gpio_filter_stress/latest

Test location /workspace/coverage/default/6.gpio_full_random.2139815506
Short name T462
Test name
Test status
Simulation time 26517200 ps
CPU time 0.7 seconds
Started Jul 01 10:46:35 AM PDT 24
Finished Jul 01 10:46:42 AM PDT 24
Peak memory 195396 kb
Host smart-455717a6-bf54-4163-9631-9d8f41fe2c47
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2139815506 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_full_random.2139815506
Directory /workspace/6.gpio_full_random/latest

Test location /workspace/coverage/default/6.gpio_intr_rand_pgm.4112637871
Short name T483
Test name
Test status
Simulation time 231417476 ps
CPU time 1.06 seconds
Started Jul 01 10:46:29 AM PDT 24
Finished Jul 01 10:46:30 AM PDT 24
Peak memory 196568 kb
Host smart-76e70890-0aae-49a5-8e87-5a5983ffe6d0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4112637871 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_intr_rand_pgm.4112637871
Directory /workspace/6.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/6.gpio_intr_with_filter_rand_intr_event.4165100146
Short name T497
Test name
Test status
Simulation time 1360988193 ps
CPU time 2.83 seconds
Started Jul 01 10:46:12 AM PDT 24
Finished Jul 01 10:46:16 AM PDT 24
Peak memory 198736 kb
Host smart-affde15d-4e53-475a-826c-6d96a7493c36
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4165100146 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 6.gpio_intr_with_filter_rand_intr_event.4165100146
Directory /workspace/6.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/6.gpio_rand_intr_trigger.4286835979
Short name T529
Test name
Test status
Simulation time 103302211 ps
CPU time 2.1 seconds
Started Jul 01 10:46:31 AM PDT 24
Finished Jul 01 10:46:34 AM PDT 24
Peak memory 197728 kb
Host smart-7c5edb79-95f6-40f5-96bf-d48d6a74c3aa
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4286835979 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_rand_intr_trigger.
4286835979
Directory /workspace/6.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/6.gpio_random_dout_din.3954863258
Short name T57
Test name
Test status
Simulation time 48909387 ps
CPU time 1.03 seconds
Started Jul 01 10:46:39 AM PDT 24
Finished Jul 01 10:46:44 AM PDT 24
Peak memory 196572 kb
Host smart-b1cf61d0-f0b6-4cb7-8b9d-a3edda2d3ea9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3954863258 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_random_dout_din.3954863258
Directory /workspace/6.gpio_random_dout_din/latest

Test location /workspace/coverage/default/6.gpio_random_dout_din_no_pullup_pulldown.721546059
Short name T445
Test name
Test status
Simulation time 45899433 ps
CPU time 0.74 seconds
Started Jul 01 10:46:12 AM PDT 24
Finished Jul 01 10:46:14 AM PDT 24
Peak memory 196076 kb
Host smart-a77704fd-11c4-42a9-8915-3e8e99708a3a
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=721546059 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_random_dout_din_no_pullup_
pulldown.721546059
Directory /workspace/6.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/6.gpio_random_long_reg_writes_reg_reads.3444432229
Short name T218
Test name
Test status
Simulation time 25709802 ps
CPU time 1.15 seconds
Started Jul 01 10:46:34 AM PDT 24
Finished Jul 01 10:46:40 AM PDT 24
Peak memory 198472 kb
Host smart-1b29fd44-ba04-4cd1-ae49-f5615c6ef732
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3444432229 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_ran
dom_long_reg_writes_reg_reads.3444432229
Directory /workspace/6.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/6.gpio_smoke.3397906582
Short name T108
Test name
Test status
Simulation time 119705230 ps
CPU time 1.13 seconds
Started Jul 01 10:46:14 AM PDT 24
Finished Jul 01 10:46:21 AM PDT 24
Peak memory 196480 kb
Host smart-055bc61b-d05c-4964-b815-5deda38508ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3397906582 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_smoke.3397906582
Directory /workspace/6.gpio_smoke/latest

Test location /workspace/coverage/default/6.gpio_smoke_no_pullup_pulldown.362832863
Short name T115
Test name
Test status
Simulation time 116033124 ps
CPU time 1.1 seconds
Started Jul 01 10:46:12 AM PDT 24
Finished Jul 01 10:46:14 AM PDT 24
Peak memory 196524 kb
Host smart-08412fea-ca52-44d0-9c37-cc79b5a5ba87
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=362832863 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_smoke_no_pullup_pulldown.362832863
Directory /workspace/6.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/6.gpio_stress_all.4034862462
Short name T513
Test name
Test status
Simulation time 52701940159 ps
CPU time 160.65 seconds
Started Jul 01 10:46:29 AM PDT 24
Finished Jul 01 10:49:10 AM PDT 24
Peak memory 198764 kb
Host smart-546fe5a4-6e08-4618-b60d-39e80c15329f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4034862462 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.g
pio_stress_all.4034862462
Directory /workspace/6.gpio_stress_all/latest

Test location /workspace/coverage/default/7.gpio_alert_test.4236606662
Short name T592
Test name
Test status
Simulation time 13995924 ps
CPU time 0.55 seconds
Started Jul 01 10:46:13 AM PDT 24
Finished Jul 01 10:46:15 AM PDT 24
Peak memory 194656 kb
Host smart-90e74dd7-9795-41e7-92bb-1d8f3fee3a5b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4236606662 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_alert_test.4236606662
Directory /workspace/7.gpio_alert_test/latest

Test location /workspace/coverage/default/7.gpio_dout_din_regs_random_rw.1238452249
Short name T210
Test name
Test status
Simulation time 47323940 ps
CPU time 0.59 seconds
Started Jul 01 10:46:32 AM PDT 24
Finished Jul 01 10:46:34 AM PDT 24
Peak memory 194664 kb
Host smart-23d6fd0c-8b64-44fe-a29a-8799dae1eeef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1238452249 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_dout_din_regs_random_rw.1238452249
Directory /workspace/7.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/7.gpio_filter_stress.2433038856
Short name T664
Test name
Test status
Simulation time 417996352 ps
CPU time 5.75 seconds
Started Jul 01 10:46:12 AM PDT 24
Finished Jul 01 10:46:19 AM PDT 24
Peak memory 197372 kb
Host smart-3344b023-78dc-4cc4-9295-a2338128ccc0
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2433038856 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_filter_stres
s.2433038856
Directory /workspace/7.gpio_filter_stress/latest

Test location /workspace/coverage/default/7.gpio_full_random.3803256022
Short name T20
Test name
Test status
Simulation time 707484084 ps
CPU time 0.86 seconds
Started Jul 01 10:46:36 AM PDT 24
Finished Jul 01 10:46:43 AM PDT 24
Peak memory 196572 kb
Host smart-fdd8244a-2bfd-4344-a558-0084c2cb89af
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3803256022 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_full_random.3803256022
Directory /workspace/7.gpio_full_random/latest

Test location /workspace/coverage/default/7.gpio_intr_rand_pgm.2752387145
Short name T495
Test name
Test status
Simulation time 19663798 ps
CPU time 0.66 seconds
Started Jul 01 10:46:34 AM PDT 24
Finished Jul 01 10:46:39 AM PDT 24
Peak memory 194964 kb
Host smart-f7ac114e-9e09-474c-813f-c57d562b2a8b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2752387145 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_intr_rand_pgm.2752387145
Directory /workspace/7.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/7.gpio_intr_with_filter_rand_intr_event.2895967720
Short name T250
Test name
Test status
Simulation time 132384401 ps
CPU time 2.66 seconds
Started Jul 01 10:46:12 AM PDT 24
Finished Jul 01 10:46:16 AM PDT 24
Peak memory 198684 kb
Host smart-73466875-7c50-43be-9a2a-47a7b5ca02d6
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2895967720 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 7.gpio_intr_with_filter_rand_intr_event.2895967720
Directory /workspace/7.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/7.gpio_rand_intr_trigger.3619308999
Short name T311
Test name
Test status
Simulation time 45013572 ps
CPU time 1.16 seconds
Started Jul 01 10:47:00 AM PDT 24
Finished Jul 01 10:47:03 AM PDT 24
Peak memory 197012 kb
Host smart-82b1e75c-d094-4161-8d28-2dd7458f91cd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3619308999 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_rand_intr_trigger.
3619308999
Directory /workspace/7.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/7.gpio_random_dout_din.2714696715
Short name T405
Test name
Test status
Simulation time 118186474 ps
CPU time 0.8 seconds
Started Jul 01 10:46:14 AM PDT 24
Finished Jul 01 10:46:15 AM PDT 24
Peak memory 196088 kb
Host smart-d5f7ee3e-2c8c-46a2-acc0-70461f643c4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2714696715 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_random_dout_din.2714696715
Directory /workspace/7.gpio_random_dout_din/latest

Test location /workspace/coverage/default/7.gpio_random_dout_din_no_pullup_pulldown.3246039811
Short name T292
Test name
Test status
Simulation time 261127736 ps
CPU time 1.18 seconds
Started Jul 01 10:46:34 AM PDT 24
Finished Jul 01 10:46:39 AM PDT 24
Peak memory 198560 kb
Host smart-8ed63e27-a7c0-46bc-99aa-d30129a9bc4b
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3246039811 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_random_dout_din_no_pullup
_pulldown.3246039811
Directory /workspace/7.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/7.gpio_random_long_reg_writes_reg_reads.3751715434
Short name T548
Test name
Test status
Simulation time 249609803 ps
CPU time 3.22 seconds
Started Jul 01 10:46:41 AM PDT 24
Finished Jul 01 10:46:47 AM PDT 24
Peak memory 198668 kb
Host smart-bf2dfb84-a6c6-40e0-8706-b8dc5a08c5fe
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3751715434 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_ran
dom_long_reg_writes_reg_reads.3751715434
Directory /workspace/7.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/7.gpio_smoke.2412783138
Short name T585
Test name
Test status
Simulation time 113586953 ps
CPU time 1 seconds
Started Jul 01 10:46:12 AM PDT 24
Finished Jul 01 10:46:15 AM PDT 24
Peak memory 197796 kb
Host smart-7f8fcfeb-d2f2-43a5-a969-ff6abda4e4c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2412783138 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_smoke.2412783138
Directory /workspace/7.gpio_smoke/latest

Test location /workspace/coverage/default/7.gpio_smoke_no_pullup_pulldown.4141369286
Short name T713
Test name
Test status
Simulation time 77763913 ps
CPU time 0.97 seconds
Started Jul 01 10:46:31 AM PDT 24
Finished Jul 01 10:46:33 AM PDT 24
Peak memory 196412 kb
Host smart-80c0000e-9070-43eb-b5a7-cbe8537dd566
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4141369286 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_smoke_no_pullup_pulldown.4141369286
Directory /workspace/7.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/7.gpio_stress_all.1878416654
Short name T455
Test name
Test status
Simulation time 51518807701 ps
CPU time 32.95 seconds
Started Jul 01 10:46:35 AM PDT 24
Finished Jul 01 10:47:12 AM PDT 24
Peak memory 198768 kb
Host smart-46510cf9-cf74-4912-aef3-912a41311ec3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1878416654 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.g
pio_stress_all.1878416654
Directory /workspace/7.gpio_stress_all/latest

Test location /workspace/coverage/default/8.gpio_alert_test.1736652231
Short name T584
Test name
Test status
Simulation time 23509297 ps
CPU time 0.57 seconds
Started Jul 01 10:46:35 AM PDT 24
Finished Jul 01 10:46:40 AM PDT 24
Peak memory 194532 kb
Host smart-a507aafc-5c8f-42b8-b1dc-167d0fac5744
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1736652231 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_alert_test.1736652231
Directory /workspace/8.gpio_alert_test/latest

Test location /workspace/coverage/default/8.gpio_dout_din_regs_random_rw.1962240201
Short name T187
Test name
Test status
Simulation time 81399969 ps
CPU time 0.69 seconds
Started Jul 01 10:46:44 AM PDT 24
Finished Jul 01 10:46:46 AM PDT 24
Peak memory 195976 kb
Host smart-5f93048f-2c30-44dd-bca7-0ac982d9b8b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1962240201 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_dout_din_regs_random_rw.1962240201
Directory /workspace/8.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/8.gpio_filter_stress.2468810354
Short name T463
Test name
Test status
Simulation time 125811059 ps
CPU time 6.09 seconds
Started Jul 01 10:46:31 AM PDT 24
Finished Jul 01 10:46:38 AM PDT 24
Peak memory 198680 kb
Host smart-b207b8af-0168-43fd-816a-e39d9536fd62
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2468810354 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_filter_stres
s.2468810354
Directory /workspace/8.gpio_filter_stress/latest

Test location /workspace/coverage/default/8.gpio_full_random.4235377427
Short name T404
Test name
Test status
Simulation time 298993202 ps
CPU time 0.99 seconds
Started Jul 01 10:46:35 AM PDT 24
Finished Jul 01 10:46:41 AM PDT 24
Peak memory 196936 kb
Host smart-d0f85ca5-d43c-4dca-b2f2-4e1085da4fc9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4235377427 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_full_random.4235377427
Directory /workspace/8.gpio_full_random/latest

Test location /workspace/coverage/default/8.gpio_intr_rand_pgm.3060226862
Short name T11
Test name
Test status
Simulation time 209722560 ps
CPU time 1.24 seconds
Started Jul 01 10:46:34 AM PDT 24
Finished Jul 01 10:46:38 AM PDT 24
Peak memory 197668 kb
Host smart-2e9620df-01f5-4349-852f-c6ce26939470
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3060226862 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_intr_rand_pgm.3060226862
Directory /workspace/8.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/8.gpio_intr_with_filter_rand_intr_event.2595007251
Short name T466
Test name
Test status
Simulation time 36086798 ps
CPU time 1.44 seconds
Started Jul 01 10:46:35 AM PDT 24
Finished Jul 01 10:46:41 AM PDT 24
Peak memory 197596 kb
Host smart-89045249-2b05-43e0-8cd7-502a776fdbf5
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2595007251 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 8.gpio_intr_with_filter_rand_intr_event.2595007251
Directory /workspace/8.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/8.gpio_rand_intr_trigger.374791541
Short name T163
Test name
Test status
Simulation time 106206698 ps
CPU time 2.31 seconds
Started Jul 01 10:46:13 AM PDT 24
Finished Jul 01 10:46:16 AM PDT 24
Peak memory 197188 kb
Host smart-1b15ccf9-2639-4d14-8014-d34a4b5dae87
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=374791541 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_rand_intr_trigger.374791541
Directory /workspace/8.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/8.gpio_random_dout_din.176300338
Short name T398
Test name
Test status
Simulation time 77247805 ps
CPU time 1.08 seconds
Started Jul 01 10:46:10 AM PDT 24
Finished Jul 01 10:46:12 AM PDT 24
Peak memory 196492 kb
Host smart-b0797154-a47c-4f18-a6b9-742aeba24c9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=176300338 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_random_dout_din.176300338
Directory /workspace/8.gpio_random_dout_din/latest

Test location /workspace/coverage/default/8.gpio_random_dout_din_no_pullup_pulldown.1095631562
Short name T519
Test name
Test status
Simulation time 16300501 ps
CPU time 0.68 seconds
Started Jul 01 10:46:19 AM PDT 24
Finished Jul 01 10:46:20 AM PDT 24
Peak memory 195672 kb
Host smart-d0ec7eb6-422e-4c33-b676-056374da1787
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1095631562 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_random_dout_din_no_pullup
_pulldown.1095631562
Directory /workspace/8.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/8.gpio_random_long_reg_writes_reg_reads.1632642514
Short name T393
Test name
Test status
Simulation time 81120907 ps
CPU time 3.88 seconds
Started Jul 01 10:46:33 AM PDT 24
Finished Jul 01 10:46:37 AM PDT 24
Peak memory 198636 kb
Host smart-83c5c01b-2537-4002-a88c-b30954321561
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1632642514 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_ran
dom_long_reg_writes_reg_reads.1632642514
Directory /workspace/8.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/8.gpio_smoke.1563437119
Short name T457
Test name
Test status
Simulation time 43542804 ps
CPU time 1.17 seconds
Started Jul 01 10:46:33 AM PDT 24
Finished Jul 01 10:46:38 AM PDT 24
Peak memory 197288 kb
Host smart-ba801baf-eff5-4096-aa57-d4f32b4526e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1563437119 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_smoke.1563437119
Directory /workspace/8.gpio_smoke/latest

Test location /workspace/coverage/default/8.gpio_smoke_no_pullup_pulldown.2707246889
Short name T136
Test name
Test status
Simulation time 131013214 ps
CPU time 1.14 seconds
Started Jul 01 10:46:12 AM PDT 24
Finished Jul 01 10:46:15 AM PDT 24
Peak memory 196448 kb
Host smart-2a4b8068-d085-45c2-8947-9ca5fdc988b9
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2707246889 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_smoke_no_pullup_pulldown.2707246889
Directory /workspace/8.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/8.gpio_stress_all.3960896219
Short name T609
Test name
Test status
Simulation time 14167213135 ps
CPU time 101.39 seconds
Started Jul 01 10:46:33 AM PDT 24
Finished Jul 01 10:48:17 AM PDT 24
Peak memory 198784 kb
Host smart-9f43f803-a439-4fb3-82ae-326cdeb8f2bf
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3960896219 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.g
pio_stress_all.3960896219
Directory /workspace/8.gpio_stress_all/latest

Test location /workspace/coverage/default/9.gpio_alert_test.433116956
Short name T460
Test name
Test status
Simulation time 83470065 ps
CPU time 0.62 seconds
Started Jul 01 10:46:38 AM PDT 24
Finished Jul 01 10:46:43 AM PDT 24
Peak memory 194860 kb
Host smart-29bd5c93-19e8-434f-9c74-10d8d41539b2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=433116956 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_alert_test.433116956
Directory /workspace/9.gpio_alert_test/latest

Test location /workspace/coverage/default/9.gpio_dout_din_regs_random_rw.367209697
Short name T273
Test name
Test status
Simulation time 30366333 ps
CPU time 0.76 seconds
Started Jul 01 10:46:39 AM PDT 24
Finished Jul 01 10:46:44 AM PDT 24
Peak memory 195928 kb
Host smart-f6048392-1929-41de-9c30-7f5f26bec397
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=367209697 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_dout_din_regs_random_rw.367209697
Directory /workspace/9.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/9.gpio_filter_stress.2916339554
Short name T546
Test name
Test status
Simulation time 492247180 ps
CPU time 4.54 seconds
Started Jul 01 10:46:32 AM PDT 24
Finished Jul 01 10:46:37 AM PDT 24
Peak memory 196160 kb
Host smart-851f95b3-7b9a-4583-bd0a-054459b2cbac
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2916339554 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_filter_stres
s.2916339554
Directory /workspace/9.gpio_filter_stress/latest

Test location /workspace/coverage/default/9.gpio_full_random.610677235
Short name T389
Test name
Test status
Simulation time 169935439 ps
CPU time 0.8 seconds
Started Jul 01 10:46:29 AM PDT 24
Finished Jul 01 10:46:30 AM PDT 24
Peak memory 196392 kb
Host smart-b5231712-7982-4b7e-8925-8245701c3460
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=610677235 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_full_random.610677235
Directory /workspace/9.gpio_full_random/latest

Test location /workspace/coverage/default/9.gpio_intr_rand_pgm.4223911903
Short name T606
Test name
Test status
Simulation time 140935885 ps
CPU time 1.16 seconds
Started Jul 01 10:46:53 AM PDT 24
Finished Jul 01 10:46:55 AM PDT 24
Peak memory 197528 kb
Host smart-575d61c8-6b20-4b85-8f0f-90fc4dbffc9f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4223911903 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_intr_rand_pgm.4223911903
Directory /workspace/9.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/9.gpio_intr_with_filter_rand_intr_event.4081583662
Short name T305
Test name
Test status
Simulation time 81361633 ps
CPU time 2.9 seconds
Started Jul 01 10:46:34 AM PDT 24
Finished Jul 01 10:46:41 AM PDT 24
Peak memory 198620 kb
Host smart-7bedc8f5-eadc-4b65-8847-e683db10df65
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4081583662 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 9.gpio_intr_with_filter_rand_intr_event.4081583662
Directory /workspace/9.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/9.gpio_rand_intr_trigger.3315579139
Short name T200
Test name
Test status
Simulation time 206008775 ps
CPU time 1.47 seconds
Started Jul 01 10:46:37 AM PDT 24
Finished Jul 01 10:46:43 AM PDT 24
Peak memory 196608 kb
Host smart-043e44aa-e09d-46cd-9e97-81e07bd30936
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3315579139 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_rand_intr_trigger.
3315579139
Directory /workspace/9.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/9.gpio_random_dout_din.3951207551
Short name T272
Test name
Test status
Simulation time 153313359 ps
CPU time 0.88 seconds
Started Jul 01 10:46:51 AM PDT 24
Finished Jul 01 10:46:53 AM PDT 24
Peak memory 196684 kb
Host smart-72e6a6fb-2b52-47bd-8bbd-318dda5a5340
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3951207551 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_random_dout_din.3951207551
Directory /workspace/9.gpio_random_dout_din/latest

Test location /workspace/coverage/default/9.gpio_random_dout_din_no_pullup_pulldown.234232992
Short name T618
Test name
Test status
Simulation time 78499310 ps
CPU time 0.67 seconds
Started Jul 01 10:46:26 AM PDT 24
Finished Jul 01 10:46:27 AM PDT 24
Peak memory 195664 kb
Host smart-12efbde3-763d-4420-9e71-8d379d816188
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=234232992 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_random_dout_din_no_pullup_
pulldown.234232992
Directory /workspace/9.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/9.gpio_random_long_reg_writes_reg_reads.601760935
Short name T686
Test name
Test status
Simulation time 1034153401 ps
CPU time 5.39 seconds
Started Jul 01 10:46:26 AM PDT 24
Finished Jul 01 10:46:32 AM PDT 24
Peak memory 198804 kb
Host smart-165d97fe-5653-45bd-a368-ddf3ba31047e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=601760935 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_rand
om_long_reg_writes_reg_reads.601760935
Directory /workspace/9.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/9.gpio_smoke.2031537834
Short name T128
Test name
Test status
Simulation time 46054791 ps
CPU time 1.13 seconds
Started Jul 01 10:46:41 AM PDT 24
Finished Jul 01 10:46:45 AM PDT 24
Peak memory 197076 kb
Host smart-02bc1b9a-a609-4a6c-a920-d3fefa374f1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2031537834 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_smoke.2031537834
Directory /workspace/9.gpio_smoke/latest

Test location /workspace/coverage/default/9.gpio_smoke_no_pullup_pulldown.1968735071
Short name T458
Test name
Test status
Simulation time 39889195 ps
CPU time 0.97 seconds
Started Jul 01 10:46:30 AM PDT 24
Finished Jul 01 10:46:32 AM PDT 24
Peak memory 196896 kb
Host smart-92c444cd-e54d-4bde-bb89-bcf39cc1627c
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1968735071 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_smoke_no_pullup_pulldown.1968735071
Directory /workspace/9.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/9.gpio_stress_all.2065762259
Short name T193
Test name
Test status
Simulation time 10563362989 ps
CPU time 122.77 seconds
Started Jul 01 10:46:39 AM PDT 24
Finished Jul 01 10:48:46 AM PDT 24
Peak memory 198696 kb
Host smart-b0fc9130-5775-4bf7-8820-32808ee3b80a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2065762259 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.g
pio_stress_all.2065762259
Directory /workspace/9.gpio_stress_all/latest

Test location /workspace/coverage/en_cdc_prims/0.gpio_smoke_en_cdc_prim.1708639644
Short name T877
Test name
Test status
Simulation time 186069142 ps
CPU time 1.33 seconds
Started Jul 01 10:38:33 AM PDT 24
Finished Jul 01 10:38:35 AM PDT 24
Peak memory 197276 kb
Host smart-1d43c3ed-8bc2-428f-8f34-87fabb212916
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1708639644 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 0.gpio_smoke_en_cdc_prim.1708639644
Directory /workspace/0.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/0.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1405253120
Short name T874
Test name
Test status
Simulation time 28581779 ps
CPU time 0.76 seconds
Started Jul 01 10:38:37 AM PDT 24
Finished Jul 01 10:38:49 AM PDT 24
Peak memory 196432 kb
Host smart-7da6ea2d-74c8-4850-a0e8-b18d6766c5f3
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1405253120 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 0.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.1405253120
Directory /workspace/0.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/1.gpio_smoke_en_cdc_prim.120868962
Short name T854
Test name
Test status
Simulation time 100437090 ps
CPU time 0.99 seconds
Started Jul 01 10:38:45 AM PDT 24
Finished Jul 01 10:38:47 AM PDT 24
Peak memory 196936 kb
Host smart-33456dda-8859-45c8-9599-8b0e9ac7c133
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=120868962 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 1.gpio_smoke_en_cdc_prim.120868962
Directory /workspace/1.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/1.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2640907360
Short name T927
Test name
Test status
Simulation time 192312628 ps
CPU time 0.98 seconds
Started Jul 01 10:38:43 AM PDT 24
Finished Jul 01 10:38:46 AM PDT 24
Peak memory 196976 kb
Host smart-d775262f-e41a-4e16-a155-1c2c41f069b6
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2640907360 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 1.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.2640907360
Directory /workspace/1.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/10.gpio_smoke_en_cdc_prim.1003809484
Short name T865
Test name
Test status
Simulation time 67285055 ps
CPU time 1.21 seconds
Started Jul 01 10:38:38 AM PDT 24
Finished Jul 01 10:38:40 AM PDT 24
Peak memory 196192 kb
Host smart-e385f85f-5abf-41d1-be53-38dce8992237
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1003809484 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 10.gpio_smoke_en_cdc_prim.1003809484
Directory /workspace/10.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/10.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3300615292
Short name T873
Test name
Test status
Simulation time 33322179 ps
CPU time 1.04 seconds
Started Jul 01 10:38:39 AM PDT 24
Finished Jul 01 10:38:41 AM PDT 24
Peak memory 198352 kb
Host smart-f0ee1664-69c4-4953-bce3-7f27f595c052
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3300615292 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 10.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3300615292
Directory /workspace/10.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/11.gpio_smoke_en_cdc_prim.3476479344
Short name T897
Test name
Test status
Simulation time 207954708 ps
CPU time 1.21 seconds
Started Jul 01 10:38:43 AM PDT 24
Finished Jul 01 10:38:45 AM PDT 24
Peak memory 196020 kb
Host smart-b4278a5b-dbca-4b2a-83d3-f9ebb94243fc
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3476479344 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 11.gpio_smoke_en_cdc_prim.3476479344
Directory /workspace/11.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/11.gpio_smoke_no_pullup_pulldown_en_cdc_prim.422629495
Short name T916
Test name
Test status
Simulation time 493797619 ps
CPU time 1.44 seconds
Started Jul 01 10:39:27 AM PDT 24
Finished Jul 01 10:39:29 AM PDT 24
Peak memory 196168 kb
Host smart-259ef2c4-8df8-49cd-8cc1-dbc36f0a5df1
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=422629495 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 11.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.422629495
Directory /workspace/11.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/12.gpio_smoke_en_cdc_prim.4221078239
Short name T856
Test name
Test status
Simulation time 23779560 ps
CPU time 0.77 seconds
Started Jul 01 10:38:35 AM PDT 24
Finished Jul 01 10:38:37 AM PDT 24
Peak memory 195740 kb
Host smart-91aabb56-26d7-41f0-b6d8-7fc974e41eb4
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=4221078239 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 12.gpio_smoke_en_cdc_prim.4221078239
Directory /workspace/12.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/12.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2081983105
Short name T863
Test name
Test status
Simulation time 215831350 ps
CPU time 1.45 seconds
Started Jul 01 10:38:35 AM PDT 24
Finished Jul 01 10:38:38 AM PDT 24
Peak memory 198292 kb
Host smart-bf3e71bb-d62e-4f40-81a7-02267743b30e
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2081983105 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 12.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2081983105
Directory /workspace/12.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/13.gpio_smoke_en_cdc_prim.1567398720
Short name T848
Test name
Test status
Simulation time 103374170 ps
CPU time 1.13 seconds
Started Jul 01 10:38:51 AM PDT 24
Finished Jul 01 10:38:54 AM PDT 24
Peak memory 198336 kb
Host smart-b4bb3202-8894-46db-89be-dbb9daa59b8c
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1567398720 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 13.gpio_smoke_en_cdc_prim.1567398720
Directory /workspace/13.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/13.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3353063329
Short name T895
Test name
Test status
Simulation time 134888186 ps
CPU time 1.11 seconds
Started Jul 01 10:39:27 AM PDT 24
Finished Jul 01 10:39:29 AM PDT 24
Peak memory 196916 kb
Host smart-0afc1d3d-95f5-4188-bcd9-a79e500d3ba2
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3353063329 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 13.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3353063329
Directory /workspace/13.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/14.gpio_smoke_en_cdc_prim.4103345514
Short name T892
Test name
Test status
Simulation time 82281746 ps
CPU time 1.14 seconds
Started Jul 01 10:38:36 AM PDT 24
Finished Jul 01 10:38:38 AM PDT 24
Peak memory 196224 kb
Host smart-672c82dd-27ad-424d-aa81-b4a8e939c9a5
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=4103345514 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 14.gpio_smoke_en_cdc_prim.4103345514
Directory /workspace/14.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/14.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2232637783
Short name T845
Test name
Test status
Simulation time 82565104 ps
CPU time 1.23 seconds
Started Jul 01 10:38:37 AM PDT 24
Finished Jul 01 10:38:40 AM PDT 24
Peak memory 198344 kb
Host smart-767462b2-c64a-4eb5-bc69-9babdd833515
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2232637783 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 14.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2232637783
Directory /workspace/14.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/15.gpio_smoke_en_cdc_prim.2732373764
Short name T915
Test name
Test status
Simulation time 36018867 ps
CPU time 1.06 seconds
Started Jul 01 10:39:32 AM PDT 24
Finished Jul 01 10:39:35 AM PDT 24
Peak memory 196912 kb
Host smart-bcf57c18-7e9b-43a1-93c7-a01586d9f8a4
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2732373764 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 15.gpio_smoke_en_cdc_prim.2732373764
Directory /workspace/15.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/15.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4086776523
Short name T923
Test name
Test status
Simulation time 384274344 ps
CPU time 1.05 seconds
Started Jul 01 10:38:47 AM PDT 24
Finished Jul 01 10:38:49 AM PDT 24
Peak memory 196020 kb
Host smart-1e2da5d6-8e9f-46dd-b6c9-e919627292aa
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4086776523 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 15.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.4086776523
Directory /workspace/15.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/16.gpio_smoke_en_cdc_prim.3432792879
Short name T840
Test name
Test status
Simulation time 83940217 ps
CPU time 1.4 seconds
Started Jul 01 10:39:04 AM PDT 24
Finished Jul 01 10:39:08 AM PDT 24
Peak memory 196900 kb
Host smart-fac01d5a-0fde-43f7-99dc-7d27436b3fb0
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3432792879 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 16.gpio_smoke_en_cdc_prim.3432792879
Directory /workspace/16.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/16.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2161857623
Short name T905
Test name
Test status
Simulation time 289021825 ps
CPU time 1.24 seconds
Started Jul 01 10:38:45 AM PDT 24
Finished Jul 01 10:38:48 AM PDT 24
Peak memory 198340 kb
Host smart-9a763ba5-1c49-4c12-9216-2f89724e2291
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2161857623 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 16.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2161857623
Directory /workspace/16.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/17.gpio_smoke_en_cdc_prim.92347386
Short name T935
Test name
Test status
Simulation time 34934773 ps
CPU time 0.87 seconds
Started Jul 01 10:38:52 AM PDT 24
Finished Jul 01 10:38:54 AM PDT 24
Peak memory 196988 kb
Host smart-0e01f145-2e8e-4706-bed3-3f9427f4b8a3
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=92347386 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 17.gpio_smoke_en_cdc_prim.92347386
Directory /workspace/17.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/17.gpio_smoke_no_pullup_pulldown_en_cdc_prim.388158229
Short name T849
Test name
Test status
Simulation time 157700669 ps
CPU time 1.34 seconds
Started Jul 01 10:39:27 AM PDT 24
Finished Jul 01 10:39:29 AM PDT 24
Peak memory 198380 kb
Host smart-80f298b8-ddc7-47c2-937f-899c1a7b2a2d
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=388158229 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 17.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.388158229
Directory /workspace/17.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/18.gpio_smoke_en_cdc_prim.99944813
Short name T886
Test name
Test status
Simulation time 41467902 ps
CPU time 1.18 seconds
Started Jul 01 10:39:20 AM PDT 24
Finished Jul 01 10:39:23 AM PDT 24
Peak memory 196044 kb
Host smart-eb7e1f65-6234-4c13-9d9b-063458b3c03d
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=99944813 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 18.gpio_smoke_en_cdc_prim.99944813
Directory /workspace/18.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/18.gpio_smoke_no_pullup_pulldown_en_cdc_prim.278435231
Short name T926
Test name
Test status
Simulation time 66865569 ps
CPU time 0.72 seconds
Started Jul 01 10:38:50 AM PDT 24
Finished Jul 01 10:38:53 AM PDT 24
Peak memory 195732 kb
Host smart-572866f7-37f5-45d5-9aff-e533101f42f2
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=278435231 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 18.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.278435231
Directory /workspace/18.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/19.gpio_smoke_en_cdc_prim.302029245
Short name T846
Test name
Test status
Simulation time 39637001 ps
CPU time 1.03 seconds
Started Jul 01 10:38:50 AM PDT 24
Finished Jul 01 10:38:52 AM PDT 24
Peak memory 196992 kb
Host smart-edeb7941-9f54-45e7-b4af-c24a0f68fd58
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=302029245 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 19.gpio_smoke_en_cdc_prim.302029245
Directory /workspace/19.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/19.gpio_smoke_no_pullup_pulldown_en_cdc_prim.410731246
Short name T880
Test name
Test status
Simulation time 592243955 ps
CPU time 0.94 seconds
Started Jul 01 10:38:46 AM PDT 24
Finished Jul 01 10:38:48 AM PDT 24
Peak memory 196884 kb
Host smart-bd48e5b9-71a5-4d36-a59d-88236926738b
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=410731246 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 19.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.410731246
Directory /workspace/19.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/2.gpio_smoke_en_cdc_prim.2164140573
Short name T888
Test name
Test status
Simulation time 267952133 ps
CPU time 1.28 seconds
Started Jul 01 10:38:42 AM PDT 24
Finished Jul 01 10:38:44 AM PDT 24
Peak memory 197024 kb
Host smart-ad4b24fa-3d25-4b7e-bc2b-deafe759575d
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2164140573 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 2.gpio_smoke_en_cdc_prim.2164140573
Directory /workspace/2.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/2.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1279939262
Short name T870
Test name
Test status
Simulation time 32662593 ps
CPU time 0.81 seconds
Started Jul 01 10:38:43 AM PDT 24
Finished Jul 01 10:38:46 AM PDT 24
Peak memory 195752 kb
Host smart-e704bbfa-4e24-4c60-831c-1a978485118a
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1279939262 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 2.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.1279939262
Directory /workspace/2.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/20.gpio_smoke_en_cdc_prim.1634008785
Short name T900
Test name
Test status
Simulation time 37747714 ps
CPU time 0.75 seconds
Started Jul 01 10:38:53 AM PDT 24
Finished Jul 01 10:38:55 AM PDT 24
Peak memory 195752 kb
Host smart-e2e83bbb-ea6b-430c-b959-6c50561218b4
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1634008785 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 20.gpio_smoke_en_cdc_prim.1634008785
Directory /workspace/20.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/20.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2687467520
Short name T860
Test name
Test status
Simulation time 106173479 ps
CPU time 0.98 seconds
Started Jul 01 10:38:50 AM PDT 24
Finished Jul 01 10:38:53 AM PDT 24
Peak memory 195972 kb
Host smart-ed932d8b-b459-41b8-8dce-986b54c414c0
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2687467520 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 20.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2687467520
Directory /workspace/20.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/21.gpio_smoke_en_cdc_prim.1891477445
Short name T878
Test name
Test status
Simulation time 172012686 ps
CPU time 1.17 seconds
Started Jul 01 10:38:48 AM PDT 24
Finished Jul 01 10:38:50 AM PDT 24
Peak memory 197096 kb
Host smart-03be80fc-746b-45ce-aae9-0a6ad1c208b6
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1891477445 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 21.gpio_smoke_en_cdc_prim.1891477445
Directory /workspace/21.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/21.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2450588224
Short name T899
Test name
Test status
Simulation time 214824738 ps
CPU time 0.99 seconds
Started Jul 01 10:39:18 AM PDT 24
Finished Jul 01 10:39:21 AM PDT 24
Peak memory 196828 kb
Host smart-63f6158c-65b1-4938-85a5-14c68e211e43
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2450588224 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 21.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2450588224
Directory /workspace/21.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/22.gpio_smoke_en_cdc_prim.3505223926
Short name T852
Test name
Test status
Simulation time 49601667 ps
CPU time 1.01 seconds
Started Jul 01 10:39:04 AM PDT 24
Finished Jul 01 10:39:17 AM PDT 24
Peak memory 196928 kb
Host smart-77c1bc44-9432-4cd1-b612-b5f790df7e16
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3505223926 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 22.gpio_smoke_en_cdc_prim.3505223926
Directory /workspace/22.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/22.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3266451804
Short name T932
Test name
Test status
Simulation time 43158811 ps
CPU time 0.96 seconds
Started Jul 01 10:38:53 AM PDT 24
Finished Jul 01 10:38:55 AM PDT 24
Peak memory 196664 kb
Host smart-de563911-14e1-42c6-97ef-23dbd120a231
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3266451804 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 22.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3266451804
Directory /workspace/22.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/23.gpio_smoke_en_cdc_prim.3767716850
Short name T936
Test name
Test status
Simulation time 167992295 ps
CPU time 1.04 seconds
Started Jul 01 10:38:43 AM PDT 24
Finished Jul 01 10:38:46 AM PDT 24
Peak memory 196896 kb
Host smart-9f6c3e53-e33a-4ae6-a223-be84ca79886f
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3767716850 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 23.gpio_smoke_en_cdc_prim.3767716850
Directory /workspace/23.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/23.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3314012477
Short name T844
Test name
Test status
Simulation time 83386406 ps
CPU time 1.27 seconds
Started Jul 01 10:39:06 AM PDT 24
Finished Jul 01 10:39:10 AM PDT 24
Peak memory 196896 kb
Host smart-7176f903-1635-4aef-9d80-5d4491eab106
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3314012477 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 23.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3314012477
Directory /workspace/23.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/24.gpio_smoke_en_cdc_prim.1016824399
Short name T882
Test name
Test status
Simulation time 156077199 ps
CPU time 1.38 seconds
Started Jul 01 10:38:50 AM PDT 24
Finished Jul 01 10:38:54 AM PDT 24
Peak memory 198416 kb
Host smart-674add1b-16eb-40f3-95d5-a808f7a5f3c0
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1016824399 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 24.gpio_smoke_en_cdc_prim.1016824399
Directory /workspace/24.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/24.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1432385743
Short name T843
Test name
Test status
Simulation time 235010316 ps
CPU time 0.93 seconds
Started Jul 01 10:38:38 AM PDT 24
Finished Jul 01 10:38:40 AM PDT 24
Peak memory 196500 kb
Host smart-0e282afc-3883-4494-bcb5-72f1cd6ece41
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1432385743 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 24.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1432385743
Directory /workspace/24.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/25.gpio_smoke_en_cdc_prim.3960191748
Short name T871
Test name
Test status
Simulation time 35849313 ps
CPU time 0.76 seconds
Started Jul 01 10:38:49 AM PDT 24
Finished Jul 01 10:38:51 AM PDT 24
Peak memory 195668 kb
Host smart-a71f66e0-c4c7-49f7-a505-257ed37a0198
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3960191748 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 25.gpio_smoke_en_cdc_prim.3960191748
Directory /workspace/25.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/25.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1544260709
Short name T896
Test name
Test status
Simulation time 317952061 ps
CPU time 1.04 seconds
Started Jul 01 10:38:44 AM PDT 24
Finished Jul 01 10:38:46 AM PDT 24
Peak memory 196988 kb
Host smart-a2ab6dad-f28e-48a6-bcd7-5a559afcb4de
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1544260709 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 25.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1544260709
Directory /workspace/25.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/26.gpio_smoke_en_cdc_prim.3325599315
Short name T906
Test name
Test status
Simulation time 34944210 ps
CPU time 1.23 seconds
Started Jul 01 10:39:12 AM PDT 24
Finished Jul 01 10:39:14 AM PDT 24
Peak memory 198332 kb
Host smart-f243ed06-004c-4f13-a90f-3b792103efa6
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3325599315 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 26.gpio_smoke_en_cdc_prim.3325599315
Directory /workspace/26.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/26.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1532360684
Short name T872
Test name
Test status
Simulation time 29676936 ps
CPU time 0.88 seconds
Started Jul 01 10:38:50 AM PDT 24
Finished Jul 01 10:38:52 AM PDT 24
Peak memory 196740 kb
Host smart-5683f5e7-0249-4d33-8946-2906214945b3
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1532360684 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 26.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1532360684
Directory /workspace/26.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/27.gpio_smoke_en_cdc_prim.2921497398
Short name T868
Test name
Test status
Simulation time 60372804 ps
CPU time 0.86 seconds
Started Jul 01 10:38:51 AM PDT 24
Finished Jul 01 10:38:54 AM PDT 24
Peak memory 196576 kb
Host smart-1f8f9080-7a80-47f8-9070-fb562a47aa60
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2921497398 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 27.gpio_smoke_en_cdc_prim.2921497398
Directory /workspace/27.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/27.gpio_smoke_no_pullup_pulldown_en_cdc_prim.368974648
Short name T917
Test name
Test status
Simulation time 210668408 ps
CPU time 1.05 seconds
Started Jul 01 10:39:18 AM PDT 24
Finished Jul 01 10:39:19 AM PDT 24
Peak memory 196960 kb
Host smart-4f7c9a8a-b219-4156-8609-37275c2289e0
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=368974648 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 27.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.368974648
Directory /workspace/27.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/28.gpio_smoke_en_cdc_prim.1371436147
Short name T920
Test name
Test status
Simulation time 62042126 ps
CPU time 1.08 seconds
Started Jul 01 10:39:29 AM PDT 24
Finished Jul 01 10:39:31 AM PDT 24
Peak memory 196988 kb
Host smart-3ab15d8f-5b37-4948-b174-f04f4cea97ec
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1371436147 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 28.gpio_smoke_en_cdc_prim.1371436147
Directory /workspace/28.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/28.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3671934525
Short name T913
Test name
Test status
Simulation time 114091392 ps
CPU time 0.92 seconds
Started Jul 01 10:39:37 AM PDT 24
Finished Jul 01 10:39:42 AM PDT 24
Peak memory 195976 kb
Host smart-d41d41c5-cc40-423e-9b49-7928be03e153
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3671934525 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 28.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3671934525
Directory /workspace/28.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/29.gpio_smoke_en_cdc_prim.4175211167
Short name T907
Test name
Test status
Simulation time 51019296 ps
CPU time 1.08 seconds
Started Jul 01 10:38:53 AM PDT 24
Finished Jul 01 10:38:55 AM PDT 24
Peak memory 197020 kb
Host smart-8b654181-4dcc-4a69-82f4-a02738e7e277
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=4175211167 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 29.gpio_smoke_en_cdc_prim.4175211167
Directory /workspace/29.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/29.gpio_smoke_no_pullup_pulldown_en_cdc_prim.693244878
Short name T889
Test name
Test status
Simulation time 201960194 ps
CPU time 1.37 seconds
Started Jul 01 10:38:39 AM PDT 24
Finished Jul 01 10:38:42 AM PDT 24
Peak memory 196980 kb
Host smart-5b1b74f3-f4f3-4000-b17e-65987b5d603e
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=693244878 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 29.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.693244878
Directory /workspace/29.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/3.gpio_smoke_en_cdc_prim.2532658763
Short name T929
Test name
Test status
Simulation time 283657235 ps
CPU time 1.25 seconds
Started Jul 01 10:38:32 AM PDT 24
Finished Jul 01 10:38:34 AM PDT 24
Peak memory 197160 kb
Host smart-df52b40e-9d9e-4a8d-ab08-0b8086d76791
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2532658763 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 3.gpio_smoke_en_cdc_prim.2532658763
Directory /workspace/3.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/3.gpio_smoke_no_pullup_pulldown_en_cdc_prim.403757703
Short name T839
Test name
Test status
Simulation time 302219515 ps
CPU time 1.49 seconds
Started Jul 01 10:38:44 AM PDT 24
Finished Jul 01 10:38:47 AM PDT 24
Peak memory 197016 kb
Host smart-9f9b31e7-66e4-4de9-ac40-abbcefd7eae3
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=403757703 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 3.gpio_smoke_no_pullup_pulldown_e
n_cdc_prim.403757703
Directory /workspace/3.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/30.gpio_smoke_en_cdc_prim.1609493341
Short name T904
Test name
Test status
Simulation time 34368325 ps
CPU time 1.08 seconds
Started Jul 01 10:38:53 AM PDT 24
Finished Jul 01 10:38:55 AM PDT 24
Peak memory 196844 kb
Host smart-340217e4-5a23-430e-b10e-996e5ea2fdb4
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1609493341 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 30.gpio_smoke_en_cdc_prim.1609493341
Directory /workspace/30.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/30.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3875166536
Short name T867
Test name
Test status
Simulation time 81692298 ps
CPU time 0.96 seconds
Started Jul 01 10:39:27 AM PDT 24
Finished Jul 01 10:39:29 AM PDT 24
Peak memory 198336 kb
Host smart-790000fd-b6c3-45e6-8aa2-478f014daecf
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3875166536 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 30.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3875166536
Directory /workspace/30.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/31.gpio_smoke_en_cdc_prim.1067825675
Short name T925
Test name
Test status
Simulation time 75103229 ps
CPU time 1.35 seconds
Started Jul 01 10:38:43 AM PDT 24
Finished Jul 01 10:38:45 AM PDT 24
Peak memory 197212 kb
Host smart-abe957e5-40f0-4134-a802-37e99c8f56a2
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1067825675 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 31.gpio_smoke_en_cdc_prim.1067825675
Directory /workspace/31.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/31.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1305787627
Short name T881
Test name
Test status
Simulation time 201670120 ps
CPU time 1.21 seconds
Started Jul 01 10:39:13 AM PDT 24
Finished Jul 01 10:39:16 AM PDT 24
Peak memory 198360 kb
Host smart-a54a7b04-0314-4635-b68c-f001ed363dec
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1305787627 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 31.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1305787627
Directory /workspace/31.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/32.gpio_smoke_en_cdc_prim.304159069
Short name T933
Test name
Test status
Simulation time 27989595 ps
CPU time 0.95 seconds
Started Jul 01 10:39:07 AM PDT 24
Finished Jul 01 10:39:10 AM PDT 24
Peak memory 197000 kb
Host smart-b49c5872-fc0f-4697-87d4-a9d89bf56103
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=304159069 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 32.gpio_smoke_en_cdc_prim.304159069
Directory /workspace/32.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/32.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4287763761
Short name T853
Test name
Test status
Simulation time 40351102 ps
CPU time 0.83 seconds
Started Jul 01 10:38:50 AM PDT 24
Finished Jul 01 10:38:52 AM PDT 24
Peak memory 195680 kb
Host smart-14c3fc57-c6d9-4a10-82b4-874e9c66f34d
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4287763761 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 32.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.4287763761
Directory /workspace/32.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/33.gpio_smoke_en_cdc_prim.1110518258
Short name T855
Test name
Test status
Simulation time 280339684 ps
CPU time 1.18 seconds
Started Jul 01 10:39:34 AM PDT 24
Finished Jul 01 10:39:38 AM PDT 24
Peak memory 196332 kb
Host smart-520af06a-53ad-429d-a61a-4881dcdb2a89
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1110518258 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 33.gpio_smoke_en_cdc_prim.1110518258
Directory /workspace/33.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/33.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3888140245
Short name T898
Test name
Test status
Simulation time 232035259 ps
CPU time 1.08 seconds
Started Jul 01 10:38:50 AM PDT 24
Finished Jul 01 10:38:52 AM PDT 24
Peak memory 198340 kb
Host smart-8477ce16-a3ab-4963-92b4-f67ce25d7efc
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3888140245 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 33.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3888140245
Directory /workspace/33.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/34.gpio_smoke_en_cdc_prim.2604407001
Short name T875
Test name
Test status
Simulation time 31130713 ps
CPU time 0.88 seconds
Started Jul 01 10:38:41 AM PDT 24
Finished Jul 01 10:38:43 AM PDT 24
Peak memory 196856 kb
Host smart-8e794a10-9737-47e8-9020-ee01cef92b36
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2604407001 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 34.gpio_smoke_en_cdc_prim.2604407001
Directory /workspace/34.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/34.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2803982689
Short name T869
Test name
Test status
Simulation time 128951539 ps
CPU time 1.02 seconds
Started Jul 01 10:38:50 AM PDT 24
Finished Jul 01 10:38:53 AM PDT 24
Peak memory 197148 kb
Host smart-62d4940f-a73b-40cb-b5ee-e3053846b793
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2803982689 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 34.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2803982689
Directory /workspace/34.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/35.gpio_smoke_en_cdc_prim.3002796428
Short name T921
Test name
Test status
Simulation time 203602691 ps
CPU time 1.19 seconds
Started Jul 01 10:38:43 AM PDT 24
Finished Jul 01 10:38:45 AM PDT 24
Peak memory 198056 kb
Host smart-7c876cf1-5eea-4386-9496-a42bfebc0e41
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3002796428 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 35.gpio_smoke_en_cdc_prim.3002796428
Directory /workspace/35.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/35.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1872890338
Short name T924
Test name
Test status
Simulation time 53075747 ps
CPU time 0.97 seconds
Started Jul 01 10:38:53 AM PDT 24
Finished Jul 01 10:38:55 AM PDT 24
Peak memory 195980 kb
Host smart-48e4a11b-d49f-4d1f-95ab-e26a1bf91423
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1872890338 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 35.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1872890338
Directory /workspace/35.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/36.gpio_smoke_en_cdc_prim.847837905
Short name T857
Test name
Test status
Simulation time 385038876 ps
CPU time 1.39 seconds
Started Jul 01 10:38:49 AM PDT 24
Finished Jul 01 10:38:51 AM PDT 24
Peak memory 197032 kb
Host smart-bbbaa816-5391-426c-bbd5-7d49ed3b4543
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=847837905 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 36.gpio_smoke_en_cdc_prim.847837905
Directory /workspace/36.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/36.gpio_smoke_no_pullup_pulldown_en_cdc_prim.466449167
Short name T893
Test name
Test status
Simulation time 255765591 ps
CPU time 1.13 seconds
Started Jul 01 10:38:53 AM PDT 24
Finished Jul 01 10:38:56 AM PDT 24
Peak memory 197000 kb
Host smart-c3063cc9-31df-4374-b4e4-a8d74650a34c
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=466449167 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 36.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.466449167
Directory /workspace/36.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/37.gpio_smoke_en_cdc_prim.3695744146
Short name T841
Test name
Test status
Simulation time 38479403 ps
CPU time 1.08 seconds
Started Jul 01 10:38:47 AM PDT 24
Finished Jul 01 10:38:49 AM PDT 24
Peak memory 196968 kb
Host smart-6a498483-86f6-4efa-9ddd-761917c01910
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3695744146 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 37.gpio_smoke_en_cdc_prim.3695744146
Directory /workspace/37.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/37.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1159396689
Short name T847
Test name
Test status
Simulation time 153755196 ps
CPU time 1.24 seconds
Started Jul 01 10:38:57 AM PDT 24
Finished Jul 01 10:38:59 AM PDT 24
Peak memory 198480 kb
Host smart-960f747f-0def-458c-ae33-cb2b4ce4cff0
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1159396689 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 37.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1159396689
Directory /workspace/37.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/38.gpio_smoke_en_cdc_prim.1685104036
Short name T937
Test name
Test status
Simulation time 41915515 ps
CPU time 0.98 seconds
Started Jul 01 10:39:03 AM PDT 24
Finished Jul 01 10:39:07 AM PDT 24
Peak memory 197080 kb
Host smart-be923594-5249-4847-bd54-35f2a7cb8db6
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1685104036 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 38.gpio_smoke_en_cdc_prim.1685104036
Directory /workspace/38.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/38.gpio_smoke_no_pullup_pulldown_en_cdc_prim.19423232
Short name T850
Test name
Test status
Simulation time 89578464 ps
CPU time 0.9 seconds
Started Jul 01 10:38:56 AM PDT 24
Finished Jul 01 10:38:57 AM PDT 24
Peak memory 195636 kb
Host smart-76d11dfe-0102-4f88-96c6-bf6c91e90213
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19423232 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 38.gpio_smoke_no_pullup_pulldown_e
n_cdc_prim.19423232
Directory /workspace/38.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/39.gpio_smoke_en_cdc_prim.1235849738
Short name T928
Test name
Test status
Simulation time 42100746 ps
CPU time 0.99 seconds
Started Jul 01 10:39:03 AM PDT 24
Finished Jul 01 10:39:07 AM PDT 24
Peak memory 195940 kb
Host smart-f11acdb4-56cc-4e4b-99d3-08b10df90a4e
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1235849738 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 39.gpio_smoke_en_cdc_prim.1235849738
Directory /workspace/39.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/39.gpio_smoke_no_pullup_pulldown_en_cdc_prim.627675100
Short name T934
Test name
Test status
Simulation time 67417808 ps
CPU time 1.29 seconds
Started Jul 01 10:38:40 AM PDT 24
Finished Jul 01 10:38:42 AM PDT 24
Peak memory 197124 kb
Host smart-7198884c-b76e-4618-8a34-c6c1fc89379f
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=627675100 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 39.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.627675100
Directory /workspace/39.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/4.gpio_smoke_en_cdc_prim.2892450690
Short name T930
Test name
Test status
Simulation time 118597351 ps
CPU time 1.09 seconds
Started Jul 01 10:38:49 AM PDT 24
Finished Jul 01 10:38:52 AM PDT 24
Peak memory 196740 kb
Host smart-9daf944e-0035-4686-af68-a2c2f12eeea5
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2892450690 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 4.gpio_smoke_en_cdc_prim.2892450690
Directory /workspace/4.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/4.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3807581628
Short name T902
Test name
Test status
Simulation time 96304305 ps
CPU time 1.06 seconds
Started Jul 01 10:39:34 AM PDT 24
Finished Jul 01 10:39:38 AM PDT 24
Peak memory 196828 kb
Host smart-d7983782-999e-4576-933e-53fddefa07b0
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3807581628 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 4.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.3807581628
Directory /workspace/4.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/40.gpio_smoke_en_cdc_prim.365837587
Short name T909
Test name
Test status
Simulation time 72395469 ps
CPU time 1.17 seconds
Started Jul 01 10:38:59 AM PDT 24
Finished Jul 01 10:39:01 AM PDT 24
Peak memory 198380 kb
Host smart-74b4c38e-f820-4980-9dcc-d4bb4236d539
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=365837587 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 40.gpio_smoke_en_cdc_prim.365837587
Directory /workspace/40.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/40.gpio_smoke_no_pullup_pulldown_en_cdc_prim.625159454
Short name T890
Test name
Test status
Simulation time 57397721 ps
CPU time 1.12 seconds
Started Jul 01 10:39:01 AM PDT 24
Finished Jul 01 10:39:03 AM PDT 24
Peak memory 198324 kb
Host smart-ad6e2775-b53e-4188-a336-3a4ad78c1560
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=625159454 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 40.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.625159454
Directory /workspace/40.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/41.gpio_smoke_en_cdc_prim.166991121
Short name T894
Test name
Test status
Simulation time 158637247 ps
CPU time 0.89 seconds
Started Jul 01 10:39:13 AM PDT 24
Finished Jul 01 10:39:16 AM PDT 24
Peak memory 196924 kb
Host smart-6cd8dc84-5ca6-4161-93f0-b924a2007604
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=166991121 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 41.gpio_smoke_en_cdc_prim.166991121
Directory /workspace/41.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/41.gpio_smoke_no_pullup_pulldown_en_cdc_prim.554254843
Short name T903
Test name
Test status
Simulation time 196233070 ps
CPU time 0.88 seconds
Started Jul 01 10:39:00 AM PDT 24
Finished Jul 01 10:39:01 AM PDT 24
Peak memory 196620 kb
Host smart-2115b2d4-2298-45c9-96f5-ba18fb8f2b56
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=554254843 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 41.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.554254843
Directory /workspace/41.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/42.gpio_smoke_en_cdc_prim.3042131827
Short name T887
Test name
Test status
Simulation time 499500625 ps
CPU time 0.93 seconds
Started Jul 01 10:38:41 AM PDT 24
Finished Jul 01 10:38:43 AM PDT 24
Peak memory 195880 kb
Host smart-87384840-58a3-4dcd-a042-29f020b75b5c
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3042131827 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 42.gpio_smoke_en_cdc_prim.3042131827
Directory /workspace/42.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/42.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3440841187
Short name T885
Test name
Test status
Simulation time 213703639 ps
CPU time 1.23 seconds
Started Jul 01 10:38:37 AM PDT 24
Finished Jul 01 10:38:40 AM PDT 24
Peak memory 197376 kb
Host smart-18ea7d22-d280-4ae6-848e-03040d36d9a3
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3440841187 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 42.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3440841187
Directory /workspace/42.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/43.gpio_smoke_en_cdc_prim.2477664084
Short name T922
Test name
Test status
Simulation time 123673596 ps
CPU time 0.8 seconds
Started Jul 01 10:38:43 AM PDT 24
Finished Jul 01 10:38:46 AM PDT 24
Peak memory 195784 kb
Host smart-49bfb056-9068-41d1-8f2d-e5898c049b2c
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2477664084 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 43.gpio_smoke_en_cdc_prim.2477664084
Directory /workspace/43.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/43.gpio_smoke_no_pullup_pulldown_en_cdc_prim.338427648
Short name T938
Test name
Test status
Simulation time 67368137 ps
CPU time 1.1 seconds
Started Jul 01 10:39:07 AM PDT 24
Finished Jul 01 10:39:11 AM PDT 24
Peak memory 196972 kb
Host smart-6201dfa3-a358-43b0-8e49-04f94df1127f
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=338427648 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 43.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.338427648
Directory /workspace/43.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/44.gpio_smoke_en_cdc_prim.428375725
Short name T842
Test name
Test status
Simulation time 211188417 ps
CPU time 0.81 seconds
Started Jul 01 10:39:16 AM PDT 24
Finished Jul 01 10:39:18 AM PDT 24
Peak memory 195616 kb
Host smart-1edfffee-7ffa-41de-b739-18f3238d1971
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=428375725 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 44.gpio_smoke_en_cdc_prim.428375725
Directory /workspace/44.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/44.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1095382681
Short name T912
Test name
Test status
Simulation time 31323507 ps
CPU time 0.98 seconds
Started Jul 01 10:39:32 AM PDT 24
Finished Jul 01 10:39:42 AM PDT 24
Peak memory 196920 kb
Host smart-d212bebe-bb92-424f-8a9f-834d45b496b5
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1095382681 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 44.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1095382681
Directory /workspace/44.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/45.gpio_smoke_en_cdc_prim.1851697670
Short name T858
Test name
Test status
Simulation time 129449535 ps
CPU time 1.21 seconds
Started Jul 01 10:39:03 AM PDT 24
Finished Jul 01 10:39:07 AM PDT 24
Peak memory 196972 kb
Host smart-8249428b-9f3f-4940-a70d-6c57b59b8465
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1851697670 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 45.gpio_smoke_en_cdc_prim.1851697670
Directory /workspace/45.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/45.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2843083549
Short name T876
Test name
Test status
Simulation time 47470503 ps
CPU time 0.82 seconds
Started Jul 01 10:39:03 AM PDT 24
Finished Jul 01 10:39:07 AM PDT 24
Peak memory 195732 kb
Host smart-d8b0fb87-282d-4131-9d12-2f95ba4cdbaa
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2843083549 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 45.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2843083549
Directory /workspace/45.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/46.gpio_smoke_en_cdc_prim.556406705
Short name T914
Test name
Test status
Simulation time 416944900 ps
CPU time 1.46 seconds
Started Jul 01 10:39:32 AM PDT 24
Finished Jul 01 10:39:35 AM PDT 24
Peak memory 196908 kb
Host smart-b7fe7f88-e4b7-49c3-b696-48d854a361b0
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=556406705 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 46.gpio_smoke_en_cdc_prim.556406705
Directory /workspace/46.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/46.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3203262244
Short name T918
Test name
Test status
Simulation time 97227955 ps
CPU time 0.99 seconds
Started Jul 01 10:38:51 AM PDT 24
Finished Jul 01 10:38:54 AM PDT 24
Peak memory 196692 kb
Host smart-45cf5eca-78f4-4329-a4bf-e8a1564abd2b
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3203262244 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 46.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3203262244
Directory /workspace/46.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/47.gpio_smoke_en_cdc_prim.1664428390
Short name T910
Test name
Test status
Simulation time 73687956 ps
CPU time 0.98 seconds
Started Jul 01 10:38:58 AM PDT 24
Finished Jul 01 10:38:59 AM PDT 24
Peak memory 197100 kb
Host smart-62f91011-3254-4001-98a1-fd1177e8cb6d
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1664428390 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 47.gpio_smoke_en_cdc_prim.1664428390
Directory /workspace/47.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/47.gpio_smoke_no_pullup_pulldown_en_cdc_prim.658205673
Short name T866
Test name
Test status
Simulation time 195176845 ps
CPU time 0.99 seconds
Started Jul 01 10:38:51 AM PDT 24
Finished Jul 01 10:38:54 AM PDT 24
Peak memory 196992 kb
Host smart-7f2c98cd-b0ef-4c64-8f7b-367597350bc8
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=658205673 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 47.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.658205673
Directory /workspace/47.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/48.gpio_smoke_en_cdc_prim.417710457
Short name T911
Test name
Test status
Simulation time 66921959 ps
CPU time 1.31 seconds
Started Jul 01 10:38:53 AM PDT 24
Finished Jul 01 10:38:55 AM PDT 24
Peak memory 196848 kb
Host smart-4c9aace0-345e-4365-ae3f-15bba4b0ca68
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=417710457 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 48.gpio_smoke_en_cdc_prim.417710457
Directory /workspace/48.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/48.gpio_smoke_no_pullup_pulldown_en_cdc_prim.376186847
Short name T901
Test name
Test status
Simulation time 48459983 ps
CPU time 1.21 seconds
Started Jul 01 10:38:59 AM PDT 24
Finished Jul 01 10:39:01 AM PDT 24
Peak memory 198384 kb
Host smart-ff4b6dd6-a293-4af0-ba62-877784ed0ee2
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=376186847 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 48.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.376186847
Directory /workspace/48.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/49.gpio_smoke_en_cdc_prim.4271417044
Short name T931
Test name
Test status
Simulation time 152880656 ps
CPU time 0.94 seconds
Started Jul 01 10:38:59 AM PDT 24
Finished Jul 01 10:39:00 AM PDT 24
Peak memory 196808 kb
Host smart-adfcd83b-a8dc-4d2e-9164-878508c72ebd
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=4271417044 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 49.gpio_smoke_en_cdc_prim.4271417044
Directory /workspace/49.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/49.gpio_smoke_no_pullup_pulldown_en_cdc_prim.493248224
Short name T859
Test name
Test status
Simulation time 195898413 ps
CPU time 1.08 seconds
Started Jul 01 10:39:07 AM PDT 24
Finished Jul 01 10:39:11 AM PDT 24
Peak memory 196324 kb
Host smart-3cc69390-48e8-40ee-8628-7fa08c677cb6
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=493248224 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 49.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.493248224
Directory /workspace/49.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/5.gpio_smoke_en_cdc_prim.1235534142
Short name T884
Test name
Test status
Simulation time 174562396 ps
CPU time 1.21 seconds
Started Jul 01 10:38:49 AM PDT 24
Finished Jul 01 10:38:51 AM PDT 24
Peak memory 196880 kb
Host smart-0ab3a90a-21f3-42d6-926c-c46ed4a3032e
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1235534142 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 5.gpio_smoke_en_cdc_prim.1235534142
Directory /workspace/5.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/5.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1045430999
Short name T862
Test name
Test status
Simulation time 38492111 ps
CPU time 0.73 seconds
Started Jul 01 10:38:47 AM PDT 24
Finished Jul 01 10:38:49 AM PDT 24
Peak memory 196376 kb
Host smart-8375b522-0b7c-4d59-9e91-4d90c29cda17
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1045430999 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 5.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.1045430999
Directory /workspace/5.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/6.gpio_smoke_en_cdc_prim.377413186
Short name T851
Test name
Test status
Simulation time 165758943 ps
CPU time 1.25 seconds
Started Jul 01 10:38:38 AM PDT 24
Finished Jul 01 10:38:41 AM PDT 24
Peak memory 197304 kb
Host smart-d95ff292-f533-4b50-99c5-e1c9825f133d
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=377413186 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 6.gpio_smoke_en_cdc_prim.377413186
Directory /workspace/6.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/6.gpio_smoke_no_pullup_pulldown_en_cdc_prim.385866249
Short name T879
Test name
Test status
Simulation time 69118752 ps
CPU time 1.06 seconds
Started Jul 01 10:38:49 AM PDT 24
Finished Jul 01 10:38:51 AM PDT 24
Peak memory 196948 kb
Host smart-a52a4ccf-33b7-4a25-878c-a0c0892dcfc3
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=385866249 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 6.gpio_smoke_no_pullup_pulldown_e
n_cdc_prim.385866249
Directory /workspace/6.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/7.gpio_smoke_en_cdc_prim.1352483258
Short name T883
Test name
Test status
Simulation time 291014656 ps
CPU time 1.43 seconds
Started Jul 01 10:38:33 AM PDT 24
Finished Jul 01 10:38:36 AM PDT 24
Peak memory 196748 kb
Host smart-cb3a3573-b106-4e86-a552-44ff5dc2639f
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1352483258 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 7.gpio_smoke_en_cdc_prim.1352483258
Directory /workspace/7.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/7.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1304734617
Short name T919
Test name
Test status
Simulation time 1100908306 ps
CPU time 1.21 seconds
Started Jul 01 10:39:27 AM PDT 24
Finished Jul 01 10:39:29 AM PDT 24
Peak memory 196168 kb
Host smart-2bf63234-0b62-4e33-accf-b88f2508710d
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1304734617 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 7.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.1304734617
Directory /workspace/7.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/8.gpio_smoke_en_cdc_prim.1578015929
Short name T891
Test name
Test status
Simulation time 165851234 ps
CPU time 1.42 seconds
Started Jul 01 10:38:52 AM PDT 24
Finished Jul 01 10:38:55 AM PDT 24
Peak memory 196964 kb
Host smart-78ff48a8-07f7-43f5-b6b1-ee7357623a2b
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1578015929 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 8.gpio_smoke_en_cdc_prim.1578015929
Directory /workspace/8.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/8.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1915176373
Short name T908
Test name
Test status
Simulation time 29990772 ps
CPU time 1.05 seconds
Started Jul 01 10:38:52 AM PDT 24
Finished Jul 01 10:38:54 AM PDT 24
Peak memory 196840 kb
Host smart-83f60f8a-45c7-499c-86a0-4136be426459
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1915176373 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 8.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.1915176373
Directory /workspace/8.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/9.gpio_smoke_en_cdc_prim.4011956574
Short name T864
Test name
Test status
Simulation time 87486682 ps
CPU time 0.73 seconds
Started Jul 01 10:38:42 AM PDT 24
Finished Jul 01 10:38:44 AM PDT 24
Peak memory 196468 kb
Host smart-9038a3b0-59d9-402d-a581-ede1b0916e28
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=4011956574 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 9.gpio_smoke_en_cdc_prim.4011956574
Directory /workspace/9.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/9.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1515056860
Short name T861
Test name
Test status
Simulation time 187351869 ps
CPU time 1.37 seconds
Started Jul 01 10:38:39 AM PDT 24
Finished Jul 01 10:38:42 AM PDT 24
Peak memory 196020 kb
Host smart-e1c8ed70-923c-4c8e-b2ab-fb25e7ab2646
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1515056860 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 9.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.1515056860
Directory /workspace/9.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%