Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	36	0	36	100.00
Crosses	128	0	128	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	32	0	32	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	128	0	128	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	32	0	32	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	5683354	1			T22	24		T23	35856		T24	78
all_pins[1]	5683354	1			T22	24		T23	35856		T24	78
all_pins[2]	5683354	1			T22	24		T23	35856		T24	78
all_pins[3]	5683354	1			T22	24		T23	35856		T24	78
all_pins[4]	5683354	1			T22	24		T23	35856		T24	78
all_pins[5]	5683354	1			T22	24		T23	35856		T24	78
all_pins[6]	5683354	1			T22	24		T23	35856		T24	78
all_pins[7]	5683354	1			T22	24		T23	35856		T24	78
all_pins[8]	5683354	1			T22	24		T23	35856		T24	78
all_pins[9]	5683354	1			T22	24		T23	35856		T24	78
all_pins[10]	5683354	1			T22	24		T23	35856		T24	78
all_pins[11]	5683354	1			T22	24		T23	35856		T24	78
all_pins[12]	5683354	1			T22	24		T23	35856		T24	78
all_pins[13]	5683354	1			T22	24		T23	35856		T24	78
all_pins[14]	5683354	1			T22	24		T23	35856		T24	78
all_pins[15]	5683354	1			T22	24		T23	35856		T24	78
all_pins[16]	5683354	1			T22	24		T23	35856		T24	78
all_pins[17]	5683354	1			T22	24		T23	35856		T24	78
all_pins[18]	5683354	1			T22	24		T23	35856		T24	78
all_pins[19]	5683354	1			T22	24		T23	35856		T24	78
all_pins[20]	5683354	1			T22	24		T23	35856		T24	78
all_pins[21]	5683354	1			T22	24		T23	35856		T24	78
all_pins[22]	5683354	1			T22	24		T23	35856		T24	78
all_pins[23]	5683354	1			T22	24		T23	35856		T24	78
all_pins[24]	5683354	1			T22	24		T23	35856		T24	78
all_pins[25]	5683354	1			T22	24		T23	35856		T24	78
all_pins[26]	5683354	1			T22	24		T23	35856		T24	78
all_pins[27]	5683354	1			T22	24		T23	35856		T24	78
all_pins[28]	5683354	1			T22	24		T23	35856		T24	78
all_pins[29]	5683354	1			T22	24		T23	35856		T24	78
all_pins[30]	5683354	1			T22	24		T23	35856		T24	78
all_pins[31]	5683354	1			T22	24		T23	35856		T24	78

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	112989052	1			T22	679		T23	715860		T24	1651
values[0x1]	68878276	1			T22	89		T23	431532		T24	845
transitions[0x0=>0x1]	41304643	1			T22	64		T23	259199		T24	508
transitions[0x1=>0x0]	41304483	1			T22	64		T23	259198		T24	507

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	3530763	1			T22	17		T23	22245		T24	62
all_pins[0]	values[0x1]	2152591	1			T22	7		T23	13611		T24	16
all_pins[0]	transitions[0x0=>0x1]	1333652	1			T22	7		T23	8542		T24	9
all_pins[0]	transitions[0x1=>0x0]	1337031	1			T23	7945		T24	15		T25	31
all_pins[1]	values[0x0]	3535356	1			T22	24		T23	22591		T24	59
all_pins[1]	values[0x1]	2147998	1			T23	13265		T24	19		T25	60
all_pins[1]	transitions[0x0=>0x1]	1287663	1			T23	8135		T24	13		T25	28
all_pins[1]	transitions[0x1=>0x0]	1292256	1			T22	7		T23	8481		T24	10
all_pins[2]	values[0x0]	3532114	1			T22	24		T23	22677		T24	59
all_pins[2]	values[0x1]	2151240	1			T23	13179		T24	19		T25	64
all_pins[2]	transitions[0x0=>0x1]	1289025	1			T23	7978		T24	13		T25	31
all_pins[2]	transitions[0x1=>0x0]	1285783	1			T23	8064		T24	13		T25	27
all_pins[3]	values[0x0]	3527030	1			T22	16		T23	22014		T24	50
all_pins[3]	values[0x1]	2156324	1			T22	8		T23	13842		T24	28
all_pins[3]	transitions[0x0=>0x1]	1291197	1			T22	8		T23	8479		T24	19
all_pins[3]	transitions[0x1=>0x0]	1286113	1			T23	7816		T24	10		T25	43
all_pins[4]	values[0x0]	3521870	1			T22	20		T23	22155		T24	47
all_pins[4]	values[0x1]	2161484	1			T22	4		T23	13701		T24	31
all_pins[4]	transitions[0x0=>0x1]	1293790	1			T23	8117		T24	21		T25	36
all_pins[4]	transitions[0x1=>0x0]	1288630	1			T22	4		T23	8258		T24	18
all_pins[5]	values[0x0]	3527271	1			T22	15		T23	21886		T24	61
all_pins[5]	values[0x1]	2156083	1			T22	9		T23	13970		T24	17
all_pins[5]	transitions[0x0=>0x1]	1289427	1			T22	5		T23	8229		T24	8
all_pins[5]	transitions[0x1=>0x0]	1294828	1			T23	7960		T24	22		T25	27
all_pins[6]	values[0x0]	3533242	1			T22	23		T23	22700		T24	58
all_pins[6]	values[0x1]	2150112	1			T22	1		T23	13156		T24	20
all_pins[6]	transitions[0x0=>0x1]	1287436	1			T23	7792		T24	13		T25	30
all_pins[6]	transitions[0x1=>0x0]	1293407	1			T22	8		T23	8606		T24	10
all_pins[7]	values[0x0]	3536284	1			T22	24		T23	22331		T24	43
all_pins[7]	values[0x1]	2147070	1			T23	13525		T24	35		T25	57
all_pins[7]	transitions[0x0=>0x1]	1287947	1			T23	8320		T24	22		T25	32
all_pins[7]	transitions[0x1=>0x0]	1290989	1			T22	1		T23	7951		T24	7
all_pins[8]	values[0x0]	3527049	1			T22	23		T23	22455		T24	63
all_pins[8]	values[0x1]	2156305	1			T22	1		T23	13401		T24	15
all_pins[8]	transitions[0x0=>0x1]	1293546	1			T22	1		T23	7819		T24	11
all_pins[8]	transitions[0x1=>0x0]	1284311	1			T23	7943		T24	31		T25	28
all_pins[9]	values[0x0]	3532886	1			T22	14		T23	22432		T24	59
all_pins[9]	values[0x1]	2150468	1			T22	10		T23	13424		T24	19
all_pins[9]	transitions[0x0=>0x1]	1288011	1			T22	9		T23	8019		T24	14
all_pins[9]	transitions[0x1=>0x0]	1293848	1			T23	7996		T24	10		T25	33
all_pins[10]	values[0x0]	3526170	1			T22	19		T23	22137		T24	52
all_pins[10]	values[0x1]	2157184	1			T22	5		T23	13719		T24	26
all_pins[10]	transitions[0x0=>0x1]	1291218	1			T22	1		T23	8246		T24	16
all_pins[10]	transitions[0x1=>0x0]	1284502	1			T22	6		T23	7951		T24	9
all_pins[11]	values[0x0]	3525625	1			T22	18		T23	22308		T24	54
all_pins[11]	values[0x1]	2157729	1			T22	6		T23	13548		T24	24
all_pins[11]	transitions[0x0=>0x1]	1292202	1			T22	1		T23	8159		T24	19
all_pins[11]	transitions[0x1=>0x0]	1291657	1			T23	8330		T24	21		T25	29
all_pins[12]	values[0x0]	3534809	1			T22	24		T23	22298		T24	54
all_pins[12]	values[0x1]	2148545	1			T23	13558		T24	24		T25	45
all_pins[12]	transitions[0x0=>0x1]	1285865	1			T23	8175		T24	15		T25	23
all_pins[12]	transitions[0x1=>0x0]	1295049	1			T22	6		T23	8165		T24	15
all_pins[13]	values[0x0]	3524041	1			T22	24		T23	22400		T24	25
all_pins[13]	values[0x1]	2159313	1			T23	13456		T24	53		T25	44
all_pins[13]	transitions[0x0=>0x1]	1292789	1			T23	7882		T24	34		T25	23
all_pins[13]	transitions[0x1=>0x0]	1282021	1			T23	7984		T24	5		T25	24
all_pins[14]	values[0x0]	3528943	1			T22	22		T23	22246		T24	41
all_pins[14]	values[0x1]	2154411	1			T22	2		T23	13610		T24	37
all_pins[14]	transitions[0x0=>0x1]	1288467	1			T22	2		T23	8109		T24	10
all_pins[14]	transitions[0x1=>0x0]	1293369	1			T23	7955		T24	26		T25	25
all_pins[15]	values[0x0]	3543389	1			T22	24		T23	22798		T24	46
all_pins[15]	values[0x1]	2139965	1			T23	13058		T24	32		T25	48
all_pins[15]	transitions[0x0=>0x1]	1279494	1			T23	7703		T24	13		T25	23
all_pins[15]	transitions[0x1=>0x0]	1293940	1			T22	2		T23	8255		T24	18
all_pins[16]	values[0x0]	3524725	1			T22	23		T23	22014		T24	43
all_pins[16]	values[0x1]	2158629	1			T22	1		T23	13842		T24	35
all_pins[16]	transitions[0x0=>0x1]	1298529	1			T22	1		T23	8519		T24	26
all_pins[16]	transitions[0x1=>0x0]	1279865	1			T23	7735		T24	23		T25	27
all_pins[17]	values[0x0]	3532707	1			T22	24		T23	22377		T24	34
all_pins[17]	values[0x1]	2150647	1			T23	13479		T24	44		T25	55
all_pins[17]	transitions[0x0=>0x1]	1286806	1			T23	7803		T24	18		T25	33
all_pins[17]	transitions[0x1=>0x0]	1294788	1			T22	1		T23	8166		T24	9
all_pins[18]	values[0x0]	3536626	1			T22	23		T23	22108		T24	43
all_pins[18]	values[0x1]	2146728	1			T22	1		T23	13748		T24	35
all_pins[18]	transitions[0x0=>0x1]	1284575	1			T22	1		T23	8066		T24	15
all_pins[18]	transitions[0x1=>0x0]	1288494	1			T23	7797		T24	24		T25	34
all_pins[19]	values[0x0]	3533453	1			T22	24		T23	22010		T24	53
all_pins[19]	values[0x1]	2149901	1			T23	13846		T24	25		T25	52
all_pins[19]	transitions[0x0=>0x1]	1289680	1			T23	8327		T24	10		T25	30
all_pins[19]	transitions[0x1=>0x0]	1286507	1			T22	1		T23	8229		T24	20
all_pins[20]	values[0x0]	3531784	1			T22	23		T23	22985		T24	54
all_pins[20]	values[0x1]	2151570	1			T22	1		T23	12871		T24	24
all_pins[20]	transitions[0x0=>0x1]	1291486	1			T22	1		T23	7606		T24	16
all_pins[20]	transitions[0x1=>0x0]	1289817	1			T23	8581		T24	17		T25	29
all_pins[21]	values[0x0]	3527397	1			T22	16		T23	22332		T24	29
all_pins[21]	values[0x1]	2155957	1			T22	8		T23	13524		T24	49
all_pins[21]	transitions[0x0=>0x1]	1292131	1			T22	8		T23	8434		T24	25
all_pins[21]	transitions[0x1=>0x0]	1287744	1			T22	1		T23	7781		T25	28
all_pins[22]	values[0x0]	3542697	1			T22	24		T23	22354		T24	65
all_pins[22]	values[0x1]	2140657	1			T23	13502		T24	13		T25	56
all_pins[22]	transitions[0x0=>0x1]	1281022	1			T23	8502		T24	4		T25	34
all_pins[22]	transitions[0x1=>0x0]	1296322	1			T22	8		T23	8524		T24	40
all_pins[23]	values[0x0]	3525641	1			T22	22		T23	22341		T24	57
all_pins[23]	values[0x1]	2157713	1			T22	2		T23	13515		T24	21
all_pins[23]	transitions[0x0=>0x1]	1296813	1			T22	2		T23	7895		T24	12
all_pins[23]	transitions[0x1=>0x0]	1279757	1			T23	7882		T24	4		T25	33
all_pins[24]	values[0x0]	3527413	1			T22	24		T23	22440		T24	52
all_pins[24]	values[0x1]	2155941	1			T23	13416		T24	26		T25	49
all_pins[24]	transitions[0x0=>0x1]	1289365	1			T23	8140		T24	21		T25	27
all_pins[24]	transitions[0x1=>0x0]	1291137	1			T22	2		T23	8239		T24	16
all_pins[25]	values[0x0]	3532111	1			T22	22		T23	22898		T24	71
all_pins[25]	values[0x1]	2151243	1			T22	2		T23	12958		T24	7
all_pins[25]	transitions[0x0=>0x1]	1287158	1			T22	2		T23	7847		T24	7
all_pins[25]	transitions[0x1=>0x0]	1291856	1			T23	8305		T24	26		T25	23
all_pins[26]	values[0x0]	3536720	1			T22	23		T23	22554		T24	50
all_pins[26]	values[0x1]	2146634	1			T22	1		T23	13302		T24	28
all_pins[26]	transitions[0x0=>0x1]	1286089	1			T23	8032		T24	28		T25	25
all_pins[26]	transitions[0x1=>0x0]	1290698	1			T22	1		T23	7688		T24	7
all_pins[27]	values[0x0]	3532283	1			T22	19		T23	22639		T24	56
all_pins[27]	values[0x1]	2151071	1			T22	5		T23	13217		T24	22
all_pins[27]	transitions[0x0=>0x1]	1289161	1			T22	5		T23	7876		T24	10
all_pins[27]	transitions[0x1=>0x0]	1284724	1			T22	1		T23	7961		T24	16
all_pins[28]	values[0x0]	3527503	1			T22	17		T23	21865		T24	62
all_pins[28]	values[0x1]	2155851	1			T22	7		T23	13991		T24	16
all_pins[28]	transitions[0x0=>0x1]	1289609	1			T22	2		T23	8472		T24	10
all_pins[28]	transitions[0x1=>0x0]	1284829	1			T23	7698		T24	16		T25	27
all_pins[29]	values[0x0]	3528730	1			T22	24		T23	22313		T24	47
all_pins[29]	values[0x1]	2154624	1			T23	13543		T24	31		T25	50
all_pins[29]	transitions[0x0=>0x1]	1289201	1			T23	8028		T24	29		T25	32
all_pins[29]	transitions[0x1=>0x0]	1290428	1			T22	7		T23	8476		T24	14
all_pins[30]	values[0x0]	3535196	1			T22	16		T23	22116		T24	47
all_pins[30]	values[0x1]	2148158	1			T22	8		T23	13740		T24	31
all_pins[30]	transitions[0x0=>0x1]	1288942	1			T22	8		T23	8368		T24	14
all_pins[30]	transitions[0x1=>0x0]	1295408	1			T23	8171		T24	14		T25	23
all_pins[31]	values[0x0]	3527224	1			T22	24		T23	22841		T24	55
all_pins[31]	values[0x1]	2156130	1			T23	13015		T24	23		T25	61
all_pins[31]	transitions[0x0=>0x1]	1292347	1			T23	7580		T24	13		T25	26
all_pins[31]	transitions[0x1=>0x0]	1284375	1			T22	8		T23	8305		T24	21