Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=31}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=31}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=31}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	192	0	192	100.00

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=31}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	32	0	32	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=31}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	192	0	192	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	32	0	32	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	18047375	1			T22	50		T23	99313		T24	146
all_values[1]	18047375	1			T22	50		T23	99313		T24	146
all_values[2]	18047375	1			T22	50		T23	99313		T24	146
all_values[3]	18047375	1			T22	50		T23	99313		T24	146
all_values[4]	18047375	1			T22	50		T23	99313		T24	146
all_values[5]	18047375	1			T22	50		T23	99313		T24	146
all_values[6]	18047375	1			T22	50		T23	99313		T24	146
all_values[7]	18047375	1			T22	50		T23	99313		T24	146
all_values[8]	18047375	1			T22	50		T23	99313		T24	146
all_values[9]	18047375	1			T22	50		T23	99313		T24	146
all_values[10]	18047375	1			T22	50		T23	99313		T24	146
all_values[11]	18047375	1			T22	50		T23	99313		T24	146
all_values[12]	18047375	1			T22	50		T23	99313		T24	146
all_values[13]	18047375	1			T22	50		T23	99313		T24	146
all_values[14]	18047375	1			T22	50		T23	99313		T24	146
all_values[15]	18047375	1			T22	50		T23	99313		T24	146
all_values[16]	18047375	1			T22	50		T23	99313		T24	146
all_values[17]	18047375	1			T22	50		T23	99313		T24	146
all_values[18]	18047375	1			T22	50		T23	99313		T24	146
all_values[19]	18047375	1			T22	50		T23	99313		T24	146
all_values[20]	18047375	1			T22	50		T23	99313		T24	146
all_values[21]	18047375	1			T22	50		T23	99313		T24	146
all_values[22]	18047375	1			T22	50		T23	99313		T24	146
all_values[23]	18047375	1			T22	50		T23	99313		T24	146
all_values[24]	18047375	1			T22	50		T23	99313		T24	146
all_values[25]	18047375	1			T22	50		T23	99313		T24	146
all_values[26]	18047375	1			T22	50		T23	99313		T24	146
all_values[27]	18047375	1			T22	50		T23	99313		T24	146
all_values[28]	18047375	1			T22	50		T23	99313		T24	146
all_values[29]	18047375	1			T22	50		T23	99313		T24	146
all_values[30]	18047375	1			T22	50		T23	99313		T24	146
all_values[31]	18047375	1			T22	50		T23	99313		T24	146

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

321500135

1

T22

1244

T23

174723

T24

2634

auto[1]

256015865

1

T22

356

T23

143077

T24

2038

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

114666115

1

T22

995

T23

605665

T24

861

auto[1]

462849885

1

T22

605

T23

257235

T24

3811

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

570912591

1

T22

1545

T23

314836

T24

4672

auto[1]

6603409

1

T22

55

T23

29655

T27

15

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	192	0	192	100.00
Automatically Generated Cross Bins	192	0	192	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	2804497	1			T22	23		T23	14686		T24	13
all_values[0]	auto[0]	auto[0]	auto[1]	7139248	1			T22	4		T23	38599		T24	97
all_values[0]	auto[0]	auto[1]	auto[0]	763597	1			T22	7		T23	4693		T24	6
all_values[0]	auto[0]	auto[1]	auto[1]	7133350	1			T22	16		T23	40420		T24	30
all_values[0]	auto[1]	auto[0]	auto[1]	103475	1			T23	482		T31	6		T1	34
all_values[0]	auto[1]	auto[1]	auto[1]	103208	1			T23	433		T31	3		T1	16
all_values[1]	auto[0]	auto[0]	auto[0]	2812484	1			T22	26		T23	14175		T24	18
all_values[1]	auto[0]	auto[0]	auto[1]	7163051	1			T22	19		T23	38540		T24	99
all_values[1]	auto[0]	auto[1]	auto[0]	781310	1			T22	4		T23	4905		T24	3
all_values[1]	auto[0]	auto[1]	auto[1]	7084492	1			T23	40765		T24	26		T26	682
all_values[1]	auto[1]	auto[0]	auto[1]	103442	1			T22	1		T23	463		T31	8
all_values[1]	auto[1]	auto[1]	auto[1]	102596	1			T23	465		T1	23		T115	3
all_values[2]	auto[0]	auto[0]	auto[0]	2809399	1			T22	27		T23	14647		T24	19
all_values[2]	auto[0]	auto[0]	auto[1]	7163540	1			T22	20		T23	41292		T24	57
all_values[2]	auto[0]	auto[1]	auto[0]	767005	1			T23	4407		T24	23		T26	124
all_values[2]	auto[0]	auto[1]	auto[1]	7101219	1			T23	38046		T24	47		T26	805
all_values[2]	auto[1]	auto[0]	auto[1]	103350	1			T22	3		T23	456		T27	1
all_values[2]	auto[1]	auto[1]	auto[1]	102862	1			T23	465		T31	1		T1	29
all_values[3]	auto[0]	auto[0]	auto[0]	2810326	1			T22	24		T23	14691		T24	9
all_values[3]	auto[0]	auto[0]	auto[1]	7132027	1			T22	3		T23	37659		T24	79
all_values[3]	auto[0]	auto[1]	auto[0]	772671	1			T22	3		T23	4440		T24	11
all_values[3]	auto[0]	auto[1]	auto[1]	7126226	1			T22	16		T23	41609		T24	47
all_values[3]	auto[1]	auto[0]	auto[1]	103593	1			T22	3		T23	477		T31	10
all_values[3]	auto[1]	auto[1]	auto[1]	102532	1			T22	1		T23	437		T31	1
all_values[4]	auto[0]	auto[0]	auto[0]	2807648	1			T22	26		T23	14163		T24	13
all_values[4]	auto[0]	auto[0]	auto[1]	7114267	1			T22	3		T23	38384		T24	60
all_values[4]	auto[0]	auto[1]	auto[0]	782180	1			T22	5		T23	4896		T24	10
all_values[4]	auto[0]	auto[1]	auto[1]	7137079	1			T22	14		T23	40935		T24	63
all_values[4]	auto[1]	auto[0]	auto[1]	103018	1			T22	2		T23	470		T31	8
all_values[4]	auto[1]	auto[1]	auto[1]	103183	1			T23	465		T31	6		T1	25
all_values[5]	auto[0]	auto[0]	auto[0]	2801353	1			T22	26		T23	13753		T24	21
all_values[5]	auto[0]	auto[0]	auto[1]	7110628	1			T23	38349		T24	74		T26	802
all_values[5]	auto[0]	auto[1]	auto[0]	783375	1			T22	5		T23	4493		T24	17
all_values[5]	auto[0]	auto[1]	auto[1]	7145568	1			T22	19		T23	41780		T24	34
all_values[5]	auto[1]	auto[0]	auto[1]	102971	1			T23	467		T31	8		T1	37
all_values[5]	auto[1]	auto[1]	auto[1]	103480	1			T23	471		T27	1		T31	4
all_values[6]	auto[0]	auto[0]	auto[0]	2814330	1			T22	26		T23	14016		T24	14
all_values[6]	auto[0]	auto[0]	auto[1]	7132736	1			T22	16		T23	41549		T24	78
all_values[6]	auto[0]	auto[1]	auto[0]	772123	1			T22	5		T23	4121		T24	13
all_values[6]	auto[0]	auto[1]	auto[1]	7121701	1			T22	1		T23	38719		T24	41
all_values[6]	auto[1]	auto[0]	auto[1]	103638	1			T22	1		T23	472		T31	10
all_values[6]	auto[1]	auto[1]	auto[1]	102847	1			T22	1		T23	436		T31	4
all_values[7]	auto[0]	auto[0]	auto[0]	2805569	1			T22	27		T23	14065		T24	11
all_values[7]	auto[0]	auto[0]	auto[1]	7172810	1			T22	18		T23	38987		T24	43
all_values[7]	auto[0]	auto[1]	auto[0]	780430	1			T22	3		T23	5213		T24	6
all_values[7]	auto[0]	auto[1]	auto[1]	7081792	1			T23	40110		T24	86		T26	710
all_values[7]	auto[1]	auto[0]	auto[1]	103689	1			T22	2		T23	487		T27	1
all_values[7]	auto[1]	auto[1]	auto[1]	103085	1			T23	451		T31	3		T1	36
all_values[8]	auto[0]	auto[0]	auto[0]	2809350	1			T22	28		T23	14081		T24	31
all_values[8]	auto[0]	auto[0]	auto[1]	7112625	1			T22	14		T23	42280		T24	88
all_values[8]	auto[0]	auto[1]	auto[0]	775443	1			T22	6		T23	4193		T24	3
all_values[8]	auto[0]	auto[1]	auto[1]	7143810	1			T23	37838		T24	24		T26	729
all_values[8]	auto[1]	auto[0]	auto[1]	103257	1			T22	1		T23	481		T27	1
all_values[8]	auto[1]	auto[1]	auto[1]	102890	1			T22	1		T23	440		T31	1
all_values[9]	auto[0]	auto[0]	auto[0]	2810056	1			T22	19		T23	13961		T24	14
all_values[9]	auto[0]	auto[0]	auto[1]	7108070	1			T22	3		T23	40888		T24	83
all_values[9]	auto[0]	auto[1]	auto[0]	777039	1			T22	6		T23	4865		T24	2
all_values[9]	auto[0]	auto[1]	auto[1]	7145999	1			T22	19		T23	38690		T24	47
all_values[9]	auto[1]	auto[0]	auto[1]	103258	1			T22	1		T23	427		T31	5
all_values[9]	auto[1]	auto[1]	auto[1]	102953	1			T22	2		T23	482		T31	3
all_values[10]	auto[0]	auto[0]	auto[0]	2807851	1			T22	28		T23	14227		T24	15
all_values[10]	auto[0]	auto[0]	auto[1]	7121893	1			T22	1		T23	39182		T24	63
all_values[10]	auto[0]	auto[1]	auto[0]	771774	1			T22	7		T23	4671		T24	10
all_values[10]	auto[0]	auto[1]	auto[1]	7139578	1			T22	13		T23	40317		T24	58
all_values[10]	auto[1]	auto[0]	auto[1]	103594	1			T22	1		T23	483		T27	1
all_values[10]	auto[1]	auto[1]	auto[1]	102685	1			T23	433		T31	3		T1	32
all_values[11]	auto[0]	auto[0]	auto[0]	2805984	1			T22	25		T23	13912		T24	17
all_values[11]	auto[0]	auto[0]	auto[1]	7111705	1			T22	3		T23	41234		T24	61
all_values[11]	auto[0]	auto[1]	auto[0]	774687	1			T22	6		T23	4528		T24	27
all_values[11]	auto[0]	auto[1]	auto[1]	7148194	1			T22	14		T23	38712		T24	41
all_values[11]	auto[1]	auto[0]	auto[1]	103629	1			T22	2		T23	479		T31	13
all_values[11]	auto[1]	auto[1]	auto[1]	103176	1			T23	448		T31	1		T1	23
all_values[12]	auto[0]	auto[0]	auto[0]	2812531	1			T22	24		T23	14437		T24	16
all_values[12]	auto[0]	auto[0]	auto[1]	7132309	1			T22	18		T23	39765		T24	45
all_values[12]	auto[0]	auto[1]	auto[0]	780784	1			T22	7		T23	4430		T24	20
all_values[12]	auto[0]	auto[1]	auto[1]	7114968	1			T23	39736		T24	65		T26	725
all_values[12]	auto[1]	auto[0]	auto[1]	104104	1			T22	1		T23	472		T27	1
all_values[12]	auto[1]	auto[1]	auto[1]	102679	1			T23	473		T31	2		T1	18
all_values[13]	auto[0]	auto[0]	auto[0]	2809624	1			T22	28		T23	14057		T24	9
all_values[13]	auto[0]	auto[0]	auto[1]	7123992	1			T22	20		T23	40144		T24	20
all_values[13]	auto[0]	auto[1]	auto[0]	778523	1			T23	5141		T24	7		T26	97
all_values[13]	auto[0]	auto[1]	auto[1]	7128281	1			T23	39044		T24	110		T26	1210
all_values[13]	auto[1]	auto[0]	auto[1]	103591	1			T22	2		T23	442		T31	8
all_values[13]	auto[1]	auto[1]	auto[1]	103364	1			T23	485		T27	1		T31	3
all_values[14]	auto[0]	auto[0]	auto[0]	2805768	1			T22	23		T23	13862		T24	11
all_values[14]	auto[0]	auto[0]	auto[1]	7131871	1			T22	19		T23	39265		T24	71
all_values[14]	auto[0]	auto[1]	auto[0]	788854	1			T22	4		T23	4684		T24	8
all_values[14]	auto[0]	auto[1]	auto[1]	7114562	1			T22	2		T23	40587		T24	56
all_values[14]	auto[1]	auto[0]	auto[1]	103127	1			T22	1		T23	484		T27	1
all_values[14]	auto[1]	auto[1]	auto[1]	103193	1			T22	1		T23	431		T31	3
all_values[15]	auto[0]	auto[0]	auto[0]	2811930	1			T22	29		T23	14316		T24	8
all_values[15]	auto[0]	auto[0]	auto[1]	7165859	1			T22	12		T23	40790		T24	69
all_values[15]	auto[0]	auto[1]	auto[0]	773097	1			T22	8		T23	4282		T24	10
all_values[15]	auto[0]	auto[1]	auto[1]	7089755	1			T23	38966		T24	59		T26	991
all_values[15]	auto[1]	auto[0]	auto[1]	103915	1			T22	1		T23	482		T27	1
all_values[15]	auto[1]	auto[1]	auto[1]	102819	1			T23	477		T31	3		T1	25
all_values[16]	auto[0]	auto[0]	auto[0]	2801925	1			T22	25		T23	14042		T24	13
all_values[16]	auto[0]	auto[0]	auto[1]	7140990	1			T22	14		T23	40618		T24	56
all_values[16]	auto[0]	auto[1]	auto[0]	776158	1			T22	10		T23	4659		T24	5
all_values[16]	auto[0]	auto[1]	auto[1]	7121716	1			T23	39068		T24	72		T26	716
all_values[16]	auto[1]	auto[0]	auto[1]	103217	1			T23	446		T31	8		T1	29
all_values[16]	auto[1]	auto[1]	auto[1]	103369	1			T22	1		T23	480		T1	29
all_values[17]	auto[0]	auto[0]	auto[0]	2812656	1			T22	26		T23	14297		T24	3
all_values[17]	auto[0]	auto[0]	auto[1]	7147792	1			T22	18		T23	40302		T24	36
all_values[17]	auto[0]	auto[1]	auto[0]	773305	1			T22	4		T23	4809		T24	10
all_values[17]	auto[0]	auto[1]	auto[1]	7106971	1			T23	38990		T24	97		T26	914
all_values[17]	auto[1]	auto[0]	auto[1]	104012	1			T22	2		T23	453		T27	1
all_values[17]	auto[1]	auto[1]	auto[1]	102639	1			T23	462		T31	3		T1	33
all_values[18]	auto[0]	auto[0]	auto[0]	2801843	1			T22	31		T23	13966		T24	4
all_values[18]	auto[0]	auto[0]	auto[1]	7160137	1			T22	13		T23	39745		T24	61
all_values[18]	auto[0]	auto[1]	auto[0]	772475	1			T22	3		T23	5018		T24	14
all_values[18]	auto[0]	auto[1]	auto[1]	7106254	1			T23	39647		T24	67		T26	729
all_values[18]	auto[1]	auto[0]	auto[1]	103619	1			T22	2		T23	466		T31	12
all_values[18]	auto[1]	auto[1]	auto[1]	103047	1			T22	1		T23	471		T31	4
all_values[19]	auto[0]	auto[0]	auto[0]	2804486	1			T22	32		T23	13909		T24	6
all_values[19]	auto[0]	auto[0]	auto[1]	7133279	1			T22	16		T23	40304		T24	89
all_values[19]	auto[0]	auto[1]	auto[0]	776315	1			T23	4557		T24	6		T26	80
all_values[19]	auto[0]	auto[1]	auto[1]	7126699	1			T23	39581		T24	45		T26	774
all_values[19]	auto[1]	auto[0]	auto[1]	103419	1			T22	2		T23	478		T27	1
all_values[19]	auto[1]	auto[1]	auto[1]	103177	1			T23	484		T31	5		T1	24
all_values[20]	auto[0]	auto[0]	auto[0]	2805364	1			T22	31		T23	14065		T24	9
all_values[20]	auto[0]	auto[0]	auto[1]	7151751	1			T22	15		T23	41116		T24	93
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all_values[31]	auto[0]	auto[0]	auto[1]	7079167	1			T22	14		T23	40981		T24	85
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User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal