Unified Coverage Report :: Group :: gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

Group : gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_gpio_env_0.1/gpio_env_cov.sv

---

Summary for Group gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	192	0	192	100.00

Variables for Group gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_pin	32	0	32	100.00	100	1	1	0
data_in	2	0	2	100.00	100	1	1	2
data_oe	2	0	2	100.00	100	1	1	2
data_out	2	0	2	100.00	100	1	1	2

Crosses for Group gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_cross_all	192	0	192	100.00	100	1	1	0

Summary for Variable cp_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	32	0	32	100.00

User Defined Bins for cp_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bins_for_gpio_bits[0]	17714095	1			T22	102		T23	93664		T24	81
bins_for_gpio_bits[1]	17714095	1			T22	102		T23	93664		T24	81
bins_for_gpio_bits[2]	17714095	1			T22	102		T23	93664		T24	81
bins_for_gpio_bits[3]	17714095	1			T22	102		T23	93664		T24	81
bins_for_gpio_bits[4]	17714095	1			T22	102		T23	93664		T24	81
bins_for_gpio_bits[5]	17714095	1			T22	102		T23	93664		T24	81
bins_for_gpio_bits[6]	17714095	1			T22	102		T23	93664		T24	81
bins_for_gpio_bits[7]	17714095	1			T22	102		T23	93664		T24	81
bins_for_gpio_bits[8]	17714095	1			T22	102		T23	93664		T24	81
bins_for_gpio_bits[9]	17714095	1			T22	102		T23	93664		T24	81
bins_for_gpio_bits[10]	17714095	1			T22	102		T23	93664		T24	81
bins_for_gpio_bits[11]	17714095	1			T22	102		T23	93664		T24	81
bins_for_gpio_bits[12]	17714095	1			T22	102		T23	93664		T24	81
bins_for_gpio_bits[13]	17714095	1			T22	102		T23	93664		T24	81
bins_for_gpio_bits[14]	17714095	1			T22	102		T23	93664		T24	81
bins_for_gpio_bits[15]	17714095	1			T22	102		T23	93664		T24	81
bins_for_gpio_bits[16]	17714095	1			T22	102		T23	93664		T24	81
bins_for_gpio_bits[17]	17714095	1			T22	102		T23	93664		T24	81
bins_for_gpio_bits[18]	17714095	1			T22	102		T23	93664		T24	81
bins_for_gpio_bits[19]	17714095	1			T22	102		T23	93664		T24	81
bins_for_gpio_bits[20]	17714095	1			T22	102		T23	93664		T24	81
bins_for_gpio_bits[21]	17714095	1			T22	102		T23	93664		T24	81
bins_for_gpio_bits[22]	17714095	1			T22	102		T23	93664		T24	81
bins_for_gpio_bits[23]	17714095	1			T22	102		T23	93664		T24	81
bins_for_gpio_bits[24]	17714095	1			T22	102		T23	93664		T24	81
bins_for_gpio_bits[25]	17714095	1			T22	102		T23	93664		T24	81
bins_for_gpio_bits[26]	17714095	1			T22	102		T23	93664		T24	81
bins_for_gpio_bits[27]	17714095	1			T22	102		T23	93664		T24	81
bins_for_gpio_bits[28]	17714095	1			T22	102		T23	93664		T24	81
bins_for_gpio_bits[29]	17714095	1			T22	102		T23	93664		T24	81
bins_for_gpio_bits[30]	17714095	1			T22	102		T23	93664		T24	81
bins_for_gpio_bits[31]	17714095	1			T22	102		T23	93664		T24	81

---

Summary for Variable data_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for data_in

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

341716680

1

T22

1616

T23

189339

T24

1336

auto[1]

225134360

1

T22

1648

T23

110385

T24

1256

---

Summary for Variable data_oe

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for data_oe

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

450671393

1

T22

2941

T23

239926

T24

2592

auto[1]

116179647

1

T22

323

T23

597984

T27

137

---

Summary for Variable data_out

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for data_out

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

416648681

1

T22

2424

T23

225823

T24

2592

auto[1]

150202359

1

T22

840

T23

739009

T27

233

---

Summary for Cross cp_cross_all

Samples crossed: cp_pin data_out data_oe data_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	192	0	192	100.00
Automatically Generated Cross Bins	192	0	192	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cp_cross_all

Bins

cp_pin	data_out	data_oe	data_in	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bins_for_gpio_bits[0]	auto[0]	auto[0]	auto[0]	6517413	1			T22	19		T23	36974		T24	28
bins_for_gpio_bits[0]	auto[0]	auto[0]	auto[1]	4678978	1			T22	48		T23	24440		T24	53
bins_for_gpio_bits[0]	auto[0]	auto[1]	auto[0]	1823754	1			T23	9145		T27	5		T28	25
bins_for_gpio_bits[0]	auto[1]	auto[0]	auto[0]	2334493	1			T22	5		T23	13055		T27	5
bins_for_gpio_bits[0]	auto[1]	auto[0]	auto[1]	549244	1			T22	18		T23	824		T28	3
bins_for_gpio_bits[0]	auto[1]	auto[1]	auto[1]	1810213	1			T22	12		T23	9226		T28	8
bins_for_gpio_bits[1]	auto[0]	auto[0]	auto[0]	6511749	1			T22	40		T23	36915		T24	40
bins_for_gpio_bits[1]	auto[0]	auto[0]	auto[1]	4672133	1			T22	14		T23	24164		T24	41
bins_for_gpio_bits[1]	auto[0]	auto[1]	auto[0]	1823455	1			T22	4		T23	9532		T28	28
bins_for_gpio_bits[1]	auto[1]	auto[0]	auto[0]	2339597	1			T22	32		T23	12965		T27	5
bins_for_gpio_bits[1]	auto[1]	auto[0]	auto[1]	552991	1			T22	11		T23	694		T27	2
bins_for_gpio_bits[1]	auto[1]	auto[1]	auto[1]	1814170	1			T22	1		T23	9394		T27	1
bins_for_gpio_bits[2]	auto[0]	auto[0]	auto[0]	6517511	1			T22	58		T23	37208		T24	42
bins_for_gpio_bits[2]	auto[0]	auto[0]	auto[1]	4675651	1			T22	22		T23	24251		T24	39
bins_for_gpio_bits[2]	auto[0]	auto[1]	auto[0]	1827624	1			T22	10		T23	9610		T27	5
bins_for_gpio_bits[2]	auto[1]	auto[0]	auto[0]	2333712	1			T22	12		T23	12401		T27	14
bins_for_gpio_bits[2]	auto[1]	auto[0]	auto[1]	549081	1			T23	780		T28	11		T31	2
bins_for_gpio_bits[2]	auto[1]	auto[1]	auto[1]	1810516	1			T23	9414		T28	8		T29	142
bins_for_gpio_bits[3]	auto[0]	auto[0]	auto[0]	6523495	1			T22	28		T23	37188		T24	42
bins_for_gpio_bits[3]	auto[0]	auto[0]	auto[1]	4674740	1			T22	40		T23	24223		T24	39
bins_for_gpio_bits[3]	auto[0]	auto[1]	auto[0]	1823338	1			T22	8		T23	9346		T28	26
bins_for_gpio_bits[3]	auto[1]	auto[0]	auto[0]	2328582	1			T22	16		T23	12918		T27	3
bins_for_gpio_bits[3]	auto[1]	auto[0]	auto[1]	548593	1			T22	10		T23	776		T27	3
bins_for_gpio_bits[3]	auto[1]	auto[1]	auto[1]	1815347	1			T23	9213		T27	2		T28	11
bins_for_gpio_bits[4]	auto[0]	auto[0]	auto[0]	6513735	1			T22	49		T23	36901		T24	40
bins_for_gpio_bits[4]	auto[0]	auto[0]	auto[1]	4683330	1			T22	38		T23	24222		T24	41
bins_for_gpio_bits[4]	auto[0]	auto[1]	auto[0]	1829906	1			T23	9593		T28	15		T29	156
bins_for_gpio_bits[4]	auto[1]	auto[0]	auto[0]	2332699	1			T22	15		T23	13006		T28	51
bins_for_gpio_bits[4]	auto[1]	auto[0]	auto[1]	546301	1			T23	816		T28	5		T31	16
bins_for_gpio_bits[4]	auto[1]	auto[1]	auto[1]	1808124	1			T23	9126		T28	29		T29	104
bins_for_gpio_bits[5]	auto[0]	auto[0]	auto[0]	6515480	1			T22	34		T23	36808		T24	41
bins_for_gpio_bits[5]	auto[0]	auto[0]	auto[1]	4683826	1			T22	33		T23	24288		T24	40
bins_for_gpio_bits[5]	auto[0]	auto[1]	auto[0]	1831466	1			T22	6		T23	9705		T27	5
bins_for_gpio_bits[5]	auto[1]	auto[0]	auto[0]	2327144	1			T22	5		T23	12882		T27	6
bins_for_gpio_bits[5]	auto[1]	auto[0]	auto[1]	549240	1			T22	7		T23	800		T27	4
bins_for_gpio_bits[5]	auto[1]	auto[1]	auto[1]	1806939	1			T22	17		T23	9181		T27	4
bins_for_gpio_bits[6]	auto[0]	auto[0]	auto[0]	6516129	1			T22	19		T23	37459		T24	63
bins_for_gpio_bits[6]	auto[0]	auto[0]	auto[1]	4683753	1			T22	40		T23	24497		T24	18
bins_for_gpio_bits[6]	auto[0]	auto[1]	auto[0]	1818183	1			T22	6		T23	8945		T27	5
bins_for_gpio_bits[6]	auto[1]	auto[0]	auto[0]	2335190	1			T22	12		T23	12771		T27	5
bins_for_gpio_bits[6]	auto[1]	auto[0]	auto[1]	550202	1			T22	13		T23	713		T27	3
bins_for_gpio_bits[6]	auto[1]	auto[1]	auto[1]	1810638	1			T22	12		T23	9279		T27	2
bins_for_gpio_bits[7]	auto[0]	auto[0]	auto[0]	6512404	1			T22	61		T23	36584		T24	36
bins_for_gpio_bits[7]	auto[0]	auto[0]	auto[1]	4681898	1			T22	11		T23	24586		T24	45
bins_for_gpio_bits[7]	auto[0]	auto[1]	auto[0]	1830253	1			T23	9688		T27	5		T28	28
bins_for_gpio_bits[7]	auto[1]	auto[0]	auto[0]	2335220	1			T22	9		T23	12992		T28	63
bins_for_gpio_bits[7]	auto[1]	auto[0]	auto[1]	549031	1			T22	14		T23	705		T27	7
bins_for_gpio_bits[7]	auto[1]	auto[1]	auto[1]	1805289	1			T22	7		T23	9109		T27	6
bins_for_gpio_bits[8]	auto[0]	auto[0]	auto[0]	6528032	1			T22	30		T23	36766		T24	36
bins_for_gpio_bits[8]	auto[0]	auto[0]	auto[1]	4663088	1			T22	48		T23	24383		T24	45
bins_for_gpio_bits[8]	auto[0]	auto[1]	auto[0]	1824032	1			T22	4		T23	9428		T28	26
bins_for_gpio_bits[8]	auto[1]	auto[0]	auto[0]	2335353	1			T22	9		T23	12955		T28	67
bins_for_gpio_bits[8]	auto[1]	auto[0]	auto[1]	553743	1			T22	6		T23	792		T27	5
bins_for_gpio_bits[8]	auto[1]	auto[1]	auto[1]	1809847	1			T22	5		T23	9340		T27	5
bins_for_gpio_bits[9]	auto[0]	auto[0]	auto[0]	6508772	1			T22	36		T23	37180		T24	36
bins_for_gpio_bits[9]	auto[0]	auto[0]	auto[1]	4684226	1			T22	27		T23	24450		T24	45
bins_for_gpio_bits[9]	auto[0]	auto[1]	auto[0]	1823446	1			T23	9362		T27	3		T28	21
bins_for_gpio_bits[9]	auto[1]	auto[0]	auto[0]	2340256	1			T22	16		T23	12727		T27	5
bins_for_gpio_bits[9]	auto[1]	auto[0]	auto[1]	547245	1			T22	3		T23	706		T27	4
bins_for_gpio_bits[9]	auto[1]	auto[1]	auto[1]	1810150	1			T22	20		T23	9239		T27	4
bins_for_gpio_bits[10]	auto[0]	auto[0]	auto[0]	6524479	1			T22	28		T23	36609		T24	41
bins_for_gpio_bits[10]	auto[0]	auto[0]	auto[1]	4676209	1			T22	36		T23	24498		T24	40
bins_for_gpio_bits[10]	auto[0]	auto[1]	auto[0]	1827685	1			T22	7		T23	9377		T28	16
bins_for_gpio_bits[10]	auto[1]	auto[0]	auto[0]	2331579	1			T22	2		T23	12830		T27	1
bins_for_gpio_bits[10]	auto[1]	auto[0]	auto[1]	547663	1			T22	13		T23	861		T27	2
bins_for_gpio_bits[10]	auto[1]	auto[1]	auto[1]	1806480	1			T22	16		T23	9489		T27	1
bins_for_gpio_bits[11]	auto[0]	auto[0]	auto[0]	6510245	1			T22	32		T23	36528		T24	44
bins_for_gpio_bits[11]	auto[0]	auto[0]	auto[1]	4684954	1			T22	31		T23	24254		T24	37
bins_for_gpio_bits[11]	auto[0]	auto[1]	auto[0]	1820669	1			T23	9420		T27	3		T28	10
bins_for_gpio_bits[11]	auto[1]	auto[0]	auto[0]	2334783	1			T22	17		T23	13161		T28	33
bins_for_gpio_bits[11]	auto[1]	auto[0]	auto[1]	550779	1			T22	17		T23	795		T27	5
bins_for_gpio_bits[11]	auto[1]	auto[1]	auto[1]	1812665	1			T22	5		T23	9506		T27	7
bins_for_gpio_bits[12]	auto[0]	auto[0]	auto[0]	6519699	1			T22	45		T23	36896		T24	47
bins_for_gpio_bits[12]	auto[0]	auto[0]	auto[1]	4682919	1			T22	19		T23	24375		T24	34
bins_for_gpio_bits[12]	auto[0]	auto[1]	auto[0]	1827386	1			T22	4		T23	9458		T28	10
bins_for_gpio_bits[12]	auto[1]	auto[0]	auto[0]	2326748	1			T22	11		T23	12835		T28	52
bins_for_gpio_bits[12]	auto[1]	auto[0]	auto[1]	549840	1			T22	16		T23	776		T27	6
bins_for_gpio_bits[12]	auto[1]	auto[1]	auto[1]	1807503	1			T22	7		T23	9324		T27	8
bins_for_gpio_bits[13]	auto[0]	auto[0]	auto[0]	6511298	1			T22	26		T23	37021		T24	45
bins_for_gpio_bits[13]	auto[0]	auto[0]	auto[1]	4681966	1			T22	35		T23	24419		T24	36
bins_for_gpio_bits[13]	auto[0]	auto[1]	auto[0]	1823637	1			T22	5		T23	9683		T27	6
bins_for_gpio_bits[13]	auto[1]	auto[0]	auto[0]	2329127	1			T22	9		T23	12456		T27	5
bins_for_gpio_bits[13]	auto[1]	auto[0]	auto[1]	550585	1			T22	16		T23	795		T28	5
bins_for_gpio_bits[13]	auto[1]	auto[1]	auto[1]	1817482	1			T22	11		T23	9290		T28	10
bins_for_gpio_bits[14]	auto[0]	auto[0]	auto[0]	6517506	1			T22	40		T23	37151		T24	53
bins_for_gpio_bits[14]	auto[0]	auto[0]	auto[1]	4675532	1			T22	21		T23	24317		T24	28
bins_for_gpio_bits[14]	auto[0]	auto[1]	auto[0]	1824957	1			T22	11		T23	9122		T28	28
bins_for_gpio_bits[14]	auto[1]	auto[0]	auto[0]	2335618	1			T22	16		T23	12979		T27	9
bins_for_gpio_bits[14]	auto[1]	auto[0]	auto[1]	548957	1			T22	3		T23	769		T28	5
bins_for_gpio_bits[14]	auto[1]	auto[1]	auto[1]	1811525	1			T22	11		T23	9326		T28	12
bins_for_gpio_bits[15]	auto[0]	auto[0]	auto[0]	6515889	1			T22	24		T23	36644		T24	43
bins_for_gpio_bits[15]	auto[0]	auto[0]	auto[1]	4674089	1			T22	37		T23	24344		T24	38
bins_for_gpio_bits[15]	auto[0]	auto[1]	auto[0]	1819610	1			T22	7		T23	9346		T27	3
bins_for_gpio_bits[15]	auto[1]	auto[0]	auto[0]	2339492	1			T22	19		T23	12882		T27	4
bins_for_gpio_bits[15]	auto[1]	auto[0]	auto[1]	550941	1			T22	11		T23	795		T27	2
bins_for_gpio_bits[15]	auto[1]	auto[1]	auto[1]	1814074	1			T22	4		T23	9653		T27	1
bins_for_gpio_bits[16]	auto[0]	auto[0]	auto[0]	6520715	1			T22	12		T23	36163		T24	40
bins_for_gpio_bits[16]	auto[0]	auto[0]	auto[1]	4675380	1			T22	46		T23	24410		T24	41
bins_for_gpio_bits[16]	auto[0]	auto[1]	auto[0]	1823369	1			T22	1		T23	9319		T28	22
bins_for_gpio_bits[16]	auto[1]	auto[0]	auto[0]	2337824	1			T22	28		T23	13419		T28	40
bins_for_gpio_bits[16]	auto[1]	auto[0]	auto[1]	552765	1			T22	15		T23	870		T28	4
bins_for_gpio_bits[16]	auto[1]	auto[1]	auto[1]	1804042	1			T23	9483		T28	29		T29	133
bins_for_gpio_bits[17]	auto[0]	auto[0]	auto[0]	6511510	1			T22	21		T23	36835		T24	31
bins_for_gpio_bits[17]	auto[0]	auto[0]	auto[1]	4686331	1			T22	37		T23	24303		T24	50
bins_for_gpio_bits[17]	auto[0]	auto[1]	auto[0]	1820015	1			T23	9017		T27	5		T28	22
bins_for_gpio_bits[17]	auto[1]	auto[0]	auto[0]	2341600	1			T22	28		T23	13425		T27	3
bins_for_gpio_bits[17]	auto[1]	auto[0]	auto[1]	548657	1			T22	14		T23	839		T28	7
bins_for_gpio_bits[17]	auto[1]	auto[1]	auto[1]	1805982	1			T22	2		T23	9245		T28	17
bins_for_gpio_bits[18]	auto[0]	auto[0]	auto[0]	6530489	1			T22	19		T23	37159		T24	49
bins_for_gpio_bits[18]	auto[0]	auto[0]	auto[1]	4673998	1			T22	50		T23	24205		T24	32
bins_for_gpio_bits[18]	auto[0]	auto[1]	auto[0]	1820248	1			T22	7		T23	9241		T28	31
bins_for_gpio_bits[18]	auto[1]	auto[0]	auto[0]	2338878	1			T22	16		T23	13086		T27	5
bins_for_gpio_bits[18]	auto[1]	auto[0]	auto[1]	550068	1			T22	10		T23	860		T28	13
bins_for_gpio_bits[18]	auto[1]	auto[1]	auto[1]	1800414	1			T23	9113		T28	10		T29	102
bins_for_gpio_bits[19]	auto[0]	auto[0]	auto[0]	6515829	1			T22	52		T23	36640		T24	50
bins_for_gpio_bits[19]	auto[0]	auto[0]	auto[1]	4683365	1			T22	39		T23	24370		T24	31
bins_for_gpio_bits[19]	auto[0]	auto[1]	auto[0]	1819140	1			T22	9		T23	9601		T27	3
bins_for_gpio_bits[19]	auto[1]	auto[0]	auto[0]	2342619	1			T22	2		T23	12611		T27	5
bins_for_gpio_bits[19]	auto[1]	auto[0]	auto[1]	549637	1			T23	803		T27	3		T28	4
bins_for_gpio_bits[19]	auto[1]	auto[1]	auto[1]	1803505	1			T23	9639		T28	18		T29	114
bins_for_gpio_bits[20]	auto[0]	auto[0]	auto[0]	6530493	1			T22	53		T23	36664		T24	36
bins_for_gpio_bits[20]	auto[0]	auto[0]	auto[1]	4667971	1			T22	29		T23	24266		T24	45
bins_for_gpio_bits[20]	auto[0]	auto[1]	auto[0]	1822814	1			T22	11		T23	8929		T27	4
bins_for_gpio_bits[20]	auto[1]	auto[0]	auto[0]	2336823	1			T22	6		T23	13170		T27	2
bins_for_gpio_bits[20]	auto[1]	auto[0]	auto[1]	550530	1			T22	3		T23	915		T27	1
bins_for_gpio_bits[20]	auto[1]	auto[1]	auto[1]	1805464	1			T23	9720		T28	17		T29	90
bins_for_gpio_bits[21]	auto[0]	auto[0]	auto[0]	6526205	1			T22	22		T23	36330		T24	43
bins_for_gpio_bits[21]	auto[0]	auto[0]	auto[1]	4678557	1			T22	49		T23	24311		T24	38
bins_for_gpio_bits[21]	auto[0]	auto[1]	auto[0]	1825721	1			T23	9131		T27	6		T28	27
bins_for_gpio_bits[21]	auto[1]	auto[0]	auto[0]	2328139	1			T22	17		T23	13414		T27	5
bins_for_gpio_bits[21]	auto[1]	auto[0]	auto[1]	549369	1			T22	11		T23	860		T27	3
bins_for_gpio_bits[21]	auto[1]	auto[1]	auto[1]	1806104	1			T22	3		T23	9618		T27	2
bins_for_gpio_bits[22]	auto[0]	auto[0]	auto[0]	6520742	1			T22	52		T23	37299		T24	33
bins_for_gpio_bits[22]	auto[0]	auto[0]	auto[1]	4677058	1			T22	32		T23	24345		T24	48
bins_for_gpio_bits[22]	auto[0]	auto[1]	auto[0]	1819449	1			T23	9111		T27	1		T29	104
bins_for_gpio_bits[22]	auto[1]	auto[0]	auto[0]	2339176	1			T22	5		T23	12639		T27	5
bins_for_gpio_bits[22]	auto[1]	auto[0]	auto[1]	553409	1			T22	12		T23	782		T27	3
bins_for_gpio_bits[22]	auto[1]	auto[1]	auto[1]	1804261	1			T22	1		T23	9488		T27	2
bins_for_gpio_bits[23]	auto[0]	auto[0]	auto[0]	6512720	1			T22	42		T23	37356		T24	49
bins_for_gpio_bits[23]	auto[0]	auto[0]	auto[1]	4685350	1			T22	46		T23	24365		T24	32
bins_for_gpio_bits[23]	auto[0]	auto[1]	auto[0]	1818605	1			T22	6		T23	9302		T27	5
bins_for_gpio_bits[23]	auto[1]	auto[0]	auto[0]	2346038	1			T22	1		T23	12844		T27	7
bins_for_gpio_bits[23]	auto[1]	auto[0]	auto[1]	551364	1			T22	6		T23	734		T28	2
bins_for_gpio_bits[23]	auto[1]	auto[1]	auto[1]	1800018	1			T22	1		T23	9063		T28	25
bins_for_gpio_bits[24]	auto[0]	auto[0]	auto[0]	6521019	1			T22	39		T23	37133		T24	42
bins_for_gpio_bits[24]	auto[0]	auto[0]	auto[1]	4677430	1			T22	31		T23	24441		T24	39
bins_for_gpio_bits[24]	auto[0]	auto[1]	auto[0]	1821794	1			T23	9334		T27	3		T28	16
bins_for_gpio_bits[24]	auto[1]	auto[0]	auto[0]	2341391	1			T22	8		T23	12738		T28	50
bins_for_gpio_bits[24]	auto[1]	auto[0]	auto[1]	547252	1			T22	22		T23	782		T27	6
bins_for_gpio_bits[24]	auto[1]	auto[1]	auto[1]	1805209	1			T22	2		T23	9236		T27	4
bins_for_gpio_bits[25]	auto[0]	auto[0]	auto[0]	6520067	1			T22	29		T23	37263		T24	44
bins_for_gpio_bits[25]	auto[0]	auto[0]	auto[1]	4681766	1			T22	53		T23	24273		T24	37
bins_for_gpio_bits[25]	auto[0]	auto[1]	auto[0]	1819986	1			T22	2		T23	9276		T27	5
bins_for_gpio_bits[25]	auto[1]	auto[0]	auto[0]	2340694	1			T22	10		T23	12879		T27	7
bins_for_gpio_bits[25]	auto[1]	auto[0]	auto[1]	547912	1			T22	2		T23	798		T31	6
bins_for_gpio_bits[25]	auto[1]	auto[1]	auto[1]	1803670	1			T22	6		T23	9175		T28	18
bins_for_gpio_bits[26]	auto[0]	auto[0]	auto[0]	6525636	1			T22	28		T23	37158		T24	39
bins_for_gpio_bits[26]	auto[0]	auto[0]	auto[1]	4674204	1			T22	41		T23	24507		T24	42
bins_for_gpio_bits[26]	auto[0]	auto[1]	auto[0]	1819742	1			T23	9458		T27	1		T28	22
bins_for_gpio_bits[26]	auto[1]	auto[0]	auto[0]	2343809	1			T22	21		T23	12325		T27	3
bins_for_gpio_bits[26]	auto[1]	auto[0]	auto[1]	550194	1			T22	8		T23	757		T28	3
bins_for_gpio_bits[26]	auto[1]	auto[1]	auto[1]	1800510	1			T22	4		T23	9459		T28	4
bins_for_gpio_bits[27]	auto[0]	auto[0]	auto[0]	6525487	1			T22	43		T23	36837		T24	45
bins_for_gpio_bits[27]	auto[0]	auto[0]	auto[1]	4679304	1			T22	55		T23	24246		T24	36
bins_for_gpio_bits[27]	auto[0]	auto[1]	auto[0]	1828271	1			T23	9280		T27	5		T28	28
bins_for_gpio_bits[27]	auto[1]	auto[0]	auto[0]	2326255	1			T22	4		T23	12958		T27	7
bins_for_gpio_bits[27]	auto[1]	auto[0]	auto[1]	548935	1			T23	821		T28	6		T31	12
bins_for_gpio_bits[27]	auto[1]	auto[1]	auto[1]	1805843	1			T23	9522		T28	10		T29	106
bins_for_gpio_bits[28]	auto[0]	auto[0]	auto[0]	6524413	1			T22	25		T23	36517		T24	30
bins_for_gpio_bits[28]	auto[0]	auto[0]	auto[1]	4667589	1			T22	59		T23	24220		T24	51
bins_for_gpio_bits[28]	auto[0]	auto[1]	auto[0]	1819619	1			T22	14		T23	9091		T28	27
bins_for_gpio_bits[28]	auto[1]	auto[0]	auto[0]	2341714	1			T23	13277		T28	24		T29	138
bins_for_gpio_bits[28]	auto[1]	auto[0]	auto[1]	552770	1			T22	4		T23	826		T27	6
bins_for_gpio_bits[28]	auto[1]	auto[1]	auto[1]	1807990	1			T23	9733		T27	4		T28	10
bins_for_gpio_bits[29]	auto[0]	auto[0]	auto[0]	6521212	1			T22	44		T23	36996		T24	36
bins_for_gpio_bits[29]	auto[0]	auto[0]	auto[1]	4675612	1			T22	35		T23	24234		T24	45
bins_for_gpio_bits[29]	auto[0]	auto[1]	auto[0]	1816828	1			T22	7		T23	9466		T27	5
bins_for_gpio_bits[29]	auto[1]	auto[0]	auto[0]	2338536	1			T22	8		T23	12889		T28	48
bins_for_gpio_bits[29]	auto[1]	auto[0]	auto[1]	551630	1			T22	4		T23	775		T27	1
bins_for_gpio_bits[29]	auto[1]	auto[1]	auto[1]	1810277	1			T22	4		T23	9304		T28	18
bins_for_gpio_bits[30]	auto[0]	auto[0]	auto[0]	6519396	1			T22	40		T23	37011		T24	61
bins_for_gpio_bits[30]	auto[0]	auto[0]	auto[1]	4675230	1			T22	15		T23	24381		T24	20
bins_for_gpio_bits[30]	auto[0]	auto[1]	auto[0]	1822869	1			T22	11		T23	9076		T28	30
bins_for_gpio_bits[30]	auto[1]	auto[0]	auto[0]	2339374	1			T22	12		T23	13204		T28	45
bins_for_gpio_bits[30]	auto[1]	auto[0]	auto[1]	554417	1			T22	6		T23	750		T28	4
bins_for_gpio_bits[30]	auto[1]	auto[1]	auto[1]	1802809	1			T22	18		T23	9242		T28	18
bins_for_gpio_bits[31]	auto[0]	auto[0]	auto[0]	6525071	1			T22	11		T23	36765		T24	31
bins_for_gpio_bits[31]	auto[0]	auto[0]	auto[1]	4675735	1			T22	62		T23	24240		T24	50
bins_for_gpio_bits[31]	auto[0]	auto[1]	auto[0]	1823798	1			T22	4		T23	9061		T27	1
bins_for_gpio_bits[31]	auto[1]	auto[0]	auto[0]	2337708	1			T23	13286		T27	3		T28	21
bins_for_gpio_bits[31]	auto[1]	auto[0]	auto[1]	550865	1			T22	15		T23	930		T28	1
bins_for_gpio_bits[31]	auto[1]	auto[1]	auto[1]	1800918	1			T22	10		T23	9382		T28	6

User Defined Cross Bins for cp_cross_all

Excluded/Illegal bins

NAME	COUNT	STATUS
data_oe_1_data_out_0_data_in_1	0	Illegal
data_oe_1_data_out_1_data_in_0	0	Illegal