Unified Coverage Report :: Group :: gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

Group : gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_gpio_env_0.1/gpio_env_cov.sv

---

Summary for Group gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	36	0	36	100.00
Crosses	128	0	128	100.00

Variables for Group gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_pin	32	0	32	100.00	100	1	1	0
data_in	2	0	2	100.00	100	1	1	2
gpio_value	2	0	2	100.00	100	1	1	2

Crosses for Group gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_cross_pins_data_in	128	0	128	100.00	100	1	1	0

Summary for Variable cp_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	32	0	32	100.00

User Defined Bins for cp_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bins_for_gpio_bits[0]	17714095	1			T22	102		T23	93664		T24	81
bins_for_gpio_bits[1]	17714095	1			T22	102		T23	93664		T24	81
bins_for_gpio_bits[2]	17714095	1			T22	102		T23	93664		T24	81
bins_for_gpio_bits[3]	17714095	1			T22	102		T23	93664		T24	81
bins_for_gpio_bits[4]	17714095	1			T22	102		T23	93664		T24	81
bins_for_gpio_bits[5]	17714095	1			T22	102		T23	93664		T24	81
bins_for_gpio_bits[6]	17714095	1			T22	102		T23	93664		T24	81
bins_for_gpio_bits[7]	17714095	1			T22	102		T23	93664		T24	81
bins_for_gpio_bits[8]	17714095	1			T22	102		T23	93664		T24	81
bins_for_gpio_bits[9]	17714095	1			T22	102		T23	93664		T24	81
bins_for_gpio_bits[10]	17714095	1			T22	102		T23	93664		T24	81
bins_for_gpio_bits[11]	17714095	1			T22	102		T23	93664		T24	81
bins_for_gpio_bits[12]	17714095	1			T22	102		T23	93664		T24	81
bins_for_gpio_bits[13]	17714095	1			T22	102		T23	93664		T24	81
bins_for_gpio_bits[14]	17714095	1			T22	102		T23	93664		T24	81
bins_for_gpio_bits[15]	17714095	1			T22	102		T23	93664		T24	81
bins_for_gpio_bits[16]	17714095	1			T22	102		T23	93664		T24	81
bins_for_gpio_bits[17]	17714095	1			T22	102		T23	93664		T24	81
bins_for_gpio_bits[18]	17714095	1			T22	102		T23	93664		T24	81
bins_for_gpio_bits[19]	17714095	1			T22	102		T23	93664		T24	81
bins_for_gpio_bits[20]	17714095	1			T22	102		T23	93664		T24	81
bins_for_gpio_bits[21]	17714095	1			T22	102		T23	93664		T24	81
bins_for_gpio_bits[22]	17714095	1			T22	102		T23	93664		T24	81
bins_for_gpio_bits[23]	17714095	1			T22	102		T23	93664		T24	81
bins_for_gpio_bits[24]	17714095	1			T22	102		T23	93664		T24	81
bins_for_gpio_bits[25]	17714095	1			T22	102		T23	93664		T24	81
bins_for_gpio_bits[26]	17714095	1			T22	102		T23	93664		T24	81
bins_for_gpio_bits[27]	17714095	1			T22	102		T23	93664		T24	81
bins_for_gpio_bits[28]	17714095	1			T22	102		T23	93664		T24	81
bins_for_gpio_bits[29]	17714095	1			T22	102		T23	93664		T24	81
bins_for_gpio_bits[30]	17714095	1			T22	102		T23	93664		T24	81
bins_for_gpio_bits[31]	17714095	1			T22	102		T23	93664		T24	81

---

Summary for Variable data_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for data_in

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

341716680

1

T22

1616

T23

189339

T24

1336

auto[1]

225134360

1

T22

1648

T23

110385

T24

1256

---

Summary for Variable gpio_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for gpio_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

341711112

1

T22

1616

T23

189321

T24

1336

auto[1]

225139928

1

T22

1648

T23

110402

T24

1256

---

Summary for Cross cp_cross_pins_data_in

Samples crossed: cp_pin gpio_value data_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cp_cross_pins_data_in

Bins

cp_pin	gpio_value	data_in	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bins_for_gpio_bits[0]	auto[0]	auto[0]	10351827	1			T22	24		T23	57375		T24	28
bins_for_gpio_bits[0]	auto[0]	auto[1]	323638	1			T23	1793		T28	2		T29	33
bins_for_gpio_bits[0]	auto[1]	auto[0]	323833	1			T23	1799		T28	2		T29	33
bins_for_gpio_bits[0]	auto[1]	auto[1]	6714797	1			T22	78		T23	32697		T24	53
bins_for_gpio_bits[1]	auto[0]	auto[0]	10350381	1			T22	76		T23	57634		T24	40
bins_for_gpio_bits[1]	auto[0]	auto[1]	324252	1			T23	1772		T28	4		T29	26
bins_for_gpio_bits[1]	auto[1]	auto[0]	324420	1			T23	1778		T28	5		T29	26
bins_for_gpio_bits[1]	auto[1]	auto[1]	6715042	1			T22	26		T23	32480		T24	41
bins_for_gpio_bits[2]	auto[0]	auto[0]	10355004	1			T22	80		T23	57440		T24	42
bins_for_gpio_bits[2]	auto[0]	auto[1]	323716	1			T23	1777		T28	2		T29	32
bins_for_gpio_bits[2]	auto[1]	auto[0]	323843	1			T23	1779		T28	2		T29	32
bins_for_gpio_bits[2]	auto[1]	auto[1]	6711532	1			T22	22		T23	32668		T24	39
bins_for_gpio_bits[3]	auto[0]	auto[0]	10352105	1			T22	52		T23	57685		T24	42
bins_for_gpio_bits[3]	auto[0]	auto[1]	323139	1			T23	1761		T28	1		T29	31
bins_for_gpio_bits[3]	auto[1]	auto[0]	323310	1			T23	1767		T28	1		T29	32
bins_for_gpio_bits[3]	auto[1]	auto[1]	6715541	1			T22	50		T23	32451		T24	39
bins_for_gpio_bits[4]	auto[0]	auto[0]	10352489	1			T22	64		T23	57762		T24	40
bins_for_gpio_bits[4]	auto[0]	auto[1]	323688	1			T23	1731		T28	5		T29	29
bins_for_gpio_bits[4]	auto[1]	auto[0]	323851	1			T23	1738		T28	5		T29	29
bins_for_gpio_bits[4]	auto[1]	auto[1]	6714067	1			T22	38		T23	32433		T24	41
bins_for_gpio_bits[5]	auto[0]	auto[0]	10350697	1			T22	45		T23	57649		T24	41
bins_for_gpio_bits[5]	auto[0]	auto[1]	323254	1			T23	1741		T28	2		T29	26
bins_for_gpio_bits[5]	auto[1]	auto[0]	323393	1			T23	1746		T28	2		T29	26
bins_for_gpio_bits[5]	auto[1]	auto[1]	6716751	1			T22	57		T23	32528		T24	40
bins_for_gpio_bits[6]	auto[0]	auto[0]	10346429	1			T22	36		T23	57478		T24	63
bins_for_gpio_bits[6]	auto[0]	auto[1]	322915	1			T22	1		T23	1690		T28	4
bins_for_gpio_bits[6]	auto[1]	auto[0]	323073	1			T22	1		T23	1697		T28	4
bins_for_gpio_bits[6]	auto[1]	auto[1]	6721678	1			T22	64		T23	32799		T24	18
bins_for_gpio_bits[7]	auto[0]	auto[0]	10355095	1			T22	70		T23	57470		T24	36
bins_for_gpio_bits[7]	auto[0]	auto[1]	322623	1			T23	1790		T28	3		T29	28
bins_for_gpio_bits[7]	auto[1]	auto[0]	322782	1			T23	1794		T28	3		T29	28
bins_for_gpio_bits[7]	auto[1]	auto[1]	6713595	1			T22	32		T23	32610		T24	45
bins_for_gpio_bits[8]	auto[0]	auto[0]	10363951	1			T22	43		T23	57410		T24	36
bins_for_gpio_bits[8]	auto[0]	auto[1]	323262	1			T23	1737		T28	3		T29	32
bins_for_gpio_bits[8]	auto[1]	auto[0]	323466	1			T23	1739		T28	3		T29	33
bins_for_gpio_bits[8]	auto[1]	auto[1]	6703416	1			T22	59		T23	32778		T24	45
bins_for_gpio_bits[9]	auto[0]	auto[0]	10348831	1			T22	52		T23	57548		T24	36
bins_for_gpio_bits[9]	auto[0]	auto[1]	323478	1			T23	1715		T28	4		T29	27
bins_for_gpio_bits[9]	auto[1]	auto[0]	323643	1			T23	1721		T28	4		T29	28
bins_for_gpio_bits[9]	auto[1]	auto[1]	6718143	1			T22	50		T23	32680		T24	45
bins_for_gpio_bits[10]	auto[0]	auto[0]	10360099	1			T22	37		T23	57040		T24	41
bins_for_gpio_bits[10]	auto[0]	auto[1]	323451	1			T23	1771		T28	2		T29	29
bins_for_gpio_bits[10]	auto[1]	auto[0]	323644	1			T23	1776		T28	2		T29	29
bins_for_gpio_bits[10]	auto[1]	auto[1]	6706901	1			T22	65		T23	33077		T24	40
bins_for_gpio_bits[11]	auto[0]	auto[0]	10342955	1			T22	49		T23	57314		T24	44
bins_for_gpio_bits[11]	auto[0]	auto[1]	322601	1			T23	1790		T29	28		T60	12
bins_for_gpio_bits[11]	auto[1]	auto[0]	322742	1			T23	1795		T29	29		T60	11
bins_for_gpio_bits[11]	auto[1]	auto[1]	6725797	1			T22	53		T23	32765		T24	37
bins_for_gpio_bits[12]	auto[0]	auto[0]	10350915	1			T22	60		T23	57438		T24	47
bins_for_gpio_bits[12]	auto[0]	auto[1]	322767	1			T23	1747		T28	4		T29	26
bins_for_gpio_bits[12]	auto[1]	auto[0]	322918	1			T23	1751		T28	4		T29	26
bins_for_gpio_bits[12]	auto[1]	auto[1]	6717495	1			T22	42		T23	32728		T24	34
bins_for_gpio_bits[13]	auto[0]	auto[0]	10340392	1			T22	40		T23	57388		T24	45
bins_for_gpio_bits[13]	auto[0]	auto[1]	323505	1			T23	1766		T28	3		T29	31
bins_for_gpio_bits[13]	auto[1]	auto[0]	323670	1			T23	1772		T28	3		T29	32
bins_for_gpio_bits[13]	auto[1]	auto[1]	6726528	1			T22	62		T23	32738		T24	36
bins_for_gpio_bits[14]	auto[0]	auto[0]	10354450	1			T22	67		T23	57500		T24	53
bins_for_gpio_bits[14]	auto[0]	auto[1]	323430	1			T23	1741		T28	3		T29	30
bins_for_gpio_bits[14]	auto[1]	auto[0]	323631	1			T23	1752		T28	3		T29	30
bins_for_gpio_bits[14]	auto[1]	auto[1]	6712584	1			T22	35		T23	32671		T24	28
bins_for_gpio_bits[15]	auto[0]	auto[0]	10351259	1			T22	50		T23	57086		T24	43
bins_for_gpio_bits[15]	auto[0]	auto[1]	323590	1			T23	1782		T28	2		T29	30
bins_for_gpio_bits[15]	auto[1]	auto[0]	323732	1			T23	1786		T28	2		T29	31
bins_for_gpio_bits[15]	auto[1]	auto[1]	6715514	1			T22	52		T23	33010		T24	38
bins_for_gpio_bits[16]	auto[0]	auto[0]	10357853	1			T22	41		T23	57095		T24	40
bins_for_gpio_bits[16]	auto[0]	auto[1]	323839	1			T23	1799		T28	4		T29	28
bins_for_gpio_bits[16]	auto[1]	auto[0]	324055	1			T23	1806		T28	4		T29	29
bins_for_gpio_bits[16]	auto[1]	auto[1]	6708348	1			T22	61		T23	32964		T24	41
bins_for_gpio_bits[17]	auto[0]	auto[0]	10348763	1			T22	49		T23	57513		T24	31
bins_for_gpio_bits[17]	auto[0]	auto[1]	324214	1			T23	1759		T28	3		T29	29
bins_for_gpio_bits[17]	auto[1]	auto[0]	324362	1			T23	1764		T28	3		T29	29
bins_for_gpio_bits[17]	auto[1]	auto[1]	6716756	1			T22	53		T23	32628		T24	50
bins_for_gpio_bits[18]	auto[0]	auto[0]	10366257	1			T22	42		T23	57735		T24	49
bins_for_gpio_bits[18]	auto[0]	auto[1]	323140	1			T23	1744		T28	2		T29	26
bins_for_gpio_bits[18]	auto[1]	auto[0]	323358	1			T23	1751		T28	2		T29	26
bins_for_gpio_bits[18]	auto[1]	auto[1]	6701340	1			T22	60		T23	32434		T24	32
bins_for_gpio_bits[19]	auto[0]	auto[0]	10353627	1			T22	63		T23	57109		T24	50
bins_for_gpio_bits[19]	auto[0]	auto[1]	323760	1			T23	1735		T28	3		T29	29
bins_for_gpio_bits[19]	auto[1]	auto[0]	323961	1			T23	1743		T28	3		T29	29
bins_for_gpio_bits[19]	auto[1]	auto[1]	6712747	1			T22	39		T23	33077		T24	31
bins_for_gpio_bits[20]	auto[0]	auto[0]	10366710	1			T22	70		T23	56994		T24	36
bins_for_gpio_bits[20]	auto[0]	auto[1]	323231	1			T23	1765		T28	4		T29	29
bins_for_gpio_bits[20]	auto[1]	auto[0]	323420	1			T23	1769		T28	4		T29	29
bins_for_gpio_bits[20]	auto[1]	auto[1]	6700734	1			T22	32		T23	33136		T24	45
bins_for_gpio_bits[21]	auto[0]	auto[0]	10356117	1			T22	39		T23	57053		T24	43
bins_for_gpio_bits[21]	auto[0]	auto[1]	323756	1			T23	1817		T28	4		T29	25
bins_for_gpio_bits[21]	auto[1]	auto[0]	323948	1			T23	1822		T28	5		T29	25
bins_for_gpio_bits[21]	auto[1]	auto[1]	6710274	1			T22	63		T23	32972		T24	38
bins_for_gpio_bits[22]	auto[0]	auto[0]	10355905	1			T22	57		T23	57315		T24	33
bins_for_gpio_bits[22]	auto[0]	auto[1]	323285	1			T23	1724		T28	5		T29	31
bins_for_gpio_bits[22]	auto[1]	auto[0]	323462	1			T23	1734		T28	5		T29	31
bins_for_gpio_bits[22]	auto[1]	auto[1]	6711443	1			T22	45		T23	32891		T24	48
bins_for_gpio_bits[23]	auto[0]	auto[0]	10353886	1			T22	49		T23	57739		T24	49
bins_for_gpio_bits[23]	auto[0]	auto[1]	323327	1			T23	1758		T28	3		T29	33
bins_for_gpio_bits[23]	auto[1]	auto[0]	323477	1			T23	1763		T28	3		T29	33
bins_for_gpio_bits[23]	auto[1]	auto[1]	6713405	1			T22	53		T23	32404		T24	32
bins_for_gpio_bits[24]	auto[0]	auto[0]	10359982	1			T22	47		T23	57459		T24	42
bins_for_gpio_bits[24]	auto[0]	auto[1]	324030	1			T23	1740		T28	4		T29	28
bins_for_gpio_bits[24]	auto[1]	auto[0]	324222	1			T23	1746		T28	4		T29	28
bins_for_gpio_bits[24]	auto[1]	auto[1]	6705861	1			T22	55		T23	32719		T24	39
bins_for_gpio_bits[25]	auto[0]	auto[0]	10356622	1			T22	40		T23	57641		T24	44
bins_for_gpio_bits[25]	auto[0]	auto[1]	323932	1			T22	1		T23	1770		T28	3
bins_for_gpio_bits[25]	auto[1]	auto[0]	324125	1			T22	1		T23	1777		T28	3
bins_for_gpio_bits[25]	auto[1]	auto[1]	6709416	1			T22	60		T23	32476		T24	37
bins_for_gpio_bits[26]	auto[0]	auto[0]	10365596	1			T22	49		T23	57180		T24	39
bins_for_gpio_bits[26]	auto[0]	auto[1]	323423	1			T23	1758		T28	2		T29	28
bins_for_gpio_bits[26]	auto[1]	auto[0]	323591	1			T23	1761		T28	2		T29	28
bins_for_gpio_bits[26]	auto[1]	auto[1]	6701485	1			T22	53		T23	32965		T24	42
bins_for_gpio_bits[27]	auto[0]	auto[0]	10356794	1			T22	47		T23	57309		T24	45
bins_for_gpio_bits[27]	auto[0]	auto[1]	323054	1			T23	1761		T28	3		T29	26
bins_for_gpio_bits[27]	auto[1]	auto[0]	323219	1			T23	1766		T28	3		T29	26
bins_for_gpio_bits[27]	auto[1]	auto[1]	6711028	1			T22	55		T23	32828		T24	36
bins_for_gpio_bits[28]	auto[0]	auto[0]	10362224	1			T22	39		T23	57127		T24	30
bins_for_gpio_bits[28]	auto[0]	auto[1]	323388	1			T23	1754		T28	2		T29	27
bins_for_gpio_bits[28]	auto[1]	auto[0]	323522	1			T23	1758		T28	2		T29	28
bins_for_gpio_bits[28]	auto[1]	auto[1]	6704961	1			T22	63		T23	33025		T24	51
bins_for_gpio_bits[29]	auto[0]	auto[0]	10352636	1			T22	59		T23	57592		T24	36
bins_for_gpio_bits[29]	auto[0]	auto[1]	323762	1			T23	1758		T28	3		T29	31
bins_for_gpio_bits[29]	auto[1]	auto[0]	323940	1			T23	1759		T28	3		T29	32
bins_for_gpio_bits[29]	auto[1]	auto[1]	6713757	1			T22	43		T23	32555		T24	45
bins_for_gpio_bits[30]	auto[0]	auto[0]	10358241	1			T22	62		T23	57548		T24	61
bins_for_gpio_bits[30]	auto[0]	auto[1]	323206	1			T22	1		T23	1740		T28	3
bins_for_gpio_bits[30]	auto[1]	auto[0]	323398	1			T22	1		T23	1743		T28	3
bins_for_gpio_bits[30]	auto[1]	auto[1]	6709250	1			T22	38		T23	32633		T24	20
bins_for_gpio_bits[31]	auto[0]	auto[0]	10362827	1			T22	14		T23	57366		T24	31
bins_for_gpio_bits[31]	auto[0]	auto[1]	323537	1			T22	1		T23	1741		T28	1
bins_for_gpio_bits[31]	auto[1]	auto[0]	323750	1			T22	1		T23	1746		T28	1
bins_for_gpio_bits[31]	auto[1]	auto[1]	6703981	1			T22	86		T23	32811		T24	50