Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10047220 |
1 |
|
|
T22 |
27 |
|
T23 |
53767 |
|
T24 |
110 |
| auto[1] |
8000155 |
1 |
|
|
T22 |
23 |
|
T23 |
45546 |
|
T24 |
36 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
17024669 |
1 |
|
|
T22 |
50 |
|
T23 |
93319 |
|
T24 |
141 |
| auto[1] |
1022706 |
1 |
|
|
T23 |
5994 |
|
T24 |
5 |
|
T26 |
208 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10065096 |
1 |
|
|
T22 |
47 |
|
T23 |
56962 |
|
T24 |
51 |
| auto[1] |
7982279 |
1 |
|
|
T22 |
3 |
|
T23 |
42351 |
|
T24 |
95 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
3486130 |
1 |
|
|
T23 |
17884 |
|
T24 |
69 |
|
T26 |
500 |
| auto[1] |
auto[0] |
auto[1] |
512680 |
1 |
|
|
T23 |
2936 |
|
T24 |
5 |
|
T26 |
122 |
| auto[1] |
auto[1] |
auto[0] |
3473443 |
1 |
|
|
T22 |
3 |
|
T23 |
18473 |
|
T24 |
21 |
| auto[1] |
auto[1] |
auto[1] |
510026 |
1 |
|
|
T23 |
3058 |
|
T26 |
86 |
|
T30 |
64 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10078977 |
1 |
|
|
T22 |
46 |
|
T23 |
53178 |
|
T24 |
117 |
| auto[1] |
7968398 |
1 |
|
|
T22 |
4 |
|
T23 |
46135 |
|
T24 |
29 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
17026920 |
1 |
|
|
T22 |
50 |
|
T23 |
93314 |
|
T24 |
142 |
| auto[1] |
1020455 |
1 |
|
|
T23 |
5999 |
|
T24 |
4 |
|
T26 |
196 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10072760 |
1 |
|
|
T22 |
46 |
|
T23 |
55569 |
|
T24 |
87 |
| auto[1] |
7974615 |
1 |
|
|
T22 |
4 |
|
T23 |
43744 |
|
T24 |
59 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
3487303 |
1 |
|
|
T22 |
1 |
|
T23 |
18694 |
|
T24 |
52 |
| auto[1] |
auto[0] |
auto[1] |
513199 |
1 |
|
|
T23 |
2973 |
|
T24 |
4 |
|
T26 |
121 |
| auto[1] |
auto[1] |
auto[0] |
3466857 |
1 |
|
|
T22 |
3 |
|
T23 |
19051 |
|
T24 |
3 |
| auto[1] |
auto[1] |
auto[1] |
507256 |
1 |
|
|
T23 |
3026 |
|
T26 |
75 |
|
T30 |
35 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10033338 |
1 |
|
|
T22 |
30 |
|
T23 |
53892 |
|
T24 |
78 |
| auto[1] |
8014037 |
1 |
|
|
T22 |
20 |
|
T23 |
45421 |
|
T24 |
68 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
17025876 |
1 |
|
|
T22 |
50 |
|
T23 |
93076 |
|
T24 |
139 |
| auto[1] |
1021499 |
1 |
|
|
T23 |
6237 |
|
T24 |
7 |
|
T26 |
133 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10060280 |
1 |
|
|
T22 |
46 |
|
T23 |
54434 |
|
T24 |
47 |
| auto[1] |
7987095 |
1 |
|
|
T22 |
4 |
|
T23 |
44879 |
|
T24 |
99 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
3469097 |
1 |
|
|
T22 |
4 |
|
T23 |
19045 |
|
T24 |
40 |
| auto[1] |
auto[0] |
auto[1] |
508065 |
1 |
|
|
T23 |
3047 |
|
T24 |
4 |
|
T26 |
76 |
| auto[1] |
auto[1] |
auto[0] |
3496499 |
1 |
|
|
T23 |
19597 |
|
T24 |
52 |
|
T26 |
246 |
| auto[1] |
auto[1] |
auto[1] |
513434 |
1 |
|
|
T23 |
3190 |
|
T24 |
3 |
|
T26 |
57 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10021318 |
1 |
|
|
T22 |
30 |
|
T23 |
55625 |
|
T24 |
78 |
| auto[1] |
8026057 |
1 |
|
|
T22 |
20 |
|
T23 |
43688 |
|
T24 |
68 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
17021151 |
1 |
|
|
T22 |
50 |
|
T23 |
92948 |
|
T24 |
141 |
| auto[1] |
1026224 |
1 |
|
|
T23 |
6365 |
|
T24 |
5 |
|
T26 |
164 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10033922 |
1 |
|
|
T22 |
46 |
|
T23 |
53536 |
|
T24 |
70 |
| auto[1] |
8013453 |
1 |
|
|
T22 |
4 |
|
T23 |
45777 |
|
T24 |
76 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
3488825 |
1 |
|
|
T22 |
4 |
|
T23 |
21080 |
|
T24 |
36 |
| auto[1] |
auto[0] |
auto[1] |
511573 |
1 |
|
|
T23 |
3386 |
|
T24 |
4 |
|
T26 |
101 |
| auto[1] |
auto[1] |
auto[0] |
3498404 |
1 |
|
|
T23 |
18332 |
|
T24 |
35 |
|
T26 |
249 |
| auto[1] |
auto[1] |
auto[1] |
514651 |
1 |
|
|
T23 |
2979 |
|
T24 |
1 |
|
T26 |
63 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10048944 |
1 |
|
|
T22 |
43 |
|
T23 |
54674 |
|
T24 |
61 |
| auto[1] |
7998431 |
1 |
|
|
T22 |
7 |
|
T23 |
44639 |
|
T24 |
85 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
17020412 |
1 |
|
|
T22 |
50 |
|
T23 |
93413 |
|
T24 |
141 |
| auto[1] |
1026963 |
1 |
|
|
T23 |
5900 |
|
T24 |
5 |
|
T26 |
175 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10029300 |
1 |
|
|
T22 |
46 |
|
T23 |
56264 |
|
T24 |
81 |
| auto[1] |
8018075 |
1 |
|
|
T22 |
4 |
|
T23 |
43049 |
|
T24 |
65 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
3501853 |
1 |
|
|
T22 |
1 |
|
T23 |
18938 |
|
T24 |
34 |
| auto[1] |
auto[0] |
auto[1] |
514422 |
1 |
|
|
T23 |
2989 |
|
T24 |
2 |
|
T26 |
94 |
| auto[1] |
auto[1] |
auto[0] |
3489259 |
1 |
|
|
T22 |
3 |
|
T23 |
18211 |
|
T24 |
26 |
| auto[1] |
auto[1] |
auto[1] |
512541 |
1 |
|
|
T23 |
2911 |
|
T24 |
3 |
|
T26 |
81 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10037207 |
1 |
|
|
T22 |
50 |
|
T23 |
54643 |
|
T24 |
29 |
| auto[1] |
8010168 |
1 |
|
|
T23 |
44670 |
|
T24 |
117 |
|
T26 |
1307 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
17024887 |
1 |
|
|
T22 |
50 |
|
T23 |
93446 |
|
T24 |
141 |
| auto[1] |
1022488 |
1 |
|
|
T23 |
5867 |
|
T24 |
5 |
|
T26 |
196 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10060325 |
1 |
|
|
T22 |
46 |
|
T23 |
56764 |
|
T24 |
61 |
| auto[1] |
7987050 |
1 |
|
|
T22 |
4 |
|
T23 |
42549 |
|
T24 |
85 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
3464083 |
1 |
|
|
T22 |
4 |
|
T23 |
18331 |
|
T24 |
14 |
| auto[1] |
auto[0] |
auto[1] |
508784 |
1 |
|
|
T23 |
2913 |
|
T26 |
69 |
|
T30 |
71 |
| auto[1] |
auto[1] |
auto[0] |
3500479 |
1 |
|
|
T23 |
18351 |
|
T24 |
66 |
|
T26 |
576 |
| auto[1] |
auto[1] |
auto[1] |
513704 |
1 |
|
|
T23 |
2954 |
|
T24 |
5 |
|
T26 |
127 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10040766 |
1 |
|
|
T22 |
43 |
|
T23 |
53611 |
|
T24 |
82 |
| auto[1] |
8006609 |
1 |
|
|
T22 |
7 |
|
T23 |
45702 |
|
T24 |
64 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
17021433 |
1 |
|
|
T22 |
50 |
|
T23 |
93183 |
|
T24 |
143 |
| auto[1] |
1025942 |
1 |
|
|
T23 |
6130 |
|
T24 |
3 |
|
T26 |
204 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10038629 |
1 |
|
|
T22 |
42 |
|
T23 |
54700 |
|
T24 |
78 |
| auto[1] |
8008746 |
1 |
|
|
T22 |
8 |
|
T23 |
44613 |
|
T24 |
68 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
3504023 |
1 |
|
|
T22 |
8 |
|
T23 |
19113 |
|
T24 |
39 |
| auto[1] |
auto[0] |
auto[1] |
514700 |
1 |
|
|
T23 |
3005 |
|
T24 |
2 |
|
T26 |
125 |
| auto[1] |
auto[1] |
auto[0] |
3478781 |
1 |
|
|
T23 |
19370 |
|
T24 |
26 |
|
T26 |
406 |
| auto[1] |
auto[1] |
auto[1] |
511242 |
1 |
|
|
T23 |
3125 |
|
T24 |
1 |
|
T26 |
79 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10081704 |
1 |
|
|
T22 |
42 |
|
T23 |
55588 |
|
T24 |
77 |
| auto[1] |
7965671 |
1 |
|
|
T22 |
8 |
|
T23 |
43725 |
|
T24 |
69 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
17026642 |
1 |
|
|
T22 |
50 |
|
T23 |
93272 |
|
T24 |
139 |
| auto[1] |
1020733 |
1 |
|
|
T23 |
6041 |
|
T24 |
7 |
|
T26 |
150 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10071855 |
1 |
|
|
T22 |
42 |
|
T23 |
56092 |
|
T24 |
59 |
| auto[1] |
7975520 |
1 |
|
|
T22 |
8 |
|
T23 |
43221 |
|
T24 |
87 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
3493199 |
1 |
|
|
T22 |
5 |
|
T23 |
18898 |
|
T24 |
47 |
| auto[1] |
auto[0] |
auto[1] |
513524 |
1 |
|
|
T23 |
3126 |
|
T24 |
3 |
|
T26 |
82 |
| auto[1] |
auto[1] |
auto[0] |
3461588 |
1 |
|
|
T22 |
3 |
|
T23 |
18282 |
|
T24 |
33 |
| auto[1] |
auto[1] |
auto[1] |
507209 |
1 |
|
|
T23 |
2915 |
|
T24 |
4 |
|
T26 |
68 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10046132 |
1 |
|
|
T22 |
39 |
|
T23 |
55106 |
|
T24 |
69 |
| auto[1] |
8001243 |
1 |
|
|
T22 |
11 |
|
T23 |
44207 |
|
T24 |
77 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
17021075 |
1 |
|
|
T22 |
50 |
|
T23 |
93139 |
|
T24 |
141 |
| auto[1] |
1026300 |
1 |
|
|
T23 |
6174 |
|
T24 |
5 |
|
T26 |
163 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10036326 |
1 |
|
|
T22 |
46 |
|
T23 |
55399 |
|
T24 |
70 |
| auto[1] |
8011049 |
1 |
|
|
T22 |
4 |
|
T23 |
43914 |
|
T24 |
76 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
3499436 |
1 |
|
|
T22 |
1 |
|
T23 |
18821 |
|
T24 |
48 |
| auto[1] |
auto[0] |
auto[1] |
514274 |
1 |
|
|
T23 |
3115 |
|
T24 |
3 |
|
T26 |
92 |
| auto[1] |
auto[1] |
auto[0] |
3485313 |
1 |
|
|
T22 |
3 |
|
T23 |
18919 |
|
T24 |
23 |
| auto[1] |
auto[1] |
auto[1] |
512026 |
1 |
|
|
T23 |
3059 |
|
T24 |
2 |
|
T26 |
71 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10064460 |
1 |
|
|
T22 |
46 |
|
T23 |
55052 |
|
T24 |
39 |
| auto[1] |
7982915 |
1 |
|
|
T22 |
4 |
|
T23 |
44261 |
|
T24 |
107 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
17022500 |
1 |
|
|
T22 |
50 |
|
T23 |
92935 |
|
T24 |
142 |
| auto[1] |
1024875 |
1 |
|
|
T23 |
6378 |
|
T24 |
4 |
|
T26 |
126 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10050094 |
1 |
|
|
T22 |
47 |
|
T23 |
53019 |
|
T24 |
63 |
| auto[1] |
7997281 |
1 |
|
|
T22 |
3 |
|
T23 |
46294 |
|
T24 |
83 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
3481116 |
1 |
|
|
T23 |
20179 |
|
T24 |
19 |
|
T26 |
260 |
| auto[1] |
auto[0] |
auto[1] |
511326 |
1 |
|
|
T23 |
3281 |
|
T26 |
66 |
|
T30 |
54 |
| auto[1] |
auto[1] |
auto[0] |
3491290 |
1 |
|
|
T22 |
3 |
|
T23 |
19737 |
|
T24 |
60 |
| auto[1] |
auto[1] |
auto[1] |
513549 |
1 |
|
|
T23 |
3097 |
|
T24 |
4 |
|
T26 |
60 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10065599 |
1 |
|
|
T22 |
46 |
|
T23 |
54177 |
|
T24 |
65 |
| auto[1] |
7981776 |
1 |
|
|
T22 |
4 |
|
T23 |
45136 |
|
T24 |
81 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
17021378 |
1 |
|
|
T22 |
50 |
|
T23 |
92894 |
|
T24 |
140 |
| auto[1] |
1025997 |
1 |
|
|
T23 |
6419 |
|
T24 |
6 |
|
T26 |
178 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10036685 |
1 |
|
|
T22 |
43 |
|
T23 |
53556 |
|
T24 |
96 |
| auto[1] |
8010690 |
1 |
|
|
T22 |
7 |
|
T23 |
45757 |
|
T24 |
50 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
3504824 |
1 |
|
|
T22 |
4 |
|
T23 |
20203 |
|
T24 |
20 |
| auto[1] |
auto[0] |
auto[1] |
516458 |
1 |
|
|
T23 |
3291 |
|
T24 |
4 |
|
T26 |
116 |
| auto[1] |
auto[1] |
auto[0] |
3479869 |
1 |
|
|
T22 |
3 |
|
T23 |
19135 |
|
T24 |
24 |
| auto[1] |
auto[1] |
auto[1] |
509539 |
1 |
|
|
T23 |
3128 |
|
T24 |
2 |
|
T26 |
62 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10041184 |
1 |
|
|
T22 |
50 |
|
T23 |
54691 |
|
T24 |
95 |
| auto[1] |
8006191 |
1 |
|
|
T23 |
44622 |
|
T24 |
51 |
|
T26 |
854 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
17015528 |
1 |
|
|
T22 |
50 |
|
T23 |
92926 |
|
T24 |
139 |
| auto[1] |
1031847 |
1 |
|
|
T23 |
6387 |
|
T24 |
7 |
|
T26 |
192 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10007932 |
1 |
|
|
T22 |
50 |
|
T23 |
53711 |
|
T24 |
55 |
| auto[1] |
8039443 |
1 |
|
|
T23 |
45602 |
|
T24 |
91 |
|
T26 |
1031 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
3516140 |
1 |
|
|
T23 |
20029 |
|
T24 |
66 |
|
T26 |
493 |
| auto[1] |
auto[0] |
auto[1] |
518837 |
1 |
|
|
T23 |
3268 |
|
T24 |
5 |
|
T26 |
113 |
| auto[1] |
auto[1] |
auto[0] |
3491456 |
1 |
|
|
T23 |
19186 |
|
T24 |
18 |
|
T26 |
346 |
| auto[1] |
auto[1] |
auto[1] |
513010 |
1 |
|
|
T23 |
3119 |
|
T24 |
2 |
|
T26 |
79 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10076289 |
1 |
|
|
T22 |
50 |
|
T23 |
56395 |
|
T24 |
76 |
| auto[1] |
7971086 |
1 |
|
|
T23 |
42918 |
|
T24 |
70 |
|
T26 |
929 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
17025427 |
1 |
|
|
T22 |
50 |
|
T23 |
93276 |
|
T24 |
139 |
| auto[1] |
1021948 |
1 |
|
|
T23 |
6037 |
|
T24 |
7 |
|
T26 |
205 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10067133 |
1 |
|
|
T22 |
43 |
|
T23 |
54999 |
|
T24 |
57 |
| auto[1] |
7980242 |
1 |
|
|
T22 |
7 |
|
T23 |
44314 |
|
T24 |
89 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
3480908 |
1 |
|
|
T22 |
7 |
|
T23 |
19302 |
|
T24 |
49 |
| auto[1] |
auto[0] |
auto[1] |
510734 |
1 |
|
|
T23 |
3122 |
|
T24 |
5 |
|
T26 |
102 |
| auto[1] |
auto[1] |
auto[0] |
3477386 |
1 |
|
|
T23 |
18975 |
|
T24 |
33 |
|
T26 |
392 |
| auto[1] |
auto[1] |
auto[1] |
511214 |
1 |
|
|
T23 |
2915 |
|
T24 |
2 |
|
T26 |
103 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10060461 |
1 |
|
|
T22 |
47 |
|
T23 |
55683 |
|
T24 |
102 |
| auto[1] |
7986914 |
1 |
|
|
T22 |
3 |
|
T23 |
43630 |
|
T24 |
44 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
17024630 |
1 |
|
|
T22 |
50 |
|
T23 |
92990 |
|
T24 |
143 |
| auto[1] |
1022745 |
1 |
|
|
T23 |
6323 |
|
T24 |
3 |
|
T26 |
135 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10054734 |
1 |
|
|
T22 |
49 |
|
T23 |
53963 |
|
T24 |
92 |
| auto[1] |
7992641 |
1 |
|
|
T22 |
1 |
|
T23 |
45350 |
|
T24 |
54 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
3501602 |
1 |
|
|
T22 |
1 |
|
T23 |
19705 |
|
T24 |
33 |
| auto[1] |
auto[0] |
auto[1] |
514781 |
1 |
|
|
T23 |
3247 |
|
T24 |
2 |
|
T26 |
90 |
| auto[1] |
auto[1] |
auto[0] |
3468294 |
1 |
|
|
T23 |
19322 |
|
T24 |
18 |
|
T26 |
224 |
| auto[1] |
auto[1] |
auto[1] |
507964 |
1 |
|
|
T23 |
3076 |
|
T24 |
1 |
|
T26 |
45 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9989213 |
1 |
|
|
T22 |
30 |
|
T23 |
55435 |
|
T24 |
38 |
| auto[1] |
8058162 |
1 |
|
|
T22 |
20 |
|
T23 |
43878 |
|
T24 |
108 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
17030324 |
1 |
|
|
T22 |
50 |
|
T23 |
93360 |
|
T24 |
142 |
| auto[1] |
1017051 |
1 |
|
|
T23 |
5953 |
|
T24 |
4 |
|
T26 |
202 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10091897 |
1 |
|
|
T22 |
46 |
|
T23 |
56273 |
|
T24 |
87 |
| auto[1] |
7955478 |
1 |
|
|
T22 |
4 |
|
T23 |
43040 |
|
T24 |
59 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
3447370 |
1 |
|
|
T22 |
1 |
|
T23 |
19283 |
|
T24 |
10 |
| auto[1] |
auto[0] |
auto[1] |
505727 |
1 |
|
|
T23 |
3123 |
|
T24 |
2 |
|
T26 |
119 |
| auto[1] |
auto[1] |
auto[0] |
3491057 |
1 |
|
|
T22 |
3 |
|
T23 |
17804 |
|
T24 |
45 |
| auto[1] |
auto[1] |
auto[1] |
511324 |
1 |
|
|
T23 |
2830 |
|
T24 |
2 |
|
T26 |
83 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10085244 |
1 |
|
|
T22 |
50 |
|
T23 |
54385 |
|
T24 |
106 |
| auto[1] |
7962131 |
1 |
|
|
T23 |
44928 |
|
T24 |
40 |
|
T26 |
1203 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
17020037 |
1 |
|
|
T22 |
50 |
|
T23 |
93074 |
|
T24 |
143 |
| auto[1] |
1027338 |
1 |
|
|
T23 |
6239 |
|
T24 |
3 |
|
T26 |
139 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10023642 |
1 |
|
|
T22 |
45 |
|
T23 |
54166 |
|
T24 |
87 |
| auto[1] |
8023733 |
1 |
|
|
T22 |
5 |
|
T23 |
45147 |
|
T24 |
59 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
3528962 |
1 |
|
|
T22 |
5 |
|
T23 |
20037 |
|
T24 |
31 |
| auto[1] |
auto[0] |
auto[1] |
519192 |
1 |
|
|
T23 |
3317 |
|
T24 |
1 |
|
T26 |
57 |
| auto[1] |
auto[1] |
auto[0] |
3467433 |
1 |
|
|
T23 |
18871 |
|
T24 |
25 |
|
T26 |
389 |
| auto[1] |
auto[1] |
auto[1] |
508146 |
1 |
|
|
T23 |
2922 |
|
T24 |
2 |
|
T26 |
82 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10048838 |
1 |
|
|
T22 |
39 |
|
T23 |
52797 |
|
T24 |
73 |
| auto[1] |
7998537 |
1 |
|
|
T22 |
11 |
|
T23 |
46516 |
|
T24 |
73 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
17017706 |
1 |
|
|
T22 |
50 |
|
T23 |
93272 |
|
T24 |
142 |
| auto[1] |
1029669 |
1 |
|
|
T23 |
6041 |
|
T24 |
4 |
|
T26 |
200 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10004796 |
1 |
|
|
T22 |
47 |
|
T23 |
55838 |
|
T24 |
104 |
| auto[1] |
8042579 |
1 |
|
|
T22 |
3 |
|
T23 |
43475 |
|
T24 |
42 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
3495103 |
1 |
|
|
T23 |
18479 |
|
T24 |
16 |
|
T26 |
460 |
| auto[1] |
auto[0] |
auto[1] |
513329 |
1 |
|
|
T23 |
2993 |
|
T24 |
2 |
|
T26 |
94 |
| auto[1] |
auto[1] |
auto[0] |
3517807 |
1 |
|
|
T22 |
3 |
|
T23 |
18955 |
|
T24 |
22 |
| auto[1] |
auto[1] |
auto[1] |
516340 |
1 |
|
|
T23 |
3048 |
|
T24 |
2 |
|
T26 |
106 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10059151 |
1 |
|
|
T22 |
39 |
|
T23 |
54882 |
|
T24 |
73 |
| auto[1] |
7988224 |
1 |
|
|
T22 |
11 |
|
T23 |
44431 |
|
T24 |
73 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
17027999 |
1 |
|
|
T22 |
50 |
|
T23 |
93142 |
|
T24 |
137 |
| auto[1] |
1019376 |
1 |
|
|
T23 |
6171 |
|
T24 |
9 |
|
T26 |
154 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10077116 |
1 |
|
|
T22 |
46 |
|
T23 |
54516 |
|
T24 |
39 |
| auto[1] |
7970259 |
1 |
|
|
T22 |
4 |
|
T23 |
44797 |
|
T24 |
107 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
3468744 |
1 |
|
|
T22 |
4 |
|
T23 |
19919 |
|
T24 |
42 |
| auto[1] |
auto[0] |
auto[1] |
508183 |
1 |
|
|
T23 |
3106 |
|
T24 |
3 |
|
T26 |
76 |
| auto[1] |
auto[1] |
auto[0] |
3482139 |
1 |
|
|
T23 |
18707 |
|
T24 |
56 |
|
T26 |
333 |
| auto[1] |
auto[1] |
auto[1] |
511193 |
1 |
|
|
T23 |
3065 |
|
T24 |
6 |
|
T26 |
78 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10069458 |
1 |
|
|
T22 |
42 |
|
T23 |
55407 |
|
T24 |
129 |
| auto[1] |
7977917 |
1 |
|
|
T22 |
8 |
|
T23 |
43906 |
|
T24 |
17 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
17028605 |
1 |
|
|
T22 |
50 |
|
T23 |
93219 |
|
T24 |
140 |
| auto[1] |
1018770 |
1 |
|
|
T23 |
6094 |
|
T24 |
6 |
|
T26 |
176 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10086876 |
1 |
|
|
T22 |
50 |
|
T23 |
54961 |
|
T24 |
66 |
| auto[1] |
7960499 |
1 |
|
|
T23 |
44352 |
|
T24 |
80 |
|
T26 |
928 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
3497332 |
1 |
|
|
T23 |
19853 |
|
T24 |
67 |
|
T26 |
429 |
| auto[1] |
auto[0] |
auto[1] |
514699 |
1 |
|
|
T23 |
3179 |
|
T24 |
6 |
|
T26 |
97 |
| auto[1] |
auto[1] |
auto[0] |
3444397 |
1 |
|
|
T23 |
18405 |
|
T24 |
7 |
|
T26 |
323 |
| auto[1] |
auto[1] |
auto[1] |
504071 |
1 |
|
|
T23 |
2915 |
|
T26 |
79 |
|
T30 |
56 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10084336 |
1 |
|
|
T22 |
42 |
|
T23 |
55725 |
|
T24 |
81 |
| auto[1] |
7963039 |
1 |
|
|
T22 |
8 |
|
T23 |
43588 |
|
T24 |
65 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
17027790 |
1 |
|
|
T22 |
50 |
|
T23 |
93553 |
|
T24 |
143 |
| auto[1] |
1019585 |
1 |
|
|
T23 |
5760 |
|
T24 |
3 |
|
T26 |
199 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10069269 |
1 |
|
|
T22 |
42 |
|
T23 |
57170 |
|
T24 |
106 |
| auto[1] |
7978106 |
1 |
|
|
T22 |
8 |
|
T23 |
42143 |
|
T24 |
40 |