Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10014952 |
1 |
|
|
T22 |
26 |
|
T23 |
52569 |
|
T24 |
95 |
| auto[1] |
8032423 |
1 |
|
|
T22 |
24 |
|
T23 |
46744 |
|
T24 |
51 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
17021776 |
1 |
|
|
T22 |
50 |
|
T23 |
92896 |
|
T24 |
143 |
| auto[1] |
1025599 |
1 |
|
|
T23 |
6417 |
|
T24 |
3 |
|
T26 |
161 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10044803 |
1 |
|
|
T22 |
46 |
|
T23 |
53311 |
|
T24 |
79 |
| auto[1] |
8002572 |
1 |
|
|
T22 |
4 |
|
T23 |
46002 |
|
T24 |
67 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
3472688 |
1 |
|
|
T22 |
4 |
|
T23 |
19136 |
|
T24 |
46 |
| auto[1] |
auto[0] |
auto[1] |
510006 |
1 |
|
|
T23 |
3105 |
|
T24 |
2 |
|
T26 |
58 |
| auto[1] |
auto[1] |
auto[0] |
3504285 |
1 |
|
|
T23 |
20449 |
|
T24 |
18 |
|
T26 |
451 |
| auto[1] |
auto[1] |
auto[1] |
515593 |
1 |
|
|
T23 |
3312 |
|
T24 |
1 |
|
T26 |
103 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |