Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10050704 |
1 |
|
|
T22 |
43 |
|
T23 |
56037 |
|
T24 |
92 |
| auto[1] |
7996671 |
1 |
|
|
T22 |
7 |
|
T23 |
43276 |
|
T24 |
54 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
17027351 |
1 |
|
|
T22 |
50 |
|
T23 |
92904 |
|
T24 |
143 |
| auto[1] |
1020024 |
1 |
|
|
T23 |
6409 |
|
T24 |
3 |
|
T26 |
145 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10068971 |
1 |
|
|
T22 |
45 |
|
T23 |
54166 |
|
T24 |
79 |
| auto[1] |
7978404 |
1 |
|
|
T22 |
5 |
|
T23 |
45147 |
|
T24 |
67 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
3496635 |
1 |
|
|
T22 |
5 |
|
T23 |
19973 |
|
T24 |
43 |
| auto[1] |
auto[0] |
auto[1] |
512400 |
1 |
|
|
T23 |
3277 |
|
T24 |
3 |
|
T26 |
74 |
| auto[1] |
auto[1] |
auto[0] |
3461745 |
1 |
|
|
T23 |
18765 |
|
T24 |
21 |
|
T26 |
298 |
| auto[1] |
auto[1] |
auto[1] |
507624 |
1 |
|
|
T23 |
3132 |
|
T26 |
71 |
|
T30 |
61 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |